[TTI] Allow passing ArrayRef of context instructions (NFC).

[fhahn]

Summary

TTI-based alternative to D132872.

This is to allow the SLP vectorizer to pass extra context instructions
for a vector bundle.

This patch just adds the plumbing, follow-up patches linked in the stack
actually make use of the new functionality.

See discussion at D132872.

[ABataev]

llvm/include/llvm/Analysis/TargetTransformInfo.h

1083

= None

2290

= None

llvm/include/llvm/CodeGen/BasicTTIImpl.h

824

= None

[dmgreen]

This seems to mess up the interface to TTI quite a lot. Are there any other cases than the SLP vectorizer where se would pass a vector of Instructions?

The CxtI only has to be a context. It gets a bit fuzzy, but could we just pass the first instruction if it is similar enough to the other instructions in the TreeEntry? It looks like the first item is already passed in at the moment.

Also, on a conceptual level - mul's are expensive, addition is relatively cheap. Would it make sense to try and mark the fadd as cheap by looking at the operands? (When I've tried in the past the performance wasn't great).

[fhahn]

In D132966#3760480, @dmgreen wrote:

This seems to mess up the interface to TTI quite a lot. Are there any other cases than the SLP vectorizer where se would pass a vector of Instructions?

Yeah the new argument is specifically to support SLP's use case. I don't think other passes are in a similar situation at the moment. There's also a version that keeps the logic in SLP: D132872, but @ABataev argued to have this generally available.

The CxtI only has to be a context. It gets a bit fuzzy, but could we just pass the first instruction if it is similar enough to the other instructions in the TreeEntry? It looks like the first item is already passed in at the moment.

I think all instructiosn in a TreeEntry should be very similar in almost all cases (same opcode). But here we need to specifically look at the users to determine if the users of all instructions in the bundle will allow fusion.

Now while spelling this out, maybe we could instead fuse elegible FMUL + FADD/FSUB TreeEntry nodes directly to a single FMULADD/SUB TreeEntry intead of checking for fusion opportunities for the vector version? @ABataev do you think that would be easily do-able?

Also, on a conceptual level - mul's are expensive, addition is relatively cheap. Would it make sense to try and mark the fadd as cheap by looking at the operands? (When I've tried in the past the performance wasn't great).

I think when I tried this a while ago in the other direction it turned out less profitable.

[ABataev]

In D132966#3761409, @fhahn wrote:

In D132966#3760480, @dmgreen wrote:

This seems to mess up the interface to TTI quite a lot. Are there any other cases than the SLP vectorizer where se would pass a vector of Instructions?

Yeah the new argument is specifically to support SLP's use case. I don't think other passes are in a similar situation at the moment. There's also a version that keeps the logic in SLP: D132872, but @ABataev argued to have this generally available.

Maybe add a specific function which returns bool if preferable to use FMA instead?

The CxtI only has to be a context. It gets a bit fuzzy, but could we just pass the first instruction if it is similar enough to the other instructions in the TreeEntry? It looks like the first item is already passed in at the moment.

I think all instructiosn in a TreeEntry should be very similar in almost all cases (same opcode). But here we need to specifically look at the users to determine if the users of all instructions in the bundle will allow fusion.

Now while spelling this out, maybe we could instead fuse elegible FMUL + FADD/FSUB TreeEntry nodes directly to a single FMULADD/SUB TreeEntry intead of checking for fusion opportunities for the vector version? @ABataev do you think that would be easily do-able?

Everything is doable, it is just a question of time. Need to adjust the cost somehow, add a flag (probably!) to the node(s) for possible "FMAsation" and change the codegen to emit FMA instead of fmul+fadd/fsub.

Also, on a conceptual level - mul's are expensive, addition is relatively cheap. Would it make sense to try and mark the fadd as cheap by looking at the operands? (When I've tried in the past the performance wasn't great).

I think when I tried this a while ago in the other direction it turned out less profitable.

[fhahn]

In D132966#3761479, @ABataev wrote:

In D132966#3761409, @fhahn wrote:

In D132966#3760480, @dmgreen wrote:

This seems to mess up the interface to TTI quite a lot. Are there any other cases than the SLP vectorizer where se would pass a vector of Instructions?

Yeah the new argument is specifically to support SLP's use case. I don't think other passes are in a similar situation at the moment. There's also a version that keeps the logic in SLP: D132872, but @ABataev argued to have this generally available.

Maybe add a specific function which returns bool if preferable to use FMA instead?

I think the issue here is that is not as simple as asking a boolean question.

We need to adjust both the scalar and vector costs, depending on whether either can use FMAs. I think if we support this in TTI, then it should be integrated into the existing APIs. If we add a new interface just geared at the SLP use case, general TTI users won't benefit anyways and then IMO it would be better to keep SLP logic in SLPVectorizer.cpp, at least initially.

The CxtI only has to be a context. It gets a bit fuzzy, but could we just pass the first instruction if it is similar enough to the other instructions in the TreeEntry? It looks like the first item is already passed in at the moment.

I think all instructiosn in a TreeEntry should be very similar in almost all cases (same opcode). But here we need to specifically look at the users to determine if the users of all instructions in the bundle will allow fusion.

Now while spelling this out, maybe we could instead fuse elegible FMUL + FADD/FSUB TreeEntry nodes directly to a single FMULADD/SUB TreeEntry intead of checking for fusion opportunities for the vector version? @ABataev do you think that would be easily do-able?

Everything is doable, it is just a question of time. Need to adjust the cost somehow, add a flag (probably!) to the node(s) for possible "FMAsation" and change the codegen to emit FMA instead of fmul+fadd/fsub.

Right, the question is what the best path forward is to incrementally improve the situation without adding too much churn until we know the cost-based decision works well for a range of targets.

llvm/include/llvm/Analysis/TargetTransformInfo.h

1083

In the inline above, an explicit ArrayRef constructor is used. I updated the code here to do the same.

2290

No default arg needed here it seems, I removed it.

llvm/include/llvm/CodeGen/BasicTTIImpl.h

824

In the inline above, an explicit ArrayRef constructor is used. I updated the code here to do the same.

[ABataev]

In D132966#3761614, @fhahn wrote:

In D132966#3761479, @ABataev wrote:

In D132966#3761409, @fhahn wrote:

In D132966#3760480, @dmgreen wrote:

This seems to mess up the interface to TTI quite a lot. Are there any other cases than the SLP vectorizer where se would pass a vector of Instructions?

Yeah the new argument is specifically to support SLP's use case. I don't think other passes are in a similar situation at the moment. There's also a version that keeps the logic in SLP: D132872, but @ABataev argued to have this generally available.

Maybe add a specific function which returns bool if preferable to use FMA instead?

I think the issue here is that is not as simple as asking a boolean question.

We need to adjust both the scalar and vector costs, depending on whether either can use FMAs. I think if we support this in TTI, then it should be integrated into the existing APIs.

Agree, that's why I thought it is better to make it part of TTI.

If we add a new interface just geared at the SLP use case, general TTI users won't benefit anyways and then IMO it would be better to keep SLP logic in SLPVectorizer.cpp, at least initially.

We already have SLP specific functions (at least for now) in TTI.

The CxtI only has to be a context. It gets a bit fuzzy, but could we just pass the first instruction if it is similar enough to the other instructions in the TreeEntry? It looks like the first item is already passed in at the moment.

I think all instructiosn in a TreeEntry should be very similar in almost all cases (same opcode). But here we need to specifically look at the users to determine if the users of all instructions in the bundle will allow fusion.

Now while spelling this out, maybe we could instead fuse elegible FMUL + FADD/FSUB TreeEntry nodes directly to a single FMULADD/SUB TreeEntry intead of checking for fusion opportunities for the vector version? @ABataev do you think that would be easily do-able?

Everything is doable, it is just a question of time. Need to adjust the cost somehow, add a flag (probably!) to the node(s) for possible "FMAsation" and change the codegen to emit FMA instead of fmul+fadd/fsub.

Right, the question is what the best path forward is to incrementally improve the situation without adding too much churn until we know the cost-based decision works well for a range of targets.

The cost still needs to be adjusted, before we do actual replacement.

[wjschmidt]

llvm/include/llvm/Analysis/TargetTransformInfo.h

2292

When applying this patch series, I see compilation errors like this:

In file included from /localdisk2/schmidtw/llvm-project/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h:22,

from /localdisk2/schmidtw/llvm-project/llvm/lib/Target/Lanai/La

naiTargetMachine.cpp:17:
/localdisk2/schmidtw/llvm-project/llvm/include/llvm/Analysis/TargetTransformInfo
.h: In instantiation of ‘llvm::InstructionCost llvm::TargetTransformInfo::Model<
T>::getArithmeticInstrCost(unsigned int, llvm::Type*, llvm::TargetTransformInfo:
:TargetCostKind, llvm::TargetTransformInfo::OperandValueInfo, llvm::TargetTransf
ormInfo::OperandValueInfo, llvm::ArrayRef<const llvm::Value*>, llvm::ArrayRef<co
nst llvm::Instruction*>) [with T = llvm::LanaiTTIImpl]’:
/localdisk2/schmidtw/llvm-project/llvm/include/llvm/Analysis/TargetTransformInfo
.h:2308:3: required from here
/localdisk2/schmidtw/llvm-project/llvm/include/llvm/Analysis/TargetTransformInfo
.h:2314:46: error: cannot convert ‘llvm::ArrayRef<const llvm::Instruction*>’ to
‘const llvm::Instruction*’
2314 | Args, CxtIs);

|                                              ^~~~~
|                                              |
|                                              llvm::ArrayRef<const llvm::

Instruction*>
In file included from /localdisk2/schmidtw/llvm-project/llvm/lib/Target/Lanai/La
naiTargetMachine.cpp:17:
/localdisk2/schmidtw/llvm-project/llvm/lib/Target/Lanai/LanaiTargetTransformInfo
.h:98:26: note: initializing argument 7 of ‘llvm::InstructionCost llvm::LanaiT
TIImpl::getArithmeticInstrCost(unsigned int, llvm::Type*, llvm::TargetTransformI
nfo::TargetCostKind, llvm::TargetTransformInfo::OperandValueInfo, llvm::TargetTr
ansformInfo::OperandValueInfo, llvm::ArrayRef<const llvm::Value*>, const llvm::I
nstruction*)’

98 |       const Instruction *CxtI = nullptr) {
   |       ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~

This occurs for Lanai, SystemZ, PowerPC, Hexagon, BPF, and NVPTX.

llvm/include/llvm/CodeGen/BasicTTIImpl.h

884

When applying this patch series, I see compilation errors for various targets stemming from this. Example:

In file included from /localdisk2/schmidtw/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h:23, from /localdisk2/schmidtw/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp:15:
/localdisk2/schmidtw/llvm-project/llvm/include/llvm/CodeGen/BasicTTIImpl.h: In i
nstantiation of ‘llvm::InstructionCost llvm::BasicTTIImplBase<T>::getArithmeticI
nstrCost(unsigned int, llvm::Type*, llvm::TargetTransformInfo::TargetCostKind, llvm::TargetTransformInfo::OperandValueInfo, llvm::TargetTransformInfo::OperandValueInfo, llvm::ArrayRef<const llvm::Value*>, llvm::ArrayRef<const llvm::Instruct
ion*>) [with T = llvm::WebAssemblyTTIImpl]’: /localdisk2/schmidtw/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyTargetT
ransformInfo.cpp:60:45: required from here
/localdisk2/schmidtw/llvm-project/llvm/include/llvm/CodeGen/BasicTTIImpl.h:884:1
1: error: cannot convert ‘llvm::ArrayRef<const llvm::Instruction*>’ to ‘const ll
vm::Instruction*’

884 |           CxtIs);
    |           ^~~~~
    |           |
    |           llvm::ArrayRef<const llvm::Instruction*>

/localdisk2/schmidtw/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyTargetT
ransformInfo.cpp:57:24: note: initializing argument 7 of ‘llvm::InstructionCos
t llvm::WebAssemblyTTIImpl::getArithmeticInstrCost(unsigned int, llvm::Type*, ll
vm::TargetTransformInfo::TargetCostKind, llvm::TargetTransformInfo::OperandValue
Info, llvm::TargetTransformInfo::OperandValueInfo, llvm::ArrayRef<const llvm::Va
lue*>, const llvm::Instruction*)’

57 |     const Instruction *CxtI) {
   |     ~~~~~~~~~~~~~~~~~~~^~~~

Appears for WebAssembly, Lanai, SystemZ, Hexagon, NVPTX, PowerPC, BPF, and AMDGPU.

llvm/include/llvm/Analysis/TargetTransformInfo.h

public:
   /// \p CxtI is the optional original context instruction, if one exists, to
   /// provide even more information.
   InstructionCost getArithmeticInstrCost(
       unsigned Opcode, Type *Ty,
       TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput,
       TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None},
       TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None},
       ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
-      const Instruction *CxtI = nullptr) const;
+      ArrayRef<const Instruction *> CxtIs = ArrayRef<const Instruction *>()) const;
 
   /// \return The cost of a shuffle instruction of kind Kind and of type Tp.
   /// The exact mask may be passed as Mask, or else the array will be empty.
   /// The index and subtype parameters are used by the subvector insertion and
   /// extraction shuffle kinds to show the insert/extract point and the type of
   /// the subvector being inserted/extracted. The operands of the shuffle can be
   /// passed through \p Args, which helps improve the cost estimation in some
   /// cases, like in broadcast loads.
public:
 
   /// \return if target want to issue a prefetch in address space \p AS.
   virtual bool shouldPrefetchAddressSpace(unsigned AS) const = 0;
 
   virtual unsigned getMaxInterleaveFactor(unsigned VF) = 0;
   virtual InstructionCost getArithmeticInstrCost(
       unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
       OperandValueInfo Opd1Info, OperandValueInfo Opd2Info,
-      ArrayRef<const Value *> Args, const Instruction *CxtI = nullptr) = 0;
+      ArrayRef<const Value *> Args, ArrayRef<const Instruction *> CxtIs) = 0;
 
   virtual InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp,
                                          ArrayRef<int> Mask,
                                          TTI::TargetCostKind CostKind,
                                          int Index, VectorType *SubTp,
                                          ArrayRef<const Value *> Args) = 0;
   virtual InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst,
                                            Type *Src, CastContextHint CCH,
unsigned getMaxInterleaveFactor(unsigned VF) override {
     return Impl.getMaxInterleaveFactor(VF);
   }
   unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
                                             unsigned &JTSize,
                                             ProfileSummaryInfo *PSI,
                                             BlockFrequencyInfo *BFI) override {
     return Impl.getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
   }
-  InstructionCost getArithmeticInstrCost(
-      unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
+  InstructionCost
+  getArithmeticInstrCost(unsigned Opcode, Type *Ty,
+                         TTI::TargetCostKind CostKind,
                          OperandValueInfo Opd1Info, OperandValueInfo Opd2Info,
                          ArrayRef<const Value *> Args,
-      const Instruction *CxtI = nullptr) override {
+                         ArrayRef<const Instruction *> CxtIs) override {
     return Impl.getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
-                                       Args, CxtI);
+                                       Args, CxtIs);
   }
 
   InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp,
                                  ArrayRef<int> Mask,
                                  TTI::TargetCostKind CostKind, int Index,
                                  VectorType *SubTp,
                                  ArrayRef<const Value *> Args) override {
     return Impl.getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp, Args);

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

public:
   bool enableWritePrefetching() const { return false; }
   bool shouldPrefetchAddressSpace(unsigned AS) const { return !AS; }
 
   unsigned getMaxInterleaveFactor(unsigned VF) const { return 1; }
 
   InstructionCost getArithmeticInstrCost(
       unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
       TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info,
-      ArrayRef<const Value *> Args,
-      const Instruction *CxtI = nullptr) const {
+      ArrayRef<const Value *> Args, ArrayRef<const Instruction *> CxtIs) const {
     // FIXME: A number of transformation tests seem to require these values
     // which seems a little odd for how arbitary there are.
     switch (Opcode) {
     default:
       break;
     case Instruction::FDiv:
     case Instruction::FRem:
     case Instruction::SDiv:

llvm/include/llvm/CodeGen/BasicTTIImpl.h

public:
 
   unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }
 
   InstructionCost getArithmeticInstrCost(
       unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
       TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None},
       TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None},
       ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
-      const Instruction *CxtI = nullptr) {
+      ArrayRef<const Instruction *> CxtIs = ArrayRef<const Instruction *>()) {
     // Check if any of the operands are vector operands.
     const TargetLoweringBase *TLI = getTLI();
     int ISD = TLI->InstructionOpcodeToISD(Opcode);
     assert(ISD && "Invalid opcode");
 
     // TODO: Handle more cost kinds.
     if (CostKind != TTI::TCK_RecipThroughput)
-      return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind,
-                                           Opd1Info, Opd2Info,
-                                           Args, CxtI);
+      return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info,
+                                           Opd2Info, Args, CxtIs);
 
     std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
 
     bool IsFloat = Ty->isFPOrFPVectorTy();
     // Assume that floating point arithmetic operations cost twice as much as
     // integer operations.
     InstructionCost OpCost = (IsFloat ? 2 : 1);
 
InstructionCost getArithmeticInstrCost(
     if (isa<ScalableVectorType>(Ty))
       return InstructionCost::getInvalid();
 
     // Else, assume that we need to scalarize this op.
     // TODO: If one of the types get legalized by splitting, handle this
     // similarly to what getCastInstrCost() does.
     if (auto *VTy = dyn_cast<FixedVectorType>(Ty)) {
       InstructionCost Cost = thisT()->getArithmeticInstrCost(
-          Opcode, VTy->getScalarType(), CostKind, Opd1Info, Opd2Info,
-          Args, CxtI);
+          Opcode, VTy->getScalarType(), CostKind, Opd1Info, Opd2Info, Args,
+          CxtIs);
       // Return the cost of multiple scalar invocation plus the cost of
       // inserting and extracting the values.
       SmallVector<Type *> Tys(Args.size(), Ty);
       return getScalarizationOverhead(VTy, Args, Tys) +
              VTy->getNumElements() * Cost;
     }
 
     // We don't know anything about this scalar instruction.

llvm/lib/Analysis/TargetTransformInfo.cpp

if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
     OpInfo = OK_UniformValue;
 
   return {OpInfo, OpProps};
 }
 
 InstructionCost TargetTransformInfo::getArithmeticInstrCost(
     unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
     OperandValueInfo Op1Info, OperandValueInfo Op2Info,
-    ArrayRef<const Value *> Args, const Instruction *CxtI) const {
+    ArrayRef<const Value *> Args, ArrayRef<const Instruction *> CxtIs) const {
   InstructionCost Cost =
       TTIImpl->getArithmeticInstrCost(Opcode, Ty, CostKind,
                                       Op1Info, Op2Info,
-                                      Args, CxtI);
+                                      Args, CxtIs);
   assert(Cost >= 0 && "TTI should not produce negative costs!");
   return Cost;
 }
 
 InstructionCost TargetTransformInfo::getShuffleCost(
     ShuffleKind Kind, VectorType *Ty, ArrayRef<int> Mask,
     TTI::TargetCostKind CostKind, int Index, VectorType *SubTp,
     ArrayRef<const Value *> Args) const {

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h

public:
 
   InstructionCost getSpliceCost(VectorType *Tp, int Index);
 
   InstructionCost getArithmeticInstrCost(
       unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
       TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
       TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
       ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
-      const Instruction *CxtI = nullptr);
+      ArrayRef<const Instruction *> CxtIs = {});
 
   InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
                                             const SCEV *Ptr);
 
   InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
                                      CmpInst::Predicate VecPred,
                                      TTI::TargetCostKind CostKind,
                                      const Instruction *I = nullptr);

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

InstructionCost AArch64TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
 
   // All other insert/extracts cost this much.
   return ST->getVectorInsertExtractBaseCost();
 }
 
 InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
     unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
     TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
-    ArrayRef<const Value *> Args,
-    const Instruction *CxtI) {
+    ArrayRef<const Value *> Args, ArrayRef<const Instruction *> CxtIs) {
 
   // TODO: Handle more cost kinds.
   if (CostKind != TTI::TCK_RecipThroughput)
-    return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
-                                         Op2Info, Args, CxtI);
+    return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
+                                         Args, CxtIs);
 
   // Legalize the type.
   std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
   int ISD = TLI->InstructionOpcodeToISD(Opcode);
 
   switch (ISD) {
   default:
     return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,

llvm/lib/Target/ARM/ARMTargetTransformInfo.h

public:
   InstructionCost getAddressComputationCost(Type *Val, ScalarEvolution *SE,
                                             const SCEV *Ptr);
 
   InstructionCost getArithmeticInstrCost(
       unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
       TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
       TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
       ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
-      const Instruction *CxtI = nullptr);
+      ArrayRef<const Instruction *> CxtIs = {});
 
   InstructionCost
   getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
                   unsigned AddressSpace, TTI::TargetCostKind CostKind,
                   TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
                   const Instruction *I = nullptr);
 
   InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

int BaseCost = ST->hasMVEIntegerOps() && Tp->isVectorTy()
                      : 1;
   return BaseCost *
          BaseT::getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp);
 }
 
 InstructionCost ARMTTIImpl::getArithmeticInstrCost(
     unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
     TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
-    ArrayRef<const Value *> Args,
-    const Instruction *CxtI) {
+    ArrayRef<const Value *> Args, ArrayRef<const Instruction *> CxtIs) {
   int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
   if (ST->isThumb() && CostKind == TTI::TCK_CodeSize && Ty->isIntegerTy(1)) {
     // Make operations on i1 relatively expensive as this often involves
     // combining predicates. AND and XOR should be easier to handle with IT
     // blocks.
     switch (ISDOpcode) {
     default:
       break;
InstructionCost ARMTTIImpl::getArithmeticInstrCost(
   }
 
   // If this operation is a shift on arm/thumb2, it might well be folded into
   // the following instruction, hence having a cost of 0.
   auto LooksLikeAFreeShift = [&]() {
     if (ST->isThumb1Only() || Ty->isVectorTy())
       return false;
 
-    if (!CxtI || !CxtI->hasOneUse() || !CxtI->isShift())
+    if (CxtIs.size() != 1 || !CxtIs[0]->hasOneUse() || !CxtIs[0]->isShift())
       return false;
     if (!Op2Info.isUniform() || !Op2Info.isConstant())
       return false;
 
     // Folded into a ADC/ADD/AND/BIC/CMP/EOR/MVN/ORR/ORN/RSB/SBC/SUB
-    switch (cast<Instruction>(CxtI->user_back())->getOpcode()) {
+    switch (cast<Instruction>(CxtIs[0]->user_back())->getOpcode()) {
     case Instruction::Add:
     case Instruction::Sub:
     case Instruction::And:
     case Instruction::Xor:
     case Instruction::Or:
     case Instruction::ICmp:
       return true;
     default:

llvm/lib/Target/X86/X86TargetTransformInfo.h

public:
   TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const;
   unsigned getLoadStoreVecRegBitWidth(unsigned AS) const;
   unsigned getMaxInterleaveFactor(unsigned VF);
   InstructionCost getArithmeticInstrCost(
       unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
       TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
       TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
       ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
-      const Instruction *CxtI = nullptr);
+      ArrayRef<const Instruction *> CxtIs = {});
   InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
                                  ArrayRef<int> Mask,
                                  TTI::TargetCostKind CostKind, int Index,
                                  VectorType *SubTp,
                                  ArrayRef<const Value *> Args = None);
   InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
                                    TTI::CastContextHint CCH,
                                    TTI::TargetCostKind CostKind,

llvm/lib/Target/X86/X86TargetTransformInfo.cpp

if (ST->hasAVX())
     return 4;
 
   return 2;
 }
 
 InstructionCost X86TTIImpl::getArithmeticInstrCost(
     unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
     TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
-    ArrayRef<const Value *> Args,
-    const Instruction *CxtI) {
+    ArrayRef<const Value *> Args, ArrayRef<const Instruction *> CxtIs) {
 
   // vXi8 multiplications are always promoted to vXi16.
   if (Opcode == Instruction::Mul && Ty->isVectorTy() &&
       Ty->getScalarSizeInBits() == 8) {
     Type *WideVecTy =
         VectorType::getExtendedElementVectorType(cast<VectorType>(Ty));
     return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty,
                             TargetTransformInfo::CastContextHint::None,
if (CostKind == TTI::TCK_CodeSize) {
     case ISD::XOR:
       return LT.first;
       break;
     }
   }
 
   // Fallback to the default implementation.
   return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
-                                       Args, CxtI);
+                                       Args, CxtIs);
 }
 
 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
                                            VectorType *BaseTp,
                                            ArrayRef<int> Mask,
                                            TTI::TargetCostKind CostKind,
                                            int Index, VectorType *SubTp,
                                            ArrayRef<const Value *> Args) {