[LLDB][RISCV] Add more instruction decode and execute for EmulateInstructionRISCV

[Emmmer]

Summary

Add:

• most of instructions from RVI base instructions set.
• some instruction decode tests from objdump.

Further work:

• implement riscv imac extension.

[tzb99]

Upon this change, My lldb logging changes a bit. The instruction is not shown anymore, but stepping is still working. Is it as expected?

* thread #1, name = 'test.o', stop reason = signal SIGSTOP
    frame #0: 0x0000000000010528

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

35–39

Upon this change, My lldb logging changes a bit. The instruction is not shown anymore, but stepping is still working. Is it as expected?

* thread #1, name = 'test.o', stop reason = signal SIGSTOP
    frame #0: 0x0000000000010528

[Emmmer]

In D132789#3757018, @tzb99 wrote:

Upon this change, My lldb logging changes a bit. The instruction is not shown anymore, but stepping is still working. Is it as expected?

* thread #1, name = 'test.o', stop reason = signal SIGSTOP
    frame #0: 0x0000000000010528

I tried to reproduce but failed.
Could you please provide more information？
(for example: what is written in main, why use .o for debugging, and the command operations executed in lldb)

[tzb99]

In D132789#3757675, @Emmmer wrote:

In D132789#3757018, @tzb99 wrote:

Upon this change, My lldb logging changes a bit. The instruction is not shown anymore, but stepping is still working. Is it as expected?

* thread #1, name = 'test.o', stop reason = signal SIGSTOP
    frame #0: 0x0000000000010528

I tried to reproduce but failed.
Could you please provide more information？
(for example: what is written in main, why use .o for debugging, and the command operations executed in lldb)

Sure. My testing script is:

#include<stdio.h>
void fun2() {
	printf("Enter fun2\n");
}
int fun1() {
	printf("Enter fun1\n");
	fun2();
	return 10;}

int main(int argc, char **argv) {
	int a = fun1();
	int b = 15;
       	printf("hello world\n");
	return 0;
}

So which file format should be used for debugging? My command option on the client side is:

lldb-server g 0.0.0.0:2345 test.o

On the lldb (x86) side is:

lldb
gdb-remote 2345
s

The objdump of my test.o file is:

0000000000010528 <_start>:
   10528:       02e000ef                jal     ra,10556 <load_gp>
   1052c:       87aa                    mv      a5,a0
   1052e:       00000517                auipc   a0,0x0
   10532:       14650513                addi    a0,a0,326 # 10674 <main>
   10536:       6582                    ld      a1,0(sp)
   10538:       0030                    addi    a2,sp,8
   1053a:       ff017113                andi    sp,sp,-16
   1053e:       00000697                auipc   a3,0x0
   10542:       68068693                addi    a3,a3,1664 # 10bbe <__libc_csu_init>
   10546:       00000717                auipc   a4,0x0

My compilation flavor should be:

riscv64-unknown-linux-gnu-gcc -g -o test.o hello.c \
-static -static-libgcc -static-libstdc++ -march=rv64imafd

Please let me know if you need more information!

[Emmmer]

In D132789#3759892, @tzb99 wrote:

In D132789#3757675, @Emmmer wrote:

In D132789#3757018, @tzb99 wrote:

Upon this change, My lldb logging changes a bit. The instruction is not shown anymore, but stepping is still working. Is it as expected?

* thread #1, name = 'test.o', stop reason = signal SIGSTOP
    frame #0: 0x0000000000010528

I tried to reproduce but failed.
Could you please provide more information？
(for example: what is written in main, why use .o for debugging, and the command operations executed in lldb)

Sure. My testing script is:

#include<stdio.h>
void fun2() {
	printf("Enter fun2\n");
}
int fun1() {
	printf("Enter fun1\n");
	fun2();
	return 10;}

int main(int argc, char **argv) {
	int a = fun1();
	int b = 15;
       	printf("hello world\n");
	return 0;
}

So which file format should be used for debugging? My command option on the client side is:

lldb-server g 0.0.0.0:2345 test.o

On the lldb (x86) side is:

lldb
gdb-remote 2345
s

The objdump of my test.o file is:

0000000000010528 <_start>:
   10528:       02e000ef                jal     ra,10556 <load_gp>
   1052c:       87aa                    mv      a5,a0
   1052e:       00000517                auipc   a0,0x0
   10532:       14650513                addi    a0,a0,326 # 10674 <main>
   10536:       6582                    ld      a1,0(sp)
   10538:       0030                    addi    a2,sp,8
   1053a:       ff017113                andi    sp,sp,-16
   1053e:       00000697                auipc   a3,0x0
   10542:       68068693                addi    a3,a3,1664 # 10bbe <__libc_csu_init>
   10546:       00000717                auipc   a4,0x0

My compilation flavor should be:

riscv64-unknown-linux-gnu-gcc -g -o test.o hello.c \
-static -static-libgcc -static-libstdc++ -march=rv64imafd

Please let me know if you need more information!

I coiped your test code to tzb.c

(on x86)

$ riscv64-unknown-linux-gnu-gcc -g -o tzb tzb.c \
  -static -static-libgcc -static-libstdc++ -march=rv64imafd

PS: -o usage is: -o <file>, it means place the output into <file>.

---

(on qemu-system-riscv64)

$ lldb
(lldb) gdb-remote 8888

(lldb) Process 5933 stopped
* thread #1, name = 'tzb', stop reason = signal SIGSTOP
    frame #0: 0x0000000000010528 tzb`_start at start.S:50
warning: This version of LLDB has no plugin for the language "assembler". Inspection of frame variables will be limited.

Then I tried to read DWARF in tzb, and dwarfdump report DW_AT_language is DW_LANG_Mips_Assembler, but DW_AT_language should be DW_LANG_C99.

---

It may be a bug caused by riscv-gnu-toolchain, and we can use this to avoid it.

(on qemu-system-riscv64)

$ gcc -g -o tzb tzb.c \
  -static -static-libgcc -static-libstdc++ -march=rv64imafd

$ lldb-server g 0.0.0.0:2345 tzb
Launched 'tzb' as process 6839...
lldb-server-local_build

(Switch to another tab)

$ lldb
(lldb) gdb-remote 2345

(lldb) Process 6839 stopped
* thread #1, name = 'tzb', stop reason = signal SIGSTOP
    frame #0: 0x0000000000010584 tzb`_start
tzb`_start:
->  0x10584 <+0>:  jal    48                    <--|
    0x10588 <+4>:  mv     a5, a0                <--|
    0x1058c <+8>:  auipc  a0, 121               <--|
    0x10590 <+12>: ld     a0, -980(a0)          <--| as expected
(lldb)

Then you can set breakpoints and go to where you want.

---

I copied some DWARF info that may be useful:

in cross-build elf file:

.debug_info

COMPILE_UNIT<header overall offset = 0x00000000>:
< 0><0x0000000c>  DW_TAG_compile_unit
                    DW_AT_stmt_list             0x00000000
                    DW_AT_low_pc                0x00010528
                    DW_AT_high_pc               <offset-from-lowpc>0x00000042
                    DW_AT_name                  ../sysdeps/riscv/start.S
                    DW_AT_comp_dir              /home/emmmer/git/riscv-gnu-toolchain/glibc/csu
                    DW_AT_producer              GNU AS 2.38
                    DW_AT_language              DW_LANG_Mips_Assembler

in native-build elf file:

.debug_info

COMPILE_UNIT<header overall offset = 0x00000000>:
< 0><0x0000000b>  DW_TAG_compile_unit
                    DW_AT_producer              GNU C17 10.3.1 -march=rv64imafd -mabi=lp64d -g
                    DW_AT_language              DW_LANG_C99
                    DW_AT_name                  tzb.c
                    DW_AT_comp_dir              /root
                    DW_AT_low_pc                0x000106ac
                    DW_AT_high_pc               <offset-from-lowpc>188
                    DW_AT_stmt_list             0x00000000

[DavidSpickett]

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

54

Is it worth putting an enable_if sizeof(T) <= 4 here? Just to prevent some potential silly mistakes.

56

I'm guessing that the int32->int64 could just be one cast to int64 but it does document the widening nicely so keep it.

66

This looks a lot like SextW but perhaps needing the shift means you can just call that here. In fact there are a few below as well.

185–416

Prefer EmulateInstructionRISCV& to pointers when you know it will never be null. A lot of existing code in this area passes a pointer but very few paths seem to ever handle nullptr.

(and if you have to take the address of the ref somewhere to fit the API that's fine but at least this new code can be a bit easier to reason about)

189

I don't know the riscv LUI but I used the mips one a lot, shouldn't this be setting the upper bits of the register. Where the register is 64 bits meaning the upper 32?

Maybe it doesn't work that way for 64 bit. On the surface I'd expect a << 32 here somewhere.

200

You could enforce that with https://en.cppreference.com/w/cpp/types/is_integral, or std::is_same if you have just 1/2 types you expect.

232

What is E here?

323

An alternative way to do this:

uint64_t result = int64_t(value.GetAsUInt64()) < int64_t(imm);
return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));

Saves some repetition.

(and I see you did this later, great minds)

417–418

static const, just for correctness.

449

Is this mask right?

SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in
register rs1 by the shift amount held in the lower 5 bits of register rs2.

From The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2.

Unless "5" means position 5 through position 0 inclusive instead of a group of 5 bits.

But then later

SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value
in register rs1 by the shift amount held in register rs2. In RV64I, only the low 6 bits of rs2 are
considered for the shift amount.

Is it 64 bit uses 6 and 32 bit uses 5?

736

So what I get from this loop is that any instruction we have a way to emulate, is an instruction that could include the PC as its destination register. Do I have that correct?

lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

200–231

This checks the decoding but do we also want to check that they apply their results correctly?

As in, if I shift left something into the PC it should change the value of the PC. That sort of thing.

[tzb99]

In D132789#3760708, @Emmmer wrote:

In D132789#3759892, @tzb99 wrote:

In D132789#3757675, @Emmmer wrote:

In D132789#3757018, @tzb99 wrote:

Upon this change, My lldb logging changes a bit. The instruction is not shown anymore, but stepping is still working. Is it as expected?

* thread #1, name = 'test.o', stop reason = signal SIGSTOP
    frame #0: 0x0000000000010528

I tried to reproduce but failed.
Could you please provide more information？
(for example: what is written in main, why use .o for debugging, and the command operations executed in lldb)

Sure. My testing script is:

#include<stdio.h>
void fun2() {
	printf("Enter fun2\n");
}
int fun1() {
	printf("Enter fun1\n");
	fun2();
	return 10;}

int main(int argc, char **argv) {
	int a = fun1();
	int b = 15;
       	printf("hello world\n");
	return 0;
}

So which file format should be used for debugging? My command option on the client side is:

lldb-server g 0.0.0.0:2345 test.o

On the lldb (x86) side is:

lldb
gdb-remote 2345
s

The objdump of my test.o file is:

0000000000010528 <_start>:
   10528:       02e000ef                jal     ra,10556 <load_gp>
   1052c:       87aa                    mv      a5,a0
   1052e:       00000517                auipc   a0,0x0
   10532:       14650513                addi    a0,a0,326 # 10674 <main>
   10536:       6582                    ld      a1,0(sp)
   10538:       0030                    addi    a2,sp,8
   1053a:       ff017113                andi    sp,sp,-16
   1053e:       00000697                auipc   a3,0x0
   10542:       68068693                addi    a3,a3,1664 # 10bbe <__libc_csu_init>
   10546:       00000717                auipc   a4,0x0

My compilation flavor should be:

riscv64-unknown-linux-gnu-gcc -g -o test.o hello.c \
-static -static-libgcc -static-libstdc++ -march=rv64imafd

Please let me know if you need more information!

I coiped your test code to tzb.c

(on x86)

$ riscv64-unknown-linux-gnu-gcc -g -o tzb tzb.c \
  -static -static-libgcc -static-libstdc++ -march=rv64imafd

PS: -o usage is: -o <file>, it means place the output into <file>.

---

(on qemu-system-riscv64)

$ lldb
(lldb) gdb-remote 8888

(lldb) Process 5933 stopped
* thread #1, name = 'tzb', stop reason = signal SIGSTOP
    frame #0: 0x0000000000010528 tzb`_start at start.S:50
warning: This version of LLDB has no plugin for the language "assembler". Inspection of frame variables will be limited.

Then I tried to read DWARF in tzb, and dwarfdump report DW_AT_language is DW_LANG_Mips_Assembler, but DW_AT_language should be DW_LANG_C99.

---

It may be a bug caused by riscv-gnu-toolchain, and we can use this to avoid it.

(on qemu-system-riscv64)

$ gcc -g -o tzb tzb.c \
  -static -static-libgcc -static-libstdc++ -march=rv64imafd

$ lldb-server g 0.0.0.0:2345 tzb
Launched 'tzb' as process 6839...
lldb-server-local_build

(Switch to another tab)

$ lldb
(lldb) gdb-remote 2345

(lldb) Process 6839 stopped
* thread #1, name = 'tzb', stop reason = signal SIGSTOP
    frame #0: 0x0000000000010584 tzb`_start
tzb`_start:
->  0x10584 <+0>:  jal    48                    <--|
    0x10588 <+4>:  mv     a5, a0                <--|
    0x1058c <+8>:  auipc  a0, 121               <--|
    0x10590 <+12>: ld     a0, -980(a0)          <--| as expected
(lldb)

Then you can set breakpoints and go to where you want.

---

I copied some DWARF info that may be useful:

in cross-build elf file:

.debug_info

COMPILE_UNIT<header overall offset = 0x00000000>:
< 0><0x0000000c>  DW_TAG_compile_unit
                    DW_AT_stmt_list             0x00000000
                    DW_AT_low_pc                0x00010528
                    DW_AT_high_pc               <offset-from-lowpc>0x00000042
                    DW_AT_name                  ../sysdeps/riscv/start.S
                    DW_AT_comp_dir              /home/emmmer/git/riscv-gnu-toolchain/glibc/csu
                    DW_AT_producer              GNU AS 2.38
                    DW_AT_language              DW_LANG_Mips_Assembler

in native-build elf file:

.debug_info

COMPILE_UNIT<header overall offset = 0x00000000>:
< 0><0x0000000b>  DW_TAG_compile_unit
                    DW_AT_producer              GNU C17 10.3.1 -march=rv64imafd -mabi=lp64d -g
                    DW_AT_language              DW_LANG_C99
                    DW_AT_name                  tzb.c
                    DW_AT_comp_dir              /root
                    DW_AT_low_pc                0x000106ac
                    DW_AT_high_pc               <offset-from-lowpc>188
                    DW_AT_stmt_list             0x00000000

Thank you very much for the investigation! The transition from riscv64-unknown-linux-gnu-gcc to gcc on qemu did improved. I can also set breakpoint on the designated memory address (failed to read the function names tho (main, etc)). Another issue I encountered (with this current patch, and same issue happened before) is that, if I kept executing "stepping" command, the ret (jalr) instruction cannot be executed properly and then the program entered into the illegal instruction region. Have you encountered the same issue by keeping stepping?

[Emmmer]

address review comments

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

66

When bit operation happens, inst is converted to int64, so we can't use SextW here directly.

449

Yes. The shamt field in RV32 is 5 bits, and The shamt field in RV64 is 6 bits.

736

Just implementing some branch instructions is not enough to debug some projects (like debugging atomic locks), so I added more instructions.

[DavidSpickett]

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

736

Right so this isn't just about instructions that branch (which is my mistake). Whenever we place a software breakpoint we're emulating the instruction we overwrote regardless of branching.

lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

166

Seems better to inline this below, I only see one call to it.

210

Please call this something other than map, tests perhaps? (it's a nit but at a glance you see oh its a map but oh wait it's in fact a vector)

[Emmmer]

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

189

The spec says:

LUI places the 32-bit U-immediate into register rd, filling in the lowest 12 bits with zeros. The 32-bit results sign-extended to 64 bits.

[Emmmer]

address review comments

[Emmmer]

Thank you very much for the investigation! The transition from riscv64-unknown-linux-gnu-gcc to gcc on qemu did improved. I can also set breakpoint on the designated memory address (failed to read the function names tho (main, etc)). Another issue I encountered (with this current patch, and same issue happened before) is that, if I kept executing "stepping" command, the ret (jalr) instruction cannot be executed properly and then the program entered into the illegal instruction region. Have you encountered the same issue by keeping stepping?

I didn't run into the illegal instruction region, but I did find an infinity loop(about atomic lock), due to the lack of RVA extension.

110cc:	100427af          	lr.w	a5,(s0)
110d0:	00079663          	bnez	a5,110dc <__run_exit_handlers+0x70>
110d4:	1ce426af          	sc.w.aq	a3,a4,(s0)
110d8:	fe069ae3          	bnez	a3,110cc <__run_exit_handlers+0x60>

sc.w.aq is going to set a3 to zero, if it didn't succeed, the bnez a3,110cc will jump to 110cc, causing an infinity loop.

[DavidSpickett]

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

189

Got it, I was expecting the LUI to "scale up" to 64 bit and be loading the upper 32 bits but that is not the case thanks for explaining.

[DavidSpickett]

This LGTM.

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h

 
 #include "lldb/Core/EmulateInstruction.h"
 #include "lldb/Interpreter/OptionValue.h"
 #include "lldb/Utility/Log.h"
 #include "lldb/Utility/Status.h"
 
 namespace lldb_private {
 
+constexpr uint32_t DecodeRD(uint32_t inst) { return (inst & 0xF80) >> 7; }
+constexpr uint32_t DecodeRS1(uint32_t inst) { return (inst & 0xF8000) >> 15; }
+constexpr uint32_t DecodeRS2(uint32_t inst) { return (inst & 0x1F00000) >> 20; }
+
+class EmulateInstructionRISCV;
+
+struct InstrPattern {
+  const char *name;
+  /// Bit mask to check the type of a instruction (B-Type, I-Type, J-Type, etc.)
+  uint32_t type_mask;
+  /// Characteristic value after bitwise-and with type_mask.
+  uint32_t eigen;
+  bool (*exec)(EmulateInstructionRISCV &emulator, uint32_t inst,
+               bool ignore_cond);
+};
+
 class EmulateInstructionRISCV : public EmulateInstruction {
 public:
   static llvm::StringRef GetPluginNameStatic() { return "riscv"; }
 
   static llvm::StringRef GetPluginDescriptionStatic() {
     return "Emulate instructions for the RISC-V architecture.";
   }
 
   static bool SupportsThisInstructionType(InstructionType inst_type) {
     switch (inst_type) {
     case eInstructionTypeAny:
     case eInstructionTypePCModifying:
       return true;
     case eInstructionTypePrologueEpilogue:
     case eInstructionTypeAll:
       return false;
+    default:
+      llvm_unreachable("Unhandled instruction type");
     }
     llvm_unreachable("Fully covered switch above!");
   }
 
   static bool SupportsThisArch(const ArchSpec &arch);
 
   static lldb_private::EmulateInstruction *
   CreateInstance(const lldb_private::ArchSpec &arch, InstructionType inst_type);
public:
   bool EvaluateInstruction(uint32_t options) override;
   bool TestEmulation(Stream *out_stream, ArchSpec &arch,
                      OptionValueDictionary *test_data) override;
   bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num,
                        RegisterInfo &reg_info) override;
 
   lldb::addr_t ReadPC(bool *success);
   bool WritePC(lldb::addr_t pc);
+
+  const InstrPattern *Decode(uint32_t inst);
   bool DecodeAndExecute(uint32_t inst, bool ignore_cond);
 };
 
 } // namespace lldb_private
 
 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_EMULATEINSTRUCTIONRISCV_H

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

 
 using namespace lldb;
 using namespace lldb_private;
 
 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionRISCV, InstructionRISCV)
 
 namespace lldb_private {
 
-// Masks for detecting instructions types. According to riscv-spec Chap 26.
-constexpr uint32_t I_MASK = 0b111000001111111;
-constexpr uint32_t J_MASK = 0b000000001111111;
-// no funct3 in the b-mask because the logic executing B<CMP> is quite similar.
-constexpr uint32_t B_MASK = 0b000000001111111;
-
 // The funct3 is the type of compare in B<CMP> instructions.
 // funct3 means "3-bits function selector", which RISC-V ISA uses as minor
 // opcode. It reuses the major opcode encoding space.
 constexpr uint32_t BEQ = 0b000;
 constexpr uint32_t BNE = 0b001;
 constexpr uint32_t BLT = 0b100;
 constexpr uint32_t BGE = 0b101;
 constexpr uint32_t BLTU = 0b110;
 constexpr uint32_t BGEU = 0b111;
 
-constexpr uint32_t DecodeRD(uint32_t inst) { return (inst & 0xF80) >> 7; }
-constexpr uint32_t DecodeRS1(uint32_t inst) { return (inst & 0xF8000) >> 15; }
-constexpr uint32_t DecodeRS2(uint32_t inst) { return (inst & 0x1F00000) >> 20; }
+constexpr uint32_t DecodeSHAMT5(uint32_t inst) { return DecodeRS2(inst); }
+constexpr uint32_t DecodeSHAMT7(uint32_t inst) {
+  return (inst & 0x7F00000) >> 20;
+}
 constexpr uint32_t DecodeFunct3(uint32_t inst) { return (inst & 0x7000) >> 12; }
 
+// used in decoder
 constexpr int32_t SignExt(uint32_t imm) { return int32_t(imm); }
 
+// used in executor
+template <typename T>
+constexpr std::enable_if_t<sizeof(T) <= 4, uint64_t> SextW(T value) {
+  return uint64_t(int64_t(int32_t(value)));
+}
+
+// used in executor
+template <typename T> constexpr uint64_t ZextD(T value) {
+  return uint64_t(value);
+}
+
 constexpr uint32_t DecodeJImm(uint32_t inst) {
   return (uint64_t(int64_t(int32_t(inst & 0x80000000)) >> 11)) // imm[20]
          | (inst & 0xff000)                                    // imm[19:12]
          | ((inst >> 9) & 0x800)                               // imm[11]
          | ((inst >> 20) & 0x7fe);                             // imm[10:1]
 }
 
 constexpr uint32_t DecodeIImm(uint32_t inst) {
   return int64_t(int32_t(inst)) >> 20; // imm[11:0]
 }
 
 constexpr uint32_t DecodeBImm(uint32_t inst) {
   return (uint64_t(int64_t(int32_t(inst & 0x80000000)) >> 19)) // imm[12]
          | ((inst & 0x80) << 4)                                // imm[11]
          | ((inst >> 20) & 0x7e0)                              // imm[10:5]
          | ((inst >> 7) & 0x1e);                               // imm[4:1]
 }
 
+constexpr uint32_t DecodeSImm(uint32_t inst) {
+  return (uint64_t(int64_t(int32_t(inst & 0xFE00000)) >> 20)) // imm[11:5]
+         | ((inst & 0xF80) >> 7);                             // imm[4:0]
+}
+
+constexpr uint32_t DecodeUImm(uint32_t inst) {
+  return SextW(inst & 0xFFFFF000); // imm[31:12]
+}
+
 static uint32_t GPREncodingToLLDB(uint32_t reg_encode) {
   if (reg_encode == 0)
     return gpr_x0_riscv;
   if (reg_encode >= 1 && reg_encode <= 31)
     return gpr_x1_riscv + reg_encode - 1;
   return LLDB_INVALID_REGNUM;
 }
 
-static bool ReadRegister(EmulateInstructionRISCV *emulator, uint32_t reg_encode,
+static bool ReadRegister(EmulateInstructionRISCV &emulator, uint32_t reg_encode,
                          RegisterValue &value) {
   uint32_t lldb_reg = GPREncodingToLLDB(reg_encode);
-  return emulator->ReadRegister(eRegisterKindLLDB, lldb_reg, value);
+  return emulator.ReadRegister(eRegisterKindLLDB, lldb_reg, value);
 }
 
-static bool WriteRegister(EmulateInstructionRISCV *emulator,
+static bool WriteRegister(EmulateInstructionRISCV &emulator,
                           uint32_t reg_encode, const RegisterValue &value) {
   uint32_t lldb_reg = GPREncodingToLLDB(reg_encode);
   EmulateInstruction::Context ctx;
   ctx.type = EmulateInstruction::eContextRegisterStore;
   ctx.SetNoArgs();
-  return emulator->WriteRegister(ctx, eRegisterKindLLDB, lldb_reg, value);
+  return emulator.WriteRegister(ctx, eRegisterKindLLDB, lldb_reg, value);
 }
 
-static bool ExecJAL(EmulateInstructionRISCV *emulator, uint32_t inst, bool) {
+static bool ExecJAL(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
   bool success = false;
   int64_t offset = SignExt(DecodeJImm(inst));
-  int64_t pc = emulator->ReadPC(&success);
-  return success && emulator->WritePC(pc + offset) &&
+  int64_t pc = emulator.ReadPC(&success);
+  return success && emulator.WritePC(pc + offset) &&
          WriteRegister(emulator, DecodeRD(inst),
                        RegisterValue(uint64_t(pc + 4)));
 }
 
-static bool ExecJALR(EmulateInstructionRISCV *emulator, uint32_t inst, bool) {
+static bool ExecJALR(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
   int64_t offset = SignExt(DecodeIImm(inst));
   RegisterValue value;
   if (!ReadRegister(emulator, DecodeRS1(inst), value))
     return false;
   bool success = false;
-  int64_t pc = emulator->ReadPC(&success);
+  int64_t pc = emulator.ReadPC(&success);
   int64_t rs1 = int64_t(value.GetAsUInt64());
   // JALR clears the bottom bit. According to riscv-spec:
   // "The JALR instruction now clears the lowest bit of the calculated target
   // address, to simplify hardware and to allow auxiliary information to be
   // stored in function pointers."
-  return emulator->WritePC((rs1 + offset) & ~1) &&
+  return emulator.WritePC((rs1 + offset) & ~1) &&
          WriteRegister(emulator, DecodeRD(inst),
                        RegisterValue(uint64_t(pc + 4)));
 }
 
 static bool CompareB(uint64_t rs1, uint64_t rs2, uint32_t funct3) {
   switch (funct3) {
   case BEQ:
     return rs1 == rs2;
   case BNE:
     return rs1 != rs2;
   case BLT:
     return int64_t(rs1) < int64_t(rs2);
   case BGE:
     return int64_t(rs1) >= int64_t(rs2);
   case BLTU:
     return rs1 < rs2;
   case BGEU:
     return rs1 >= rs2;
   default:
     llvm_unreachable("unexpected funct3");
   }
 }
 
-static bool ExecB(EmulateInstructionRISCV *emulator, uint32_t inst,
+static bool ExecB(EmulateInstructionRISCV &emulator, uint32_t inst,
                   bool ignore_cond) {
   bool success = false;
-  uint64_t pc = emulator->ReadPC(&success);
+  uint64_t pc = emulator.ReadPC(&success);
   if (!success)
     return false;
 
   uint64_t offset = SignExt(DecodeBImm(inst));
   uint64_t target = pc + offset;
   if (ignore_cond)
-    return emulator->WritePC(target);
+    return emulator.WritePC(target);
 
   RegisterValue value1;
   RegisterValue value2;
   if (!ReadRegister(emulator, DecodeRS1(inst), value1) ||
       !ReadRegister(emulator, DecodeRS2(inst), value2))
     return false;
 
   uint32_t funct3 = DecodeFunct3(inst);
   if (CompareB(value1.GetAsUInt64(), value2.GetAsUInt64(), funct3))
-    return emulator->WritePC(target);
+    return emulator.WritePC(target);
 
   return true;
 }
 
-struct InstrPattern {
-  const char *name;
-  /// Bit mask to check the type of a instruction (B-Type, I-Type, J-Type, etc.)
-  uint32_t type_mask;
-  /// Characteristic value after bitwise-and with type_mask.
-  uint32_t eigen;
-  bool (*exec)(EmulateInstructionRISCV *emulator, uint32_t inst,
-               bool ignore_cond);
-};
+static bool ExecLUI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  uint32_t imm = DecodeUImm(inst);
+  RegisterValue value;
+  value.SetUInt64(SignExt(imm));
+  return WriteRegister(emulator, DecodeRD(inst), value);
+}
+
+static bool ExecAUIPC(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  uint32_t imm = DecodeUImm(inst);
+  RegisterValue value;
+  bool success = false;
+  value.SetUInt64(SignExt(imm) + emulator.ReadPC(&success));
+  return success && WriteRegister(emulator, DecodeRD(inst), value);
+}
+
+template <typename T>
+static std::enable_if_t<std::is_integral_v<T>, T>
+ReadMem(EmulateInstructionRISCV &emulator, uint64_t addr, bool *success) {
+
+  EmulateInstructionRISCV::Context ctx;
+  ctx.type = EmulateInstruction::eContextRegisterLoad;
+  ctx.SetNoArgs();
+  return T(emulator.ReadMemoryUnsigned(ctx, addr, sizeof(T), T(), success));
+}
+
+template <typename T>
+static bool WriteMem(EmulateInstructionRISCV &emulator, uint64_t addr,
+                     RegisterValue value) {
+  EmulateInstructionRISCV::Context ctx;
+  ctx.type = EmulateInstruction::eContextRegisterStore;
+  ctx.SetNoArgs();
+  return emulator.WriteMemoryUnsigned(ctx, addr, value.GetAsUInt64(),
+                                      sizeof(T));
+}
+
+static uint64_t LoadStoreAddr(EmulateInstructionRISCV &emulator,
+                              uint32_t inst) {
+  auto rs1 = DecodeRS1(inst);
+  int32_t imm = SignExt(DecodeSImm(inst));
+  RegisterValue value;
+  if (!ReadRegister(emulator, rs1, value))
+    return LLDB_INVALID_ADDRESS;
+  uint64_t addr = value.GetAsUInt64() + uint64_t(imm);
+  return addr;
+}
+
+// Read T from memory, then load its sign-extended value E to register.
+template <typename T, typename E>
+static bool Load(EmulateInstructionRISCV &emulator, uint32_t inst,
+                 uint64_t (*extend)(E)) {
+  uint64_t addr = LoadStoreAddr(emulator, inst);
+  if (addr == LLDB_INVALID_ADDRESS)
+    return false;
+  bool success = false;
+  E value = E(ReadMem<T>(emulator, addr, &success));
+  if (!success)
+    return false;
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(extend(value)));
+}
+
+template <typename T>
+static bool Store(EmulateInstructionRISCV &emulator, uint32_t inst) {
+  uint64_t addr = LoadStoreAddr(emulator, inst);
+  if (addr == LLDB_INVALID_ADDRESS)
+    return false;
+  RegisterValue value;
+  if (!ReadRegister(emulator, DecodeRS2(inst), value))
+    return false;
+  return WriteMem<T>(emulator, addr, value);
+}
+
+static bool ExecLB(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return Load<uint8_t, int8_t>(emulator, inst, SextW);
+}
+
+static bool ExecLH(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return Load<uint16_t, int16_t>(emulator, inst, SextW);
+}
+
+static bool ExecLW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return Load<uint32_t, int32_t>(emulator, inst, SextW);
+}
+
+static bool ExecLD(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return Load<uint64_t, uint64_t>(emulator, inst, ZextD);
+}
+
+static bool ExecLBU(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return Load<uint8_t, uint8_t>(emulator, inst, ZextD);
+}
+
+static bool ExecLHU(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return Load<uint16_t, uint16_t>(emulator, inst, ZextD);
+}
+
+static bool ExecLWU(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return Load<uint32_t, uint32_t>(emulator, inst, ZextD);
+}
+
+static bool ExecSB(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return Store<uint8_t>(emulator, inst);
+}
+
+static bool ExecSH(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return Store<uint16_t>(emulator, inst);
+}
+
+static bool ExecSW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return Store<uint32_t>(emulator, inst);
+}
+
+static bool ExecSD(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  return Store<uint64_t>(emulator, inst);
+}
+
+static bool ExecADDI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  int32_t imm = SignExt(DecodeIImm(inst));
+
+  RegisterValue value;
+  if (!ReadRegister(emulator, rs1, value))
+    return false;
+
+  uint64_t result = int64_t(value.GetAsUInt64()) + int64_t(imm);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSLTI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  int32_t imm = SignExt(DecodeIImm(inst));
+
+  RegisterValue value;
+  if (!ReadRegister(emulator, rs1, value))
+    return false;
+
+  uint64_t result = int64_t(value.GetAsUInt64()) < int64_t(imm);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSLTIU(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  int32_t imm = SignExt(DecodeIImm(inst));
+
+  RegisterValue value;
+  if (!ReadRegister(emulator, rs1, value))
+    return false;
+
+  uint64_t result = value.GetAsUInt64() < uint64_t(imm);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecXORI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  int32_t imm = SignExt(DecodeIImm(inst));
+
+  RegisterValue value;
+  if (!ReadRegister(emulator, rs1, value))
+    return false;
+
+  uint64_t result = value.GetAsUInt64() ^ uint64_t(imm);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecORI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  int32_t imm = SignExt(DecodeIImm(inst));
+
+  RegisterValue value;
+  if (!ReadRegister(emulator, rs1, value))
+    return false;
+
+  uint64_t result = value.GetAsUInt64() | uint64_t(imm);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecANDI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  int32_t imm = SignExt(DecodeIImm(inst));
+
+  RegisterValue value;
+  if (!ReadRegister(emulator, rs1, value))
+    return false;
+
+  uint64_t result = value.GetAsUInt64() & uint64_t(imm);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSLLI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto shamt = DecodeSHAMT7(inst);
+
+  RegisterValue value;
+  if (!ReadRegister(emulator, rs1, value))
+    return false;
+
+  uint64_t result = value.GetAsUInt64() << shamt;
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSRLI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto shamt = DecodeSHAMT7(inst);
+
+  RegisterValue value;
+  if (!ReadRegister(emulator, rs1, value))
+    return false;
+
+  uint64_t result = value.GetAsUInt64() >> shamt;
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSRAI(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto shamt = DecodeSHAMT7(inst);
+
+  RegisterValue value;
+  if (!ReadRegister(emulator, rs1, value))
+    return false;
+
+  uint64_t result = int64_t(value.GetAsUInt64()) >> shamt;
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecADD(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result = value1.GetAsUInt64() + value2.GetAsUInt64();
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSUB(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
 
-static InstrPattern PATTERNS[] = {
-    {"JAL", J_MASK, 0b1101111, ExecJAL},
-    {"JALR", I_MASK, 0b000000001100111, ExecJALR},
-    {"B<CMP>", B_MASK, 0b1100011, ExecB},
-    // TODO: {LR/SC}.{W/D} and ECALL
+  uint64_t result = value1.GetAsUInt64() - value2.GetAsUInt64();
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSLL(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result = value1.GetAsUInt64() << (value2.GetAsUInt64() & 0b111111);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSLT(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result = int64_t(value1.GetAsUInt64()) < int64_t(value2.GetAsUInt64());
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSLTU(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result = value1.GetAsUInt64() < value2.GetAsUInt64();
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecXOR(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result = value1.GetAsUInt64() ^ value2.GetAsUInt64();
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSRL(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result = value1.GetAsUInt64() >> (value2.GetAsUInt64() & 0b111111);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSRA(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result =
+      int64_t(value1.GetAsUInt64()) >> (value2.GetAsUInt64() & 0b111111);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecOR(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result = value1.GetAsUInt64() | value2.GetAsUInt64();
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecAND(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result = value1.GetAsUInt64() & value2.GetAsUInt64();
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecADDIW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  int32_t imm = SignExt(DecodeIImm(inst));
+
+  RegisterValue value1;
+  if (!ReadRegister(emulator, rs1, value1))
+    return false;
+
+  uint64_t result = SextW(int32_t(value1.GetAsUInt64()) + imm);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSLLIW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto shamt = DecodeSHAMT5(inst);
+
+  RegisterValue value1;
+  if (!ReadRegister(emulator, rs1, value1))
+    return false;
+
+  uint64_t result = SextW(uint32_t(value1.GetAsUInt64()) << shamt);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSRLIW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto shamt = DecodeSHAMT5(inst);
+
+  RegisterValue value1;
+  if (!ReadRegister(emulator, rs1, value1))
+    return false;
+
+  uint64_t result = SextW(uint32_t(value1.GetAsUInt64()) >> shamt);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSRAIW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto shamt = DecodeSHAMT5(inst);
+
+  RegisterValue value1;
+  if (!ReadRegister(emulator, rs1, value1))
+    return false;
+
+  uint64_t result = SextW(int32_t(value1.GetAsUInt64()) >> shamt);
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecADDW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result = SextW(value1.GetAsUInt32() + value2.GetAsUInt32());
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSUBW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result = SextW(value1.GetAsUInt32() - value2.GetAsUInt32());
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSLLW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result = SextW(uint32_t(value1.GetAsUInt64())
+                          << (value2.GetAsUInt64() & 0b111111));
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSRLW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result = SextW(uint32_t(value1.GetAsUInt64()) >>
+                          (value2.GetAsUInt64() & 0b111111));
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static bool ExecSRAW(EmulateInstructionRISCV &emulator, uint32_t inst, bool) {
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = DecodeRS2(inst);
+
+  RegisterValue value1;
+  RegisterValue value2;
+  if (!ReadRegister(emulator, rs1, value1) ||
+      !ReadRegister(emulator, rs2, value2))
+    return false;
+
+  uint64_t result =
+      SextW(int32_t(value1.GetAsUInt64()) >> (value2.GetAsUInt64() & 0b111111));
+  return WriteRegister(emulator, DecodeRD(inst), RegisterValue(result));
+}
+
+static const InstrPattern PATTERNS[] = {
+    {"LUI", 0x7F, 0x37, ExecLUI},
+    {"AUIPC", 0x7F, 0x17, ExecAUIPC},
+    {"JAL", 0x7F, 0x6F, ExecJAL},
+    {"JALR", 0x707F, 0x67, ExecJALR},
+    {"B<CMP>", 0x7F, 0x63, ExecB},
+    {"LB", 0x707F, 0x3, ExecLB},
+    {"LH", 0x707F, 0x1003, ExecLH},
+    {"LW", 0x707F, 0x2003, ExecLW},
+    {"LBU", 0x707F, 0x4003, ExecLBU},
+    {"LHU", 0x707F, 0x5003, ExecLHU},
+    {"SB", 0x707F, 0x23, ExecSB},
+    {"SH", 0x707F, 0x1023, ExecSH},
+    {"SW", 0x707F, 0x2023, ExecSW},
+    {"ADDI", 0x707F, 0x13, ExecADDI},
+    {"SLTI", 0x707F, 0x2013, ExecSLTI},
+    {"SLTIU", 0x707F, 0x3013, ExecSLTIU},
+    {"XORI", 0x707F, 0x4013, ExecXORI},
+    {"ORI", 0x707F, 0x6013, ExecORI},
+    {"ANDI", 0x707F, 0x7013, ExecANDI},
+    {"SLLI", 0xF800707F, 0x1013, ExecSLLI},
+    {"SRLI", 0xF800707F, 0x5013, ExecSRLI},
+    {"SRAI", 0xF800707F, 0x40005013, ExecSRAI},
+    {"ADD", 0xFE00707F, 0x33, ExecADD},
+    {"SUB", 0xFE00707F, 0x40000033, ExecSUB},
+    {"SLL", 0xFE00707F, 0x1033, ExecSLL},
+    {"SLT", 0xFE00707F, 0x2033, ExecSLT},
+    {"SLTU", 0xFE00707F, 0x3033, ExecSLTU},
+    {"XOR", 0xFE00707F, 0x4033, ExecXOR},
+    {"SRL", 0xFE00707F, 0x5033, ExecSRL},
+    {"SRA", 0xFE00707F, 0x40005033, ExecSRA},
+    {"OR", 0xFE00707F, 0x6033, ExecOR},
+    {"AND", 0xFE00707F, 0x7033, ExecAND},
+    {"LWU", 0x707F, 0x6003, ExecLWU},
+    {"LD", 0x707F, 0x3003, ExecLD},
+    {"SD", 0x707F, 0x3023, ExecSD},
+    {"ADDIW", 0x707F, 0x1B, ExecADDIW},
+    {"SLLIW", 0xFE00707F, 0x101B, ExecSLLIW},
+    {"SRLIW", 0xFE00707F, 0x501B, ExecSRLIW},
+    {"SRAIW", 0xFE00707F, 0x4000501B, ExecSRAIW},
+    {"ADDW", 0xFE00707F, 0x3B, ExecADDW},
+    {"SUBW", 0xFE00707F, 0x4000003B, ExecSUBW},
+    {"SLLW", 0xFE00707F, 0x103B, ExecSLLW},
+    {"SRLW", 0xFE00707F, 0x503B, ExecSRLW},
+    {"SRAW", 0xFE00707F, 0x4000503B, ExecSRAW},
 };
 
+const InstrPattern *EmulateInstructionRISCV::Decode(uint32_t inst) {
+  for (const InstrPattern &pat : PATTERNS) {
+    if ((inst & pat.type_mask) == pat.eigen) {
+      return &pat;
+    }
+  }
+  return nullptr;
+}
+
 /// This function only determines the next instruction address for software
-/// sigle stepping by emulating branching instructions including:
-/// - from Base Instruction Set  : JAL, JALR, B<CMP>, ECALL
-/// - from Atomic Instruction Set: LR -> BNE -> SC -> BNE
-/// We will get rid of this tedious code when the riscv debug spec is ratified.
+/// sigle stepping by emulating instructions
 bool EmulateInstructionRISCV::DecodeAndExecute(uint32_t inst,
                                                bool ignore_cond) {
-  Log *log = GetLog(LLDBLog::Process | LLDBLog::Breakpoints);
-  for (const InstrPattern &pat : PATTERNS) {
-    if ((inst & pat.type_mask) == pat.eigen) {
-      LLDB_LOGF(log, "EmulateInstructionRISCV::%s: inst(%x) was decoded to %s",
-                __FUNCTION__, inst, pat.name);
-      return pat.exec(this, inst, ignore_cond);
-    }
+  Log *log = GetLog(LLDBLog::Unwind);
+  const InstrPattern *pattern = this->Decode(inst);
+  if (pattern) {
+              __FUNCTION__, inst, pattern->name);
+    return pattern->exec(*this, inst, ignore_cond);
   }
 
   LLDB_LOGF(log,
             "EmulateInstructionRISCV::%s: inst(0x%x) does not branch: "
             "no need to calculate the next pc address which is trivial.",
             __FUNCTION__, inst);
   return true;
 }
 
 bool EmulateInstructionRISCV::EvaluateInstruction(uint32_t options) {
   uint32_t inst_size = m_opcode.GetByteSize();
   uint32_t inst = m_opcode.GetOpcode32();
   bool increase_pc = options & eEmulateInstructionOptionAutoAdvancePC;
   bool ignore_cond = options & eEmulateInstructionOptionIgnoreConditions;
   bool success = false;
 
-  lldb::addr_t old_pc = 0;
+  lldb::addr_t old_pc = LLDB_INVALID_ADDRESS;
   if (increase_pc) {
     old_pc = ReadPC(&success);
     if (!success)
       return false;
   }
 
   if (inst_size == 2) {
     // TODO: execute RVC
bool EmulateInstructionRISCV::ReadInstruction() {
   if (!success) {
     m_addr = LLDB_INVALID_ADDRESS;
     return false;
   }
 
   Context ctx;
   ctx.type = eContextReadOpcode;
   ctx.SetNoArgs();
-  uint32_t inst = (uint32_t)ReadMemoryUnsigned(ctx, m_addr, 4, 0, &success);
-  uint16_t try_rvc = (uint16_t)(inst & 0x0000ffff);
+  uint32_t inst = uint32_t(ReadMemoryUnsigned(ctx, m_addr, 4, 0, &success));
+  uint16_t try_rvc = uint16_t(inst & 0x0000ffff);
   // check whether the compressed encode could be valid
   uint16_t mask = try_rvc & 0b11;
-  if (try_rvc != 0 && mask != 3) {
+  if (try_rvc != 0 && mask != 3)
     m_opcode.SetOpcode16(try_rvc, GetByteOrder());
-  } else {
+  else
     m_opcode.SetOpcode32(inst, GetByteOrder());
-  }
 
   return true;
 }
 
 lldb::addr_t EmulateInstructionRISCV::ReadPC(bool *success) {
   return ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC,
                               LLDB_INVALID_ADDRESS, success);
 }

lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

 #define GEN_BRANCH_TEST(name, rs1, rs2_branched, rs2_continued)                \
   TEST_F(RISCVEmulatorTester, test##name##Branched) {                          \
     testBranch(this, name, true, rs1, rs2_branched);                           \
   }                                                                            \
   TEST_F(RISCVEmulatorTester, test##name##Continued) {                         \
     testBranch(this, name, false, rs1, rs2_continued);                         \
   }
 
+void CheckRD(RISCVEmulatorTester *tester, uint64_t rd, uint64_t value) {
+  ASSERT_EQ(tester->gpr.gpr[rd], value);
+}
+
+using RS1 = uint64_t;
+using RS2 = uint64_t;
+using PC = uint64_t;
+using RDComputer = std::function<uint64_t(RS1, RS2, PC)>;
+
+void TestInst(RISCVEmulatorTester *tester, uint64_t inst, bool has_rs2,
+              RDComputer rd_val) {
+
+  lldb::addr_t old_pc = 0x114514;
+  tester->WritePC(old_pc);
+  auto rd = DecodeRD(inst);
+  auto rs1 = DecodeRS1(inst);
+  auto rs2 = 0;
+  if (rs1)
+    tester->gpr.gpr[rs1] = 0x1919;
+
+  if (has_rs2) {
+    rs2 = DecodeRS2(inst);
+    if (rs2)
+      tester->gpr.gpr[rs2] = 0x8181;
+  }
+
+  ASSERT_TRUE(tester->DecodeAndExecute(inst, false));
+  CheckRD(tester, rd,
+          rd_val(tester->gpr.gpr[rs1], rs2 ? tester->gpr.gpr[rs2] : 0, old_pc));
+}
+
 // GEN_BRANCH_TEST(opcode, imm1, imm2, imm3):
 // It should branch for instruction `opcode imm1, imm2`
 // It should do nothing for instruction `opcode imm1, imm3`
 GEN_BRANCH_TEST(BEQ, 1, 1, 0)
 GEN_BRANCH_TEST(BNE, 1, 0, 1)
 GEN_BRANCH_TEST(BLT, -2, 1, -3)
 GEN_BRANCH_TEST(BGE, -2, -3, 1)
 GEN_BRANCH_TEST(BLTU, -2, -1, 1)
 GEN_BRANCH_TEST(BGEU, -2, 1, -1)
 
-void testNothing(RISCVEmulatorTester *tester, uint32_t inst) {
-  lldb::addr_t old_pc = 0x114514;
-  tester->WritePC(old_pc);
-  tester->SetInstruction(Opcode(inst, tester->GetByteOrder()),
-                         LLDB_INVALID_ADDRESS, nullptr);
-  ASSERT_TRUE(tester->EvaluateInstruction(0));
-  bool success = false;
-  auto pc = tester->ReadPC(&success);
-  ASSERT_TRUE(success);
-  ASSERT_EQ(pc, old_pc);
-  ASSERT_TRUE(
-      tester->EvaluateInstruction(eEmulateInstructionOptionAutoAdvancePC));
-  pc = tester->ReadPC(&success);
-  ASSERT_TRUE(success);
-  ASSERT_EQ(pc, old_pc + 4);
-}
+struct TestData {
+  uint32_t inst;
+  std::string name;
+  bool has_rs2;
+  RDComputer rd_val;
+};
 
-#define GEN_NOTHING_TEST(name, inst)                                           \
-  TEST_F(RISCVEmulatorTester, testDoNothing_##name) { testNothing(this, inst); }
+TEST_F(RISCVEmulatorTester, TestDecodeAndExcute) {
 
-// GEN_NOTHING_TEST(name, inst):
-// It should do nothing (except increasing pc) for instruction `inst`
-GEN_NOTHING_TEST(mv, 0x01813083)   // mv a0, a5
-GEN_NOTHING_TEST(li, 0x00078513)   // li a5, 0
-GEN_NOTHING_TEST(sd, 0x02010413)   // sd s0, sp(16)
-GEN_NOTHING_TEST(lw, 0x0007879b)   // lw a5, s0(-20)
-GEN_NOTHING_TEST(addi, 0x00113423) // addi sp, sp, -16
+  std::vector<TestData> tests = {
+      {0x00010113, "ADDI", false, [](RS1 rs1, RS2, PC) { return rs1 + 0; }},
+      {0x00023517, "AUIPC", false, [](RS1, RS2, PC pc) { return pc + 143360; }},
+      {0x0006079b, "ADDIW", false, [](RS1 rs1, RS2, PC) { return rs1 + 0; }},
+      {0x00110837, "LUI", false, [](RS1, RS2, PC pc) { return 1114112; }},
+      {0x00147513, "ANDI", false, [](RS1 rs1, RS2, PC) { return rs1 & 1; }},
+      {0x00153513, "SLTIU", false, [](RS1 rs1, RS2, PC) { return rs1 != 0; }},
+      {0x00256513, "ORI", false, [](RS1 rs1, RS2, PC) { return rs1 | 1; }},
+      {0x00451a13, "SLLI", false, [](RS1 rs1, RS2, PC) { return rs1 << 4; }},
+      {0x00455693, "SRLI", false, [](RS1 rs1, RS2, PC) { return rs1 >> 4; }},
+      {0x00a035b3, "SLTU", true, [](RS1 rs1, RS2 rs2, PC) { return rs2 != 0; }},
+      {0x00b50633, "ADD", true, [](RS1 rs1, RS2 rs2, PC) { return rs1 + rs2; }},
+      {0x40d507b3, "SUB", true, [](RS1 rs1, RS2 rs2, PC) { return rs1 - rs2; }},
+  };
+  for (auto i : tests) {
+    const InstrPattern *pattern = this->Decode(i.inst);
+    ASSERT_TRUE(pattern != nullptr);
+    std::string name = pattern->name;
+    ASSERT_EQ(name, i.name);
+    TestInst(this, i.inst, i.has_rs2, i.rd_val);
+  }
+}