[RISCV][M68k] Replace fixed size BitVector with std::bittest.

[craig.topper]

Summary

Saves a heap allocation and avoids an explicit call to the BitVector constructor.

[craig.topper]

Upload complete patch.

[myhsu]

LGTM on 68k side.
Thanks for fixing.

[myhsu]

typo in the title: std::bittest -> std::bitset

[reames]

LGTM

llvm/lib/Target/M68k/M68kSubtarget.h

 
 #ifndef LLVM_LIB_TARGET_M68K_M68KSUBTARGET_H
 #define LLVM_LIB_TARGET_M68K_M68KSUBTARGET_H
 
 #include "M68kFrameLowering.h"
 #include "M68kISelLowering.h"
 #include "M68kInstrInfo.h"
 
-#include "llvm/ADT/BitVector.h"
 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
 #include "llvm/CodeGen/RegisterBankInfo.h"
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/MC/MCInstrItineraries.h"

 
 protected:
   // These define which ISA is supported. Since each Motorola M68k ISA is
   // built on top of the previous one whenever an ISA is selected the previous
   // selected as well.
   enum SubtargetEnum { M00, M10, M20, M30, M40, M60 };
   SubtargetEnum SubtargetKind = M00;
 
-  BitVector UserReservedRegister;
+  std::bitset<M68k::NUM_TARGET_REGS> UserReservedRegister;
 
   InstrItineraryData InstrItins;
 
   /// Small section is used.
   bool UseSmallSection = true;
 
   const M68kTargetMachine &TM;
 

llvm/lib/Target/M68k/M68kSubtarget.cpp

static StringRef selectM68kCPU(Triple TT, StringRef CPU) {
   }
   return CPU;
 }
 
 void M68kSubtarget::anchor() {}
 
 M68kSubtarget::M68kSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
                              const M68kTargetMachine &TM)
-    : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
-      UserReservedRegister(M68k::NUM_TARGET_REGS), TM(TM), TSInfo(),
+    : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TM(TM), TSInfo(),
       InstrInfo(initializeSubtargetDependencies(CPU, TT, FS, TM)),
       FrameLowering(*this, this->getStackAlignment()), TLInfo(TM, *this),
       TargetTriple(TT) {
   CallLoweringInfo.reset(new M68kCallLowering(*getTargetLowering()));
   Legalizer.reset(new M68kLegalizerInfo(*this));
 
   auto *RBI = new M68kRegisterBankInfo(*getRegisterInfo());
   RegBankInfo.reset(RBI);

llvm/lib/Target/RISCV/RISCVSubtarget.h

private:
   bool EnableUnalignedScalarMem = false;
   bool HasLUIADDIFusion = false;
   bool HasForcedAtomics = false;
   unsigned XLen = 32;
   unsigned ZvlLen = 0;
   MVT XLenVT = MVT::i32;
   uint8_t MaxInterleaveFactor = 2;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
-  BitVector UserReservedRegister;
+  std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
   RISCVTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
 
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
   RISCVFeatures::validate(TT, getFeatureBits());
   return *this;
 }
 
 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
                                StringRef TuneCPU, StringRef FS,
                                StringRef ABIName, const TargetMachine &TM)
     : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
-      UserReservedRegister(RISCV::NUM_TARGET_REGS),
-      FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
+      FrameLowering(
+          initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
   Legalizer.reset(new RISCVLegalizerInfo(*this));
 
   auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
   RegBankInfo.reset(RBI);
   InstSelector.reset(createRISCVInstructionSelector(
       *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));