[LoongArch] Add some fixups and relocations

[wangleiat]

Summary

This patch only add %pc_hi20/%pc_lo12/%plt relocations in order
to be able to generate gnu ld linkable relocation file for the
hello world IR :

@.str = private unnamed_addr constant [14 x i8] c"Hello world!\0A\00", align 1

define dso_local signext i32 @main() nounwind {
entry:
  %call = call signext i32 (ptr, ...) @printf(ptr noundef @.str)
  ret i32 0
}

declare dso_local signext i32 @printf(ptr noundef, ...)

This patch also updated some test cases due to new modifiers.
New test: test/MC/LoongArch/Relocations/relocations.s

[xen0n]

This is something we all have been longing for. I'm still studying the other targets for the current coding practices in this area but at least the test case changes seem very sane. Many thanks.

Can't wait to run some native tests with this applied ;-)

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h

28

From a quick grep, the middle part should be spelled the same as the target name, i.e. the names should look like VK_LoongArch_XXX instead. Don't use the binutils convention ("LARCH") as the "larch" abbreviation is in fact not seen anywhere outside binutils.

[wangleiat]

Address @xen0n's comment.

[xen0n]

LGTM with the nit resolved. Others, opinions?

[wangleiat]

test case change larch to loongarch

[SixWeining]

rebase

llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp

 // LoongArchAsmParser.cpp - Parse LoongArch assembly to MCInst instructions -=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/LoongArchInstPrinter.h"
+#include "MCTargetDesc/LoongArchMCExpr.h"
 #include "MCTargetDesc/LoongArchMCTargetDesc.h"
 #include "TargetInfo/LoongArchTargetInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCValue.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/Casting.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "loongarch-asm-parser"
 
 namespace {
bool processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands,
                           MCStreamer &Out);
 
 // Auto-generated instruction matching functions.
 #define GET_ASSEMBLER_HEADER
 #include "LoongArchGenAsmMatcher.inc"
 
   OperandMatchResultTy parseRegister(OperandVector &Operands);
   OperandMatchResultTy parseImmediate(OperandVector &Operands);
+  OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands);
+  OperandMatchResultTy parseSImm26Operand(OperandVector &Operands);
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 
 public:
   enum LoongArchMatchResultTy {
     Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
     Match_RequiresMsbNotLessThanLsb,
     Match_RequiresOpnd2NotR0R1,
 #define GET_OPERAND_DIAGNOSTIC_TYPES
 #include "LoongArchGenAsmMatcher.inc"
 #undef GET_OPERAND_DIAGNOSTIC_TYPES
   };
 
+  static bool classifySymbolRef(const MCExpr *Expr,
+                                LoongArchMCExpr::VariantKind &Kind);
+
   LoongArchAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
                      const MCInstrInfo &MII, const MCTargetOptions &Options)
       : MCTargetAsmParser(Options, STI, MII) {
     Parser.addAliasForDirective(".half", ".2byte");
     Parser.addAliasForDirective(".hword", ".2byte");
     Parser.addAliasForDirective(".word", ".4byte");
     Parser.addAliasForDirective(".dword", ".8byte");
 
public:
   LoongArchOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
 
   bool isToken() const override { return Kind == KindTy::Token; }
   bool isReg() const override { return Kind == KindTy::Register; }
   bool isImm() const override { return Kind == KindTy::Immediate; }
   bool isMem() const override { return false; }
   void setReg(MCRegister PhysReg) { Reg.RegNum = PhysReg; }
 
-  static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm) {
+  static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm,
+                                  LoongArchMCExpr::VariantKind &VK) {
+    if (auto *LE = dyn_cast<LoongArchMCExpr>(Expr)) {
+      VK = LE->getKind();
+      return false;
+    }
+
     if (auto CE = dyn_cast<MCConstantExpr>(Expr)) {
       Imm = CE->getValue();
       return true;
     }
 
     return false;
   }
 
   template <unsigned N, int P = 0> bool isUImm() const {
     if (!isImm())
       return false;
 
     int64_t Imm;
-    bool IsConstantImm = evaluateConstantImm(getImm(), Imm);
-    return IsConstantImm && isUInt<N>(Imm - P);
+    LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<N>(Imm - P) &&
+           VK == LoongArchMCExpr::VK_LoongArch_None;
   }
 
   template <unsigned N, unsigned S = 0> bool isSImm() const {
     if (!isImm())
       return false;
 
     int64_t Imm;
-    bool IsConstantImm = evaluateConstantImm(getImm(), Imm);
-    return IsConstantImm && isShiftedInt<N, S>(Imm);
+    LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isShiftedInt<N, S>(Imm) &&
+           VK == LoongArchMCExpr::VK_LoongArch_None;
   }
 
   bool isUImm2() const { return isUImm<2>(); }
   bool isUImm2plus1() const { return isUImm<2, 1>(); }
   bool isUImm3() const { return isUImm<3>(); }
   bool isUImm5() const { return isUImm<5>(); }
   bool isUImm6() const { return isUImm<6>(); }
   bool isUImm8() const { return isUImm<8>(); }
   bool isUImm12() const { return isUImm<12>(); }
   bool isUImm14() const { return isUImm<14>(); }
   bool isUImm15() const { return isUImm<15>(); }
-  bool isSImm12() const { return isSImm<12>(); }
+
+  bool isSImm12() const {
+    if (!isImm())
+      return false;
+
+    int64_t Imm;
+    LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_PCREL_LO;
+
+    return IsConstantImm
+               ? (isInt<12>(Imm) &&
+                  (VK == LoongArchMCExpr::VK_LoongArch_None || IsValidKind))
+               : (LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
+                  IsValidKind);
+  }
+
   bool isSImm14lsl2() const { return isSImm<14, 2>(); }
   bool isSImm16() const { return isSImm<16>(); }
   bool isSImm16lsl2() const { return isSImm<16, 2>(); }
   bool isSImm20() const { return isSImm<20>(); }
+
+  bool isSImm20pcalau12i() const {
+    if (!isImm())
+      return false;
+
+    int64_t Imm;
+    LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    bool IsValidKind = VK == LoongArchMCExpr::VK_LoongArch_PCREL_HI;
+
+    return IsConstantImm
+               ? (isInt<20>(Imm) &&
+                  (VK == LoongArchMCExpr::VK_LoongArch_None || IsValidKind))
+               : (LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
+                  IsValidKind);
+  }
+
   bool isSImm21lsl2() const { return isSImm<21, 2>(); }
-  bool isSImm26lsl2() const { return isSImm<26, 2>(); }
+
+  bool isSImm26Operand() const {
+    int64_t Imm;
+    LoongArchMCExpr::VariantKind VK = LoongArchMCExpr::VK_LoongArch_None;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    bool IsValidKind = (VK == LoongArchMCExpr::VK_LoongArch_CALL ||
+                        VK == LoongArchMCExpr::VK_LoongArch_CALL_PLT);
+
+    return IsConstantImm
+               ? (isShiftedInt<26, 2>(Imm) &&
+                  (VK == LoongArchMCExpr::VK_LoongArch_None || IsValidKind))
+               : (LoongArchAsmParser::classifySymbolRef(getImm(), VK) &&
+                  IsValidKind);
+  }
 
   /// Gets location of the first token of this operand.
   SMLoc getStartLoc() const override { return StartLoc; }
   /// Gets location of the last token of this operand.
   SMLoc getEndLoc() const override { return EndLoc; }
 
   unsigned getReg() const override {
     assert(Kind == KindTy::Register && "Invalid type access!");

 }
 
 OperandMatchResultTy LoongArchAsmParser::tryParseRegister(unsigned &RegNo,
                                                           SMLoc &StartLoc,
                                                           SMLoc &EndLoc) {
   llvm_unreachable("Unimplemented function.");
 }
 
+bool LoongArchAsmParser::classifySymbolRef(const MCExpr *Expr,
+                                           LoongArchMCExpr::VariantKind &Kind) {
+  Kind = LoongArchMCExpr::VK_LoongArch_None;
+
+  if (const LoongArchMCExpr *RE = dyn_cast<LoongArchMCExpr>(Expr)) {
+    Kind = RE->getKind();
+    Expr = RE->getSubExpr();
+  }
+
+  MCValue Res;
+  if (Expr->evaluateAsRelocatable(Res, nullptr, nullptr))
+    return Res.getRefKind() == LoongArchMCExpr::VK_LoongArch_None;
+  return false;
+}
+
 OperandMatchResultTy
 LoongArchAsmParser::parseRegister(OperandVector &Operands) {
   if (getLexer().getTok().isNot(AsmToken::Dollar))
     return MatchOperand_NoMatch;
 
   // Eat the $ prefix.
   getLexer().Lex();
   if (getLexer().getKind() != AsmToken::Identifier)

 }
 
 OperandMatchResultTy
 LoongArchAsmParser::parseImmediate(OperandVector &Operands) {
   SMLoc S = getLoc();
   SMLoc E;
   const MCExpr *Res;
 
+  switch (getLexer().getKind()) {
+  default:
+    return MatchOperand_NoMatch;
+  case AsmToken::LParen:
+  case AsmToken::Dot:
+  case AsmToken::Minus:
+  case AsmToken::Plus:
+  case AsmToken::Exclaim:
+  case AsmToken::Tilde:
+  case AsmToken::Integer:
+  case AsmToken::String:
+  case AsmToken::Identifier:
     if (getParser().parseExpression(Res, E))
       return MatchOperand_ParseFail;
+    break;
+  case AsmToken::Percent:
+    return parseOperandWithModifier(Operands);
+  }
 
   Operands.push_back(LoongArchOperand::createImm(Res, S, E));
   return MatchOperand_Success;
 }
 
+OperandMatchResultTy
+LoongArchAsmParser::parseOperandWithModifier(OperandVector &Operands) {
+  SMLoc S = getLoc();
+  SMLoc E;
+
+  if (getLexer().getKind() != AsmToken::Percent) {
+    Error(getLoc(), "expected '%' for operand modifier");
+    return MatchOperand_ParseFail;
+  }
+
+  getParser().Lex(); // Eat '%'
+
+  if (getLexer().getKind() != AsmToken::Identifier) {
+    Error(getLoc(), "expected valid identifier for operand modifier");
+    return MatchOperand_ParseFail;
+  }
+  StringRef Identifier = getParser().getTok().getIdentifier();
+  LoongArchMCExpr::VariantKind VK =
+      LoongArchMCExpr::getVariantKindForName(Identifier);
+  if (VK == LoongArchMCExpr::VK_LoongArch_Invalid) {
+    Error(getLoc(), "unrecognized operand modifier");
+    return MatchOperand_ParseFail;
+  }
+
+  getParser().Lex(); // Eat the identifier
+  if (getLexer().getKind() != AsmToken::LParen) {
+    Error(getLoc(), "expected '('");
+    return MatchOperand_ParseFail;
+  }
+  getParser().Lex(); // Eat '('
+
+  const MCExpr *SubExpr;
+  if (getParser().parseParenExpression(SubExpr, E)) {
+    return MatchOperand_ParseFail;
+  }
+
+  const MCExpr *ModExpr = LoongArchMCExpr::create(SubExpr, VK, getContext());
+  Operands.push_back(LoongArchOperand::createImm(ModExpr, S, E));
+  return MatchOperand_Success;
+}
+
+OperandMatchResultTy
+LoongArchAsmParser::parseSImm26Operand(OperandVector &Operands) {
+  SMLoc S = getLoc();
+  const MCExpr *Res;
+
+  if (getLexer().getKind() == AsmToken::Percent)
+    return parseOperandWithModifier(Operands);
+
+  if (getLexer().getKind() != AsmToken::Identifier)
+    return MatchOperand_NoMatch;
+
+  StringRef Identifier;
+  if (getParser().parseIdentifier(Identifier))
+    return MatchOperand_ParseFail;
+
+  SMLoc E = SMLoc::getFromPointer(S.getPointer() + Identifier.size());
+
+  MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
+  Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
+  Res = LoongArchMCExpr::create(Res, LoongArchMCExpr::VK_LoongArch_CALL,
+                                getContext());
+  Operands.push_back(LoongArchOperand::createImm(Res, S, E));
+  return MatchOperand_Success;
+}
+
 /// Looks at a token type and creates the relevant operand from this
 /// information, adding to Operands. Return true upon an error.
 bool LoongArchAsmParser::parseOperand(OperandVector &Operands,
                                       StringRef Mnemonic) {
+  // Check if the current operand has a custom associated parser, if so, try to
+  // custom parse the operand, or fallback to the general approach.
+  OperandMatchResultTy Result =
+      MatchOperandParserImpl(Operands, Mnemonic, /*ParseForAllFeatures=*/true);
+  if (Result == MatchOperand_Success)
+    return false;
+  if (Result == MatchOperand_ParseFail)
+    return true;
+
   if (parseRegister(Operands) == MatchOperand_Success ||
       parseImmediate(Operands) == MatchOperand_Success)
     return false;
 
   // Finally we have exhausted all options and must declare defeat.
   Error(getLoc(), "unknown operand");
   return true;
 }
return generateImmOutOfRangeError(Operands, ErrorInfo, /*Lower=*/0,
                                       /*Upper=*/(1 << 6) - 1);
   case Match_InvalidUImm12:
     return generateImmOutOfRangeError(Operands, ErrorInfo, /*Lower=*/0,
                                       /*Upper=*/(1 << 12) - 1);
   case Match_InvalidUImm15:
     return generateImmOutOfRangeError(Operands, ErrorInfo, /*Lower=*/0,
                                       /*Upper=*/(1 << 15) - 1);
   case Match_InvalidSImm12:
-    return generateImmOutOfRangeError(Operands, ErrorInfo, /*Lower=*/-(1 << 11),
-                                      /*Upper=*/(1 << 11) - 1);
+    return generateImmOutOfRangeError(
+        Operands, ErrorInfo, /*Lower=*/-(1 << 11),
+        /*Upper=*/(1 << 11) - 1,
+        "operand must be a symbol with modifier (e.g. %pc_lo12) or an integer "
+        "in the range");
   case Match_InvalidSImm14lsl2:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, /*Lower=*/-(1 << 15), /*Upper=*/(1 << 15) - 4,
         "immediate must be a multiple of 4 in the range");
   case Match_InvalidSImm16:
     return generateImmOutOfRangeError(Operands, ErrorInfo, /*Lower=*/-(1 << 15),
                                       /*Upper=*/(1 << 15) - 1);
   case Match_InvalidSImm16lsl2:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, /*Lower=*/-(1 << 17), /*Upper=*/(1 << 17) - 4,
         "immediate must be a multiple of 4 in the range");
   case Match_InvalidSImm20:
     return generateImmOutOfRangeError(Operands, ErrorInfo, /*Lower=*/-(1 << 19),
                                       /*Upper=*/(1 << 19) - 1);
+  case Match_InvalidSImm20pcalau12i:
+    return generateImmOutOfRangeError(
+        Operands, ErrorInfo, /*Lower=*/-(1 << 19),
+        /*Upper=*/(1 << 19) - 1,
+        "operand must be a symbol with modifier (e.g. %pc_hi20) or an integer "
+        "in the range");
   case Match_InvalidSImm21lsl2:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, /*Lower=*/-(1 << 22), /*Upper=*/(1 << 22) - 4,
         "immediate must be a multiple of 4 in the range");
-  case Match_InvalidSImm26lsl2:
+  case Match_InvalidSImm26Operand:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, /*Lower=*/-(1 << 27), /*Upper=*/(1 << 27) - 4,
-        "immediate must be a multiple of 4 in the range");
+        "operand must be a bare symbol name or an immediate must be a multiple "
+        "of 4 in the range");
   }
   llvm_unreachable("Unknown match type detected!");
 }
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchAsmParser() {
   RegisterMCAsmParser<LoongArchAsmParser> X(getTheLoongArch32Target());
   RegisterMCAsmParser<LoongArchAsmParser> Y(getTheLoongArch64Target());
 }

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

 //===----------------------------------------------------------------------===//
 
 #include "LoongArchISelLowering.h"
 #include "LoongArch.h"
 #include "LoongArchMachineFunctionInfo.h"
 #include "LoongArchRegisterInfo.h"
 #include "LoongArchSubtarget.h"
 #include "LoongArchTargetMachine.h"
+#include "MCTargetDesc/LoongArchBaseInfo.h"
 #include "MCTargetDesc/LoongArchMCTargetDesc.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/KnownBits.h"
 
 using namespace llvm;
 
SDValue LoongArchTargetLowering::lowerGlobalAddress(SDValue Op,
                                                     SelectionDAG &DAG) const {
   SDLoc DL(Op);
   EVT Ty = getPointerTy(DAG.getDataLayout());
   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
   unsigned ADDIOp = Subtarget.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
 
   // TODO: Support dso_preemptable and target flags.
   if (GV->isDSOLocal()) {
-    SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty);
-    SDValue AddrHi(DAG.getMachineNode(LoongArch::PCALAU12I, DL, Ty, GA), 0);
-    SDValue Addr(DAG.getMachineNode(ADDIOp, DL, Ty, AddrHi, GA), 0);
-    return Addr;
+    SDValue GAHi =
+        DAG.getTargetGlobalAddress(GV, DL, Ty, 0, LoongArchII::MO_PCREL_HI);
+    SDValue GALo =
+        DAG.getTargetGlobalAddress(GV, DL, Ty, 0, LoongArchII::MO_PCREL_LO);
+    SDValue AddrHi(DAG.getMachineNode(LoongArch::PCALAU12I, DL, Ty, GAHi), 0);
+
+    return SDValue(DAG.getMachineNode(ADDIOp, DL, Ty, AddrHi, GALo), 0);
   }
   report_fatal_error("Unable to lowerGlobalAddress");
 }
 
 SDValue LoongArchTargetLowering::lowerShiftLeftParts(SDValue Op,
                                                      SelectionDAG &DAG) const {
   SDLoc DL(Op);
   SDValue Lo = Op.getOperand(0);
LoongArchTargetLowering::LowerCall(CallLoweringInfo &CLI,
   for (auto &Reg : RegsToPass) {
     Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
     Glue = Chain.getValue(1);
   }
 
   // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
   // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
   // split it and then direct call can be matched by PseudoCALL.
-  // FIXME: Add target flags for relocation.
-  if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee))
-    Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT);
-  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
-    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT);
+  if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
+    const GlobalValue *GV = S->getGlobal();
+    unsigned OpFlags =
+        getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV)
+            ? LoongArchII::MO_CALL
+            : LoongArchII::MO_CALL_PLT;
+    Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT, 0, OpFlags);
+  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
+    unsigned OpFlags = getTargetMachine().shouldAssumeDSOLocal(
+                           *MF.getFunction().getParent(), nullptr)
+                           ? LoongArchII::MO_CALL
+                           : LoongArchII::MO_CALL_PLT;
+    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, OpFlags);
+  }
 
   // The first call operand is the chain and the second is the target address.
   SmallVector<SDValue> Ops;
   Ops.push_back(Chain);
   Ops.push_back(Callee);
 
   // Add argument registers to the end of the list so that they are
   // known live into the call.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 }
 
 def simm16_lsl2_br : Operand<OtherVT> {
   let ParserMatchClass = SImmAsmOperand<16, "lsl2">;
   let EncoderMethod = "getImmOpValueAsr2";
   let DecoderMethod = "decodeSImmOperand<16, 2>";
 }
 
-def simm20 : Operand<GRLenVT> {
-  let ParserMatchClass = SImmAsmOperand<20>;
+class SImm20Operand : Operand<GRLenVT> {
   let DecoderMethod = "decodeSImmOperand<20>";
 }
 
+def simm20 : SImm20Operand {
+  let ParserMatchClass = SImmAsmOperand<20>;
+}
+
+def simm20_pcalau12i : SImm20Operand {
+  let ParserMatchClass = SImmAsmOperand<20, "pcalau12i">;
+}
+
 def simm21_lsl2 : Operand<OtherVT> {
   let ParserMatchClass = SImmAsmOperand<21, "lsl2">;
   let EncoderMethod = "getImmOpValueAsr2";
   let DecoderMethod = "decodeSImmOperand<21, 2>";
 }
 
-def simm26_lsl2 : Operand<OtherVT> {
-  let ParserMatchClass = SImmAsmOperand<26, "lsl2">;
+// TODO: Need split the ParserMethod/PredicateMethod for call/jump/tailcall.
+def SImm26Operand: AsmOperandClass {
+  let Name = "SImm26Operand";
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = "InvalidSImm26Operand";
+  let ParserMethod = "parseSImm26Operand";
+}
+
+// A symbol or an imm used in B/PseudoBR.
+def simm26_b : Operand<OtherVT> {
+  let ParserMatchClass = SImm26Operand;
+  let EncoderMethod = "getImmOpValueAsr2";
+  let DecoderMethod = "decodeSImmOperand<26, 2>";
+}
+
+// A symbol or an imm used in BL/PseudoCALL.
+def simm26_bl : Operand<GRLenVT> {
+  let ParserMatchClass = SImm26Operand;
   let EncoderMethod = "getImmOpValueAsr2";
   let DecoderMethod = "decodeSImmOperand<26, 2>";
 }
 
 // Standalone (codegen-only) immleaf patterns.
 
 // A 12-bit signed immediate plus one where the imm range will be [-2047, 2048].
 def simm12_plus1 : ImmLeaf<GRLenVT,

 def fpimm1    : PatLeaf<(fpimm), [{return N->isExactlyValue(+1.0);}]>;
 
 // Return an immediate subtracted from 32.
 def ImmSubFrom32 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
-def CallSymbol: AsmOperandClass {
-  let Name = "CallSymbol";
-  let RenderMethod = "addImmOperands";
-  let PredicateMethod = "isImm";
-}
-
-// A bare symbol used in call only.
-def call_symbol : Operand<iPTR> {
-  let ParserMatchClass = CallSymbol;
-}
-
 def BaseAddr : ComplexPattern<iPTR, 1, "SelectBaseAddr">;
 
 //===----------------------------------------------------------------------===//
 // Instruction Formats
 //===----------------------------------------------------------------------===//
 
 include "LoongArchInstrFormats.td"
 include "LoongArchFloatInstrFormats.td"

 }
 class BrCCZ_1RI21<bits<6> op, string opstr>
     : Fmt1RI21<op, (outs), (ins GPR:$rj, simm21_lsl2:$imm21), opstr,
                "$rj, $imm21"> {
   let isBranch = 1;
   let isTerminator = 1;
 }
 class Br_I26<bits<6> op, string opstr>
-    : FmtI26<op, (outs), (ins simm26_lsl2:$imm26), opstr, "$imm26"> {
+    : FmtI26<op, (outs), (ins simm26_b:$imm26), opstr, "$imm26"> {
   let isBranch = 1;
   let isTerminator = 1;
 }
 
 let mayLoad = 1 in {
 class LOAD_3R<bits<17> op, string opstr>
     : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), opstr, "$rd, $rj, $rk">;
 class LOAD_2RI12<bits<10> op, string opstr>

 def ALSL_W : ALU_3RI2<0b000000000000010, "alsl.w", uimm2_plus1>;
 def LU12I_W : ALU_1RI20<0b0001010, "lu12i.w", simm20>;
 def SLT  : ALU_3R<0b00000000000100100, "slt">;
 def SLTU : ALU_3R<0b00000000000100101, "sltu">;
 def SLTI  : ALU_2RI12<0b0000001000, "slti", simm12>;
 def SLTUI : ALU_2RI12<0b0000001001, "sltui", simm12>;
 def PCADDI    : ALU_1RI20<0b0001100, "pcaddi", simm20>;
 def PCADDU12I : ALU_1RI20<0b0001110, "pcaddu12i", simm20>;
-def PCALAU12I : ALU_1RI20<0b0001101, "pcalau12i", simm20>;
+def PCALAU12I : ALU_1RI20<0b0001101, "pcalau12i", simm20_pcalau12i>;
 def AND  : ALU_3R<0b00000000000101001, "and">;
 def OR   : ALU_3R<0b00000000000101010, "or">;
 def NOR  : ALU_3R<0b00000000000101000, "nor">;
 def XOR  : ALU_3R<0b00000000000101011, "xor">;
 def ANDN : ALU_3R<0b00000000000101101, "andn">;
 def ORN  : ALU_3R<0b00000000000101100, "orn">;
 def ANDI : ALU_2RI12<0b0000001101, "andi", uimm12>;
 def ORI  : ALU_2RI12<0b0000001110, "ori", uimm12>;

 def BLT  : BrCC_2RI16<0b011000, "blt">;
 def BGE  : BrCC_2RI16<0b011001, "bge">;
 def BLTU : BrCC_2RI16<0b011010, "bltu">;
 def BGEU : BrCC_2RI16<0b011011, "bgeu">;
 def BEQZ : BrCCZ_1RI21<0b010000, "beqz">;
 def BNEZ : BrCCZ_1RI21<0b010001, "bnez">;
 def B : Br_I26<0b010100, "b">;
 
-let isCall = 1 in
-def BL : FmtI26<0b010101, (outs), (ins simm26_lsl2:$imm26), "bl", "$imm26">;
+let isCall = 1, Defs=[R1] in
+def BL : FmtI26<0b010101, (outs), (ins simm26_bl:$imm26), "bl", "$imm26">;
 def JIRL : Fmt2RI16<0b010011, (outs GPR:$rd),
                     (ins GPR:$rj, simm16_lsl2:$imm16), "jirl",
                     "$rd, $rj, $imm16">;
 
 // Common Memory Access Instructions
 def LD_B  : LOAD_2RI12<0b0010100000, "ld.b">;
 def LD_H  : LOAD_2RI12<0b0010100001, "ld.h">;
 def LD_W  : LOAD_2RI12<0b0010100010, "ld.w">;

 def : Pat<(brcond GPR:$rj, bb:$imm21), (BNEZ GPR:$rj, bb:$imm21)>;
 
 def : Pat<(brcond (GRLenVT (seteq GPR:$rj, 0)), bb:$imm21),
           (BEQZ GPR:$rj, bb:$imm21)>;
 def : Pat<(brcond (GRLenVT (setne GPR:$rj, 0)), bb:$imm21),
           (BNEZ GPR:$rj, bb:$imm21)>;
 
 let isBarrier = 1, isBranch = 1, isTerminator = 1 in
-def PseudoBR : Pseudo<(outs), (ins simm26_lsl2:$imm26), [(br bb:$imm26)]>,
-               PseudoInstExpansion<(B simm26_lsl2:$imm26)>;
+def PseudoBR : Pseudo<(outs), (ins simm26_b:$imm26), [(br bb:$imm26)]>,
+               PseudoInstExpansion<(B simm26_b:$imm26)>;
 
 let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
 def PseudoBRIND : Pseudo<(outs), (ins GPR:$rj, simm16_lsl2:$imm16), []>,
                   PseudoInstExpansion<(JIRL R0, GPR:$rj, simm16_lsl2:$imm16)>;
 
 def : Pat<(brind GPR:$rj), (PseudoBRIND GPR:$rj, 0)>;
 def : Pat<(brind (add GPR:$rj, simm16_lsl2:$imm16)),
           (PseudoBRIND GPR:$rj, simm16_lsl2:$imm16)>;
 
 let isCall = 1, Defs = [R1] in
-def PseudoCALL : Pseudo<(outs), (ins call_symbol:$func), []> {
+def PseudoCALL : Pseudo<(outs), (ins simm26_bl:$func), []> {
   let AsmString = "bl\t$func";
 }
 
 def : Pat<(loongarch_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>;
 def : Pat<(loongarch_call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
 
 let isCall = 1, Defs = [R1] in
 def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rj),

llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp

 //=- LoongArchMCInstLower.cpp - Convert LoongArch MachineInstr to an MCInst -=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains code to lower LoongArch MachineInstrs to their
 // corresponding MCInst records.
 //
 //===----------------------------------------------------------------------===//
 
 #include "LoongArch.h"
 #include "LoongArchSubtarget.h"
+#include "MCTargetDesc/LoongArchBaseInfo.h"
+#include "MCTargetDesc/LoongArchMCExpr.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
                                     const AsmPrinter &AP) {
   MCContext &Ctx = AP.OutContext;
+  LoongArchMCExpr::VariantKind Kind;
 
-  // TODO: Processing target flags.
+  switch (MO.getTargetFlags()) {
+  default:
+    llvm_unreachable("Unknown target flag on GV operand");
+  case LoongArchII::MO_None:
+    Kind = LoongArchMCExpr::VK_LoongArch_None;
+    break;
+  case LoongArchII::MO_CALL:
+    Kind = LoongArchMCExpr::VK_LoongArch_CALL;
+    break;
+  case LoongArchII::MO_CALL_PLT:
+    Kind = LoongArchMCExpr::VK_LoongArch_CALL_PLT;
+    break;
+  case LoongArchII::MO_PCREL_HI:
+    Kind = LoongArchMCExpr::VK_LoongArch_PCREL_HI;
+    break;
+  case LoongArchII::MO_PCREL_LO:
+    Kind = LoongArchMCExpr::VK_LoongArch_PCREL_LO;
+    break;
+    // TODO: Handle more target-flags.
+  }
 
   const MCExpr *ME =
       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
 
   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
     ME = MCBinaryExpr::createAdd(
         ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
 
+  if (Kind != LoongArchMCExpr::VK_LoongArch_None)
+    ME = LoongArchMCExpr::create(ME, Kind, Ctx);
   return MCOperand::createExpr(ME);
 }
 
 bool llvm::lowerLoongArchMachineOperandToMCOperand(const MachineOperand &MO,
                                                    MCOperand &MCOp,
                                                    const AsmPrinter &AP) {
   switch (MO.getType()) {
   default:

llvm/lib/Target/LoongArch/MCTargetDesc/CMakeLists.txt

 add_llvm_component_library(LLVMLoongArchDesc
   LoongArchAsmBackend.cpp
   LoongArchBaseInfo.cpp
   LoongArchELFObjectWriter.cpp
   LoongArchELFStreamer.cpp
   LoongArchInstPrinter.cpp
   LoongArchMCAsmInfo.cpp
-  LoongArchMCTargetDesc.cpp
   LoongArchMCCodeEmitter.cpp
+  LoongArchMCExpr.cpp
+  LoongArchMCTargetDesc.cpp
   LoongArchMatInt.cpp
   LoongArchTargetStreamer.cpp
 
   LINK_COMPONENTS
   MC
   LoongArchInfo
   Support
 
   ADD_TO_COMPONENT
   LoongArch
   )

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h

 //===-- LoongArchAsmBackend.h - LoongArch Assembler Backend ---*- C++ -*---===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the LoongArchAsmBackend class.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHASMBACKEND_H
 #define LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHASMBACKEND_H
 
 #include "MCTargetDesc/LoongArchBaseInfo.h"
+#include "MCTargetDesc/LoongArchFixupKinds.h"
 #include "MCTargetDesc/LoongArchMCTargetDesc.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 
 namespace llvm {
 
 class LoongArchAsmBackend : public MCAsmBackend {
public:
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override {
     return false;
   }
 
   unsigned getNumFixupKinds() const override {
-    // FIXME: Implement this when we define fixup kind
-    return 0;
+    return LoongArch::NumTargetFixupKinds;
   }
 
+  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
+
   void relaxInstruction(MCInst &Inst,
                         const MCSubtargetInfo &STI) const override {}
 
   bool writeNopData(raw_ostream &OS, uint64_t Count,
                     const MCSubtargetInfo *STI) const override;
 
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override;
 };
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHASMBACKEND_H

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp

 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/Support/Endian.h"
 #include "llvm/Support/EndianStream.h"
 
 #define DEBUG_TYPE "loongarch-asmbackend"
 
 using namespace llvm;
 
+const MCFixupKindInfo &
+LoongArchAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
+  const static MCFixupKindInfo Infos[] = {
+      // This table *must* be in the order that the fixup_* kinds are defined in
+      // LoongArchFixupKinds.h.
+      //
+      // {name, offset, bits, flags}
+      {"fixup_loongarch_b26", 0, 26, 0},
+      {"fixup_loongarch_pcala_hi20", 5, 20, MCFixupKindInfo::FKF_IsPCRel},
+      {"fixup_loongarch_pcala_lo12", 10, 12, MCFixupKindInfo::FKF_IsPCRel},
+      // TODO: Add more fixup kinds.
+  };
+
+  static_assert((array_lengthof(Infos)) == LoongArch::NumTargetFixupKinds,
+                "Not all fixup kinds added to Infos array");
+
+  if (Kind < FirstTargetFixupKind)
+    return MCAsmBackend::getFixupKindInfo(Kind);
+
+  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
+         "Invalid kind!");
+  return Infos[Kind - FirstTargetFixupKind];
+}
+
 void LoongArchAsmBackend::applyFixup(const MCAssembler &Asm,
                                      const MCFixup &Fixup,
                                      const MCValue &Target,
                                      MutableArrayRef<char> Data, uint64_t Value,
                                      bool IsResolved,
                                      const MCSubtargetInfo *STI) const {
   // TODO: Apply the Value for given Fixup into the provided data fragment.
   return;

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchBaseInfo.h

 #include "MCTargetDesc/LoongArchMCTargetDesc.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/SubtargetFeature.h"
 
 namespace llvm {
 
+// This namespace holds all of the target specific flags that instruction info
+// tracks.
+namespace LoongArchII {
+enum {
+  MO_None,
+  MO_CALL,
+  MO_CALL_PLT,
+  MO_PCREL_HI,
+  MO_PCREL_LO,
+  // TODO: Add more flags.
+};
+} // end namespace LoongArchII
+
 namespace LoongArchABI {
 enum ABI {
   ABI_ILP32S,
   ABI_ILP32F,
   ABI_ILP32D,
   ABI_LP64S,
   ABI_LP64F,
   ABI_LP64D,

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp

 //===-- LoongArchELFObjectWriter.cpp - LoongArch ELF Writer ---*- C++ -*---===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
+#include "MCTargetDesc/LoongArchFixupKinds.h"
 #include "MCTargetDesc/LoongArchMCTargetDesc.h"
+#include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCFixup.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/Support/ErrorHandling.h"
 
 using namespace llvm;
 
unsigned LoongArchELFObjectWriter::getRelocType(MCContext &Ctx,
                                                 bool IsPCRel) const {
   // Determine the type of the relocation
   unsigned Kind = Fixup.getTargetKind();
 
   if (Kind >= FirstLiteralRelocationKind)
     return Kind - FirstLiteralRelocationKind;
 
   switch (Kind) {
-  // TODO: Implement this when we defined fixup kind.
   default:
+    Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");
     return ELF::R_LARCH_NONE;
+  case FK_Data_1:
+    Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
+    return ELF::R_LARCH_NONE;
+  case FK_Data_2:
+    Ctx.reportError(Fixup.getLoc(), "2-byte data relocations not supported");
+    return ELF::R_LARCH_NONE;
+  case FK_Data_4:
+    return ELF::R_LARCH_32;
+  case FK_Data_8:
+    return ELF::R_LARCH_64;
+  case LoongArch::fixup_loongarch_pcala_hi20:
+    return ELF::R_LARCH_PCALA_HI20;
+  case LoongArch::fixup_loongarch_pcala_lo12:
+    return ELF::R_LARCH_PCALA_LO12;
+  case LoongArch::fixup_loongarch_b26:
+    return ELF::R_LARCH_B26;
+    // TODO: Handle more fixup-kinds.
   }
 }
 
 std::unique_ptr<MCObjectTargetWriter>
 llvm::createLoongArchELFObjectWriter(uint8_t OSABI, bool Is64Bit) {
   return std::make_unique<LoongArchELFObjectWriter>(OSABI, Is64Bit);
 }

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h

+//===- LoongArchFixupKinds.h - LoongArch Specific Fixup Entries -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHFIXUPKINDS_H
+#define LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHFIXUPKINDS_H
+
+#include "llvm/MC/MCFixup.h"
+
+#undef LoongArch
+
+namespace llvm {
+namespace LoongArch {
+//
+// This table *must* be in the same order of
+// MCFixupKindInfo Infos[LoongArch::NumTargetFixupKinds] in
+// LoongArchAsmBackend.cpp.
+//
+enum Fixups {
+  // 26-bit fixup for symbol references in the b/bl instructions.
+  fixup_loongarch_b26 = FirstTargetFixupKind,
+  // 20-bit fixup corresponding to %pc_hi20(foo) for instruction pcalau12i.
+  fixup_loongarch_pcala_hi20,
+  // 12-bit fixup corresponding to %pc_lo12(foo) for instructions addi.w/d.
+  fixup_loongarch_pcala_lo12,
+  // TODO: Add more fixup kind.
+
+  // Used as a sentinel, must be the last.
+  fixup_loongarch_invalid,
+  NumTargetFixupKinds = fixup_loongarch_invalid - FirstTargetFixupKind
+};
+} // end namespace LoongArch
+} // end namespace llvm
+
+#endif

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp

 //=- LoongArchMCCodeEmitter.cpp - Convert LoongArch code to machine code --===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the LoongArchMCCodeEmitter class.
 //
 //===----------------------------------------------------------------------===//
 
+#include "LoongArchFixupKinds.h"
 #include "MCTargetDesc/LoongArchBaseInfo.h"
+#include "MCTargetDesc/LoongArchMCExpr.h"
 #include "MCTargetDesc/LoongArchMCTargetDesc.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Support/Casting.h"
 #include "llvm/Support/EndianStream.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "mccodeemitter"
 
 namespace {
 class LoongArchMCCodeEmitter : public MCCodeEmitter {
   LoongArchMCCodeEmitter(const LoongArchMCCodeEmitter &) = delete;
   void operator=(const LoongArchMCCodeEmitter &) = delete;
   MCContext &Ctx;
   MCInstrInfo const &MCII;
 
 public:
   LoongArchMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
       : Ctx(ctx), MCII(MCII) {}
 
   ~LoongArchMCCodeEmitter() override {}
 
   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override;
 
+  void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
+                          SmallVectorImpl<MCFixup> &Fixups,
+                          const MCSubtargetInfo &STI) const;
+
   /// TableGen'erated function for getting the binary encoding for an
   /// instruction.
   uint64_t getBinaryCodeForInstr(const MCInst &MI,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
 
   /// Return binary encoding of operand. If the machine operand requires
   /// relocation, record the relocation and return zero.
public:
   /// Return binary encoding of an immediate operand specified by OpNo.
   /// The value returned is the value of the immediate shifted right
   //  arithmetically by 2.
   /// Note that this function is dedicated to specific immediate types,
   /// e.g. simm14_lsl2, simm16_lsl2, simm21_lsl2 and simm26_lsl2.
   unsigned getImmOpValueAsr2(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
+
+  unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO,
+                          SmallVectorImpl<MCFixup> &Fixups,
+                          const MCSubtargetInfo &STI) const;
 };
 } // end namespace
 
 unsigned
 LoongArchMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                                           SmallVectorImpl<MCFixup> &Fixups,
                                           const MCSubtargetInfo &STI) const {
 
   if (MO.isReg())
     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
 
   if (MO.isImm())
     return static_cast<unsigned>(MO.getImm());
 
-  llvm_unreachable("Unhandled expression!");
+  // MO must be an Expr.
+  assert(MO.isExpr());
+  return getExprOpValue(MI, MO, Fixups, STI);
 }
 
 unsigned
 LoongArchMCCodeEmitter::getImmOpValueSub1(const MCInst &MI, unsigned OpNo,
                                           SmallVectorImpl<MCFixup> &Fixups,
                                           const MCSubtargetInfo &STI) const {
   return MI.getOperand(OpNo).getImm() - 1;
 }
 
 unsigned
 LoongArchMCCodeEmitter::getImmOpValueAsr2(const MCInst &MI, unsigned OpNo,
                                           SmallVectorImpl<MCFixup> &Fixups,
                                           const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+
+  if (MO.isImm()) {
     unsigned Res = MI.getOperand(OpNo).getImm();
     assert((Res & 3) == 0 && "lowest 2 bits are non-zero");
     return Res >> 2;
   }
 
+  return getExprOpValue(MI, MO, Fixups, STI);
+}
+
+unsigned
+LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
+                                       SmallVectorImpl<MCFixup> &Fixups,
+                                       const MCSubtargetInfo &STI) const {
+  assert(MO.isExpr() && "getExprOpValue expects only expressions");
+  const MCExpr *Expr = MO.getExpr();
+  MCExpr::ExprKind Kind = Expr->getKind();
+  LoongArch::Fixups FixupKind = LoongArch::fixup_loongarch_invalid;
+  if (Kind == MCExpr::Target) {
+    const LoongArchMCExpr *LAExpr = cast<LoongArchMCExpr>(Expr);
+
+    switch (LAExpr->getKind()) {
+    case LoongArchMCExpr::VK_LoongArch_None:
+    case LoongArchMCExpr::VK_LoongArch_Invalid:
+      llvm_unreachable("Unhandled fixup kind!");
+    case LoongArchMCExpr::VK_LoongArch_PCREL_HI:
+      FixupKind = LoongArch::fixup_loongarch_pcala_hi20;
+      break;
+    case LoongArchMCExpr::VK_LoongArch_PCREL_LO:
+      FixupKind = LoongArch::fixup_loongarch_pcala_lo12;
+      break;
+    case LoongArchMCExpr::VK_LoongArch_CALL:
+    case LoongArchMCExpr::VK_LoongArch_CALL_PLT:
+      FixupKind = LoongArch::fixup_loongarch_b26;
+      break;
+    }
+  }
+
+  assert(FixupKind != LoongArch::fixup_loongarch_invalid &&
+         "Unhandled expression!");
+
+  Fixups.push_back(
+      MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
+  return 0;
+}
+
+void LoongArchMCCodeEmitter::expandFunctionCall(
+    const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
+    const MCSubtargetInfo &STI) const {
+  MCOperand Func = MI.getOperand(0);
+  MCInst TmpInst = Func.isExpr()
+                       ? MCInstBuilder(LoongArch::BL).addExpr(Func.getExpr())
+                       : MCInstBuilder(LoongArch::BL).addImm(Func.getImm());
+  uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
+  support::endian::write(OS, Binary, support::little);
+}
+
 void LoongArchMCCodeEmitter::encodeInstruction(
     const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
     const MCSubtargetInfo &STI) const {
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   // Get byte count of instruction.
   unsigned Size = Desc.getSize();
 
+  if (MI.getOpcode() == LoongArch::PseudoCALL)
+    return expandFunctionCall(MI, OS, Fixups, STI);
+
   switch (Size) {
   default:
     llvm_unreachable("Unhandled encodeInstruction length!");
   case 4: {
     uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
     support::endian::write(OS, Bits, support::little);
     break;
   }

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h

+//= LoongArchMCExpr.h - LoongArch specific MC expression classes -*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes LoongArch-specific MCExprs, used for modifiers like
+// "%pc_hi20" or "%pc_lo12" etc.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHMCEXPR_H
+#define LLVM_LIB_TARGET_LOONGARCH_MCTARGETDESC_LOONGARCHMCEXPR_H
+
+#include "llvm/MC/MCExpr.h"
+
+namespace llvm {
+
+class StringRef;
+
+class LoongArchMCExpr : public MCTargetExpr {
+public:
+  enum VariantKind {
+    // TODO: Add more target kinds.
+    VK_LoongArch_None,
+    VK_LoongArch_CALL,
+    VK_LoongArch_CALL_PLT,
+    VK_LoongArch_PCREL_HI,
+    VK_LoongArch_PCREL_LO,
+    VK_LoongArch_Invalid // Must be the last item.
+  };
+
+private:
+  const MCExpr *Expr;
+  const VariantKind Kind;
+
+  explicit LoongArchMCExpr(const MCExpr *Expr, VariantKind Kind)
+      : Expr(Expr), Kind(Kind) {}
+
+public:
+  static const LoongArchMCExpr *create(const MCExpr *Expr, VariantKind Kind,
+                                       MCContext &Ctx);
+
+  VariantKind getKind() const { return Kind; }
+  const MCExpr *getSubExpr() const { return Expr; }
+
+  void printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const override;
+  bool evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout,
+                                 const MCFixup *Fixup) const override;
+  void visitUsedExpr(MCStreamer &Streamer) const override;
+  MCFragment *findAssociatedFragment() const override {
+    return getSubExpr()->findAssociatedFragment();
+  }
+
+  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
+
+  static bool classof(const MCExpr *E) {
+    return E->getKind() == MCExpr::Target;
+  }
+
+  static StringRef getVariantKindName(VariantKind Kind);
+  static VariantKind getVariantKindForName(StringRef name);
+};
+
+} // end namespace llvm
+
+#endif

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp

+//===-- LoongArchMCExpr.cpp - LoongArch specific MC expression classes ----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the implementation of the assembly expression modifiers
+// accepted by the LoongArch architecture.
+//
+//===----------------------------------------------------------------------===//
+
+#include "LoongArchMCExpr.h"
+#include "LoongArchAsmBackend.h"
+#include "LoongArchFixupKinds.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCValue.h"
+#include "llvm/Support/ErrorHandling.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "loongarch-mcexpr"
+
+const LoongArchMCExpr *
+LoongArchMCExpr::create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx) {
+  return new (Ctx) LoongArchMCExpr(Expr, Kind);
+}
+
+void LoongArchMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
+  VariantKind Kind = getKind();
+  bool HasVariant =
+      ((Kind != VK_LoongArch_None) && (Kind != VK_LoongArch_CALL));
+
+  if (HasVariant)
+    OS << '%' << getVariantKindName(getKind()) << '(';
+  Expr->print(OS, MAI);
+  if (HasVariant)
+    OS << ')';
+}
+
+bool LoongArchMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
+                                                const MCAsmLayout *Layout,
+                                                const MCFixup *Fixup) const {
+  // Explicitly drop the layout and assembler to prevent any symbolic folding in
+  // the expression handling.  This is required to preserve symbolic difference
+  // expressions to emit the paired relocations.
+  if (!getSubExpr()->evaluateAsRelocatable(Res, nullptr, nullptr))
+    return false;
+
+  Res =
+      MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), getKind());
+  // Custom fixup types are not valid with symbol difference expressions.
+  return Res.getSymB() ? getKind() == VK_LoongArch_None : true;
+}
+
+void LoongArchMCExpr::visitUsedExpr(MCStreamer &Streamer) const {
+  Streamer.visitUsedExpr(*getSubExpr());
+}
+
+StringRef LoongArchMCExpr::getVariantKindName(VariantKind Kind) {
+  switch (Kind) {
+  default:
+    llvm_unreachable("Invalid ELF symbol kind");
+  case VK_LoongArch_CALL_PLT:
+    return "plt";
+  case VK_LoongArch_PCREL_HI:
+    return "pc_hi20";
+  case VK_LoongArch_PCREL_LO:
+    return "pc_lo12";
+  }
+}
+
+LoongArchMCExpr::VariantKind
+LoongArchMCExpr::getVariantKindForName(StringRef name) {
+  return StringSwitch<LoongArchMCExpr::VariantKind>(name)
+      .Case("pc_hi20", VK_LoongArch_PCREL_HI)
+      .Case("pc_lo12", VK_LoongArch_PCREL_LO)
+      .Case("plt", VK_LoongArch_CALL_PLT)
+      .Default(VK_LoongArch_Invalid);
+}

llvm/test/CodeGen/LoongArch/analyze-branch.ll

 define void @test_bcc_fallthrough_taken(i64 %in) nounwind {
 ; CHECK-LABEL: test_bcc_fallthrough_taken:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; CHECK-NEXT:    ori $a1, $zero, 42
 ; CHECK-NEXT:    bne $a0, $a1, .LBB0_3
 ; CHECK-NEXT:  # %bb.1: # %true
-; CHECK-NEXT:    bl test_true
+; CHECK-NEXT:    bl %plt(test_true)
 ; CHECK-NEXT:  .LBB0_2: # %true
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB0_3: # %false
-; CHECK-NEXT:    bl test_false
+; CHECK-NEXT:    bl %plt(test_false)
 ; CHECK-NEXT:    b .LBB0_2
   %tst = icmp eq i64 %in, 42
   br i1 %tst, label %true, label %false, !prof !0
 
 ;; Expected layout order is: Entry, TrueBlock, FalseBlock
 ;; Entry->TrueBlock is the common path, which should be taken whenever the
 ;; conditional branch is false.
 

 define void @test_bcc_fallthrough_nottaken(i64 %in) nounwind {
 ; CHECK-LABEL: test_bcc_fallthrough_nottaken:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; CHECK-NEXT:    ori $a1, $zero, 42
 ; CHECK-NEXT:    beq $a0, $a1, .LBB1_1
 ; CHECK-NEXT:  # %bb.3: # %false
-; CHECK-NEXT:    bl test_false
+; CHECK-NEXT:    bl %plt(test_false)
 ; CHECK-NEXT:  .LBB1_2: # %true
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB1_1: # %true
-; CHECK-NEXT:    bl test_true
+; CHECK-NEXT:    bl %plt(test_true)
 ; CHECK-NEXT:    b .LBB1_2
   %tst = icmp eq i64 %in, 42
   br i1 %tst, label %true, label %false, !prof !1
 
 ;; Expected layout order is: Entry, FalseBlock, TrueBlock
 ;; Entry->FalseBlock is the common path, which should be taken whenever the
 ;; conditional branch is false.
 
 true:
   call void @test_true()
   ret void
 
 false:
   call void @test_false()
   ret void
 }

llvm/test/CodeGen/LoongArch/bnez-beqz.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64
 
 declare void @bar()
 
 define void @bnez_i32(i32 signext %0) nounwind {
 ; LA32-LABEL: bnez_i32:
 ; LA32:       # %bb.0: # %start
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    bnez $a0, .LBB0_2
 ; LA32-NEXT:  # %bb.1: # %t
-; LA32-NEXT:    bl bar
+; LA32-NEXT:    bl %plt(bar)
 ; LA32-NEXT:  .LBB0_2: # %f
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: bnez_i32:
 ; LA64:       # %bb.0: # %start
 ; LA64-NEXT:    addi.d $sp, $sp, -16
 ; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-NEXT:    bnez $a0, .LBB0_2
 ; LA64-NEXT:  # %bb.1: # %t
-; LA64-NEXT:    bl bar
+; LA64-NEXT:    bl %plt(bar)
 ; LA64-NEXT:  .LBB0_2: # %f
 ; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-NEXT:    addi.d $sp, $sp, 16
 ; LA64-NEXT:    ret
 start:
   %1 = icmp eq i32 %0, 0
   br i1 %1, label %t, label %f
 
 t:
   tail call void @bar()
   br label %f
 
 f:
   ret void
 }
 
 define void @beqz_i32(i32 signext %0) nounwind {
 ; LA32-LABEL: beqz_i32:
 ; LA32:       # %bb.0: # %start
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    beqz $a0, .LBB1_2
 ; LA32-NEXT:  # %bb.1: # %t
-; LA32-NEXT:    bl bar
+; LA32-NEXT:    bl %plt(bar)
 ; LA32-NEXT:  .LBB1_2: # %f
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: beqz_i32:
 ; LA64:       # %bb.0: # %start
 ; LA64-NEXT:    addi.d $sp, $sp, -16
 ; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-NEXT:    beqz $a0, .LBB1_2
 ; LA64-NEXT:  # %bb.1: # %t
-; LA64-NEXT:    bl bar
+; LA64-NEXT:    bl %plt(bar)
 ; LA64-NEXT:  .LBB1_2: # %f
 ; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-NEXT:    addi.d $sp, $sp, 16
 ; LA64-NEXT:    ret
 start:
   %1 = icmp ne i32 %0, 0
   br i1 %1, label %t, label %f
 
 t:
   tail call void @bar()
   br label %f
 
 f:
   ret void
 }
 
 define void @bnez_i64(i64 %0) nounwind {
 ; LA32-LABEL: bnez_i64:
 ; LA32:       # %bb.0: # %start
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    or $a0, $a0, $a1
 ; LA32-NEXT:    bnez $a0, .LBB2_2
 ; LA32-NEXT:  # %bb.1: # %t
-; LA32-NEXT:    bl bar
+; LA32-NEXT:    bl %plt(bar)
 ; LA32-NEXT:  .LBB2_2: # %f
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: bnez_i64:
 ; LA64:       # %bb.0: # %start
 ; LA64-NEXT:    addi.d $sp, $sp, -16
 ; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-NEXT:    bnez $a0, .LBB2_2
 ; LA64-NEXT:  # %bb.1: # %t
-; LA64-NEXT:    bl bar
+; LA64-NEXT:    bl %plt(bar)
 ; LA64-NEXT:  .LBB2_2: # %f
 ; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-NEXT:    addi.d $sp, $sp, 16
 ; LA64-NEXT:    ret
 start:
   %1 = icmp eq i64 %0, 0
   br i1 %1, label %t, label %f
 
 t:
   tail call void @bar()
   br label %f
 
 f:
   ret void
 }
 
 define void @beqz_i64(i64 %0) nounwind {
 ; LA32-LABEL: beqz_i64:
 ; LA32:       # %bb.0: # %start
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    or $a0, $a0, $a1
 ; LA32-NEXT:    beqz $a0, .LBB3_2
 ; LA32-NEXT:  # %bb.1: # %t
-; LA32-NEXT:    bl bar
+; LA32-NEXT:    bl %plt(bar)
 ; LA32-NEXT:  .LBB3_2: # %f
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: beqz_i64:
 ; LA64:       # %bb.0: # %start
 ; LA64-NEXT:    addi.d $sp, $sp, -16
 ; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-NEXT:    beqz $a0, .LBB3_2
 ; LA64-NEXT:  # %bb.1: # %t
-; LA64-NEXT:    bl bar
+; LA64-NEXT:    bl %plt(bar)
 ; LA64-NEXT:  .LBB3_2: # %f
 ; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-NEXT:    addi.d $sp, $sp, 16
 ; LA64-NEXT:    ret
 start:
   %1 = icmp ne i64 %0, 0
   br i1 %1, label %t, label %f
 
 t:
   tail call void @bar()
   br label %f
 
 f:
   ret void
 }

llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll

 define i64 @caller_i128_in_regs() nounwind {
 ; CHECK-LABEL: caller_i128_in_regs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; CHECK-NEXT:    ori $a0, $zero, 1
 ; CHECK-NEXT:    ori $a1, $zero, 2
 ; CHECK-NEXT:    move $a2, $zero
-; CHECK-NEXT:    bl callee_i128_in_regs
+; CHECK-NEXT:    bl %plt(callee_i128_in_regs)
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
 ; CHECK-NEXT:    ret
   %1 = call i64 @callee_i128_in_regs(i64 1, i128 2)
   ret i64 %1
 }
 
 ;; Check that the stack is used once the GPRs are exhausted.

 ; CHECK-NEXT:    ori $a0, $zero, 1
 ; CHECK-NEXT:    ori $a1, $zero, 2
 ; CHECK-NEXT:    ori $a2, $zero, 3
 ; CHECK-NEXT:    ori $a3, $zero, 4
 ; CHECK-NEXT:    ori $a4, $zero, 5
 ; CHECK-NEXT:    ori $a6, $zero, 6
 ; CHECK-NEXT:    ori $a7, $zero, 7
 ; CHECK-NEXT:    move $a5, $zero
-; CHECK-NEXT:    bl callee_many_scalars
+; CHECK-NEXT:    bl %plt(callee_many_scalars)
 ; CHECK-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 32
 ; CHECK-NEXT:    ret
   %1 = call i64 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i128 5, i64 6, i128 7, i64 8)
   ret i64 %1
 }
 
 ;; Check that i256 is passed indirectly.

 ; CHECK-NEXT:    st.d $zero, $sp, 8
 ; CHECK-NEXT:    st.d $zero, $sp, 56
 ; CHECK-NEXT:    st.d $zero, $sp, 48
 ; CHECK-NEXT:    st.d $zero, $sp, 40
 ; CHECK-NEXT:    ori $a0, $zero, 1
 ; CHECK-NEXT:    st.d $a0, $sp, 32
 ; CHECK-NEXT:    addi.d $a0, $sp, 32
 ; CHECK-NEXT:    addi.d $a1, $sp, 0
-; CHECK-NEXT:    bl callee_large_scalars
+; CHECK-NEXT:    bl %plt(callee_large_scalars)
 ; CHECK-NEXT:    ld.d $ra, $sp, 72 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 80
 ; CHECK-NEXT:    ret
   %1 = call i64 @callee_large_scalars(i256 1, i256 2)
   ret i64 %1
 }
 
 ;; Check that arguments larger than 2*GRLen are handled correctly when their

 ; CHECK-NEXT:    ori $a0, $zero, 1
 ; CHECK-NEXT:    ori $a1, $zero, 2
 ; CHECK-NEXT:    ori $a2, $zero, 3
 ; CHECK-NEXT:    ori $a3, $zero, 4
 ; CHECK-NEXT:    ori $a4, $zero, 5
 ; CHECK-NEXT:    ori $a5, $zero, 6
 ; CHECK-NEXT:    ori $a6, $zero, 7
 ; CHECK-NEXT:    addi.d $a7, $sp, 48
-; CHECK-NEXT:    bl callee_large_scalars_exhausted_regs
+; CHECK-NEXT:    bl %plt(callee_large_scalars_exhausted_regs)
 ; CHECK-NEXT:    ld.d $ra, $sp, 88 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 96
 ; CHECK-NEXT:    ret
   %1 = call i64 @callee_large_scalars_exhausted_regs(
       i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i256 8, i64 9,
       i256 10)
   ret i64 %1
 }

 ; CHECK-NEXT:    st.d $a0, $sp, 16
 ; CHECK-NEXT:    ori $a0, $zero, 3
 ; CHECK-NEXT:    st.d $a0, $sp, 56
 ; CHECK-NEXT:    st.d $a0, $sp, 24
 ; CHECK-NEXT:    ori $a0, $zero, 4
 ; CHECK-NEXT:    st.d $a0, $sp, 64
 ; CHECK-NEXT:    st.d $a0, $sp, 32
 ; CHECK-NEXT:    addi.d $a0, $sp, 8
-; CHECK-NEXT:    bl callee_large_struct
+; CHECK-NEXT:    bl %plt(callee_large_struct)
 ; CHECK-NEXT:    ld.d $ra, $sp, 72 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 80
 ; CHECK-NEXT:    ret
   %ls = alloca %struct.large, align 8
   %a = getelementptr inbounds %struct.large, ptr %ls, i64 0, i32 0
   store i64 1, ptr %a
   %b = getelementptr inbounds %struct.large, ptr %ls, i64 0, i32 1
   store i64 2, ptr %b
; CHECK-NEXT:    ret
   ret i128 -1
 }
 
 define i64 @caller_small_scalar_ret() nounwind {
 ; CHECK-LABEL: caller_small_scalar_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT:    bl callee_small_scalar_ret
+; CHECK-NEXT:    bl %plt(callee_small_scalar_ret)
 ; CHECK-NEXT:    addi.w $a2, $zero, -2
 ; CHECK-NEXT:    xor $a0, $a0, $a2
 ; CHECK-NEXT:    orn $a0, $a0, $a1
 ; CHECK-NEXT:    sltui $a0, $a0, 1
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
 ; CHECK-NEXT:    ret
   %1 = call i128 @callee_small_scalar_ret()
; CHECK-NEXT:    ret
   ret %struct.small { i64 1, ptr null }
 }
 
 define i64 @caller_small_struct_ret() nounwind {
 ; CHECK-LABEL: caller_small_struct_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT:    bl callee_small_struct_ret
+; CHECK-NEXT:    bl %plt(callee_small_struct_ret)
 ; CHECK-NEXT:    add.d $a0, $a0, $a1
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
 ; CHECK-NEXT:    ret
   %1 = call %struct.small @callee_small_struct_ret()
   %2 = extractvalue %struct.small %1, 0
   %3 = extractvalue %struct.small %1, 1
   %4 = ptrtoint ptr %3 to i64

 }
 
 define void @caller_large_scalar_ret() nounwind {
 ; CHECK-LABEL: caller_large_scalar_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -48
 ; CHECK-NEXT:    st.d $ra, $sp, 40 # 8-byte Folded Spill
 ; CHECK-NEXT:    addi.d $a0, $sp, 0
-; CHECK-NEXT:    bl callee_large_scalar_ret
+; CHECK-NEXT:    bl %plt(callee_large_scalar_ret)
 ; CHECK-NEXT:    ld.d $ra, $sp, 40 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 48
 ; CHECK-NEXT:    ret
   %1 = call i256 @callee_large_scalar_ret()
   ret void
 }
 
 ;; Check return struct which size is more than 2*GRLen.

 }
 
 define i64 @caller_large_struct_ret() nounwind {
 ; CHECK-LABEL: caller_large_struct_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -48
 ; CHECK-NEXT:    st.d $ra, $sp, 40 # 8-byte Folded Spill
 ; CHECK-NEXT:    addi.d $a0, $sp, 8
-; CHECK-NEXT:    bl callee_large_struct_ret
+; CHECK-NEXT:    bl %plt(callee_large_struct_ret)
 ; CHECK-NEXT:    ld.d $a0, $sp, 32
 ; CHECK-NEXT:    ld.d $a1, $sp, 8
 ; CHECK-NEXT:    add.d $a0, $a1, $a0
 ; CHECK-NEXT:    ld.d $ra, $sp, 40 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 48
 ; CHECK-NEXT:    ret
   %1 = alloca %struct.large
   call void @callee_large_struct_ret(ptr sret(%struct.large) %1)

 define i64 @caller_float_in_fpr() nounwind {
 ; CHECK-LABEL: caller_float_in_fpr:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; CHECK-NEXT:    ori $a0, $zero, 1
 ; CHECK-NEXT:    movgr2fr.w $fa0, $zero
 ; CHECK-NEXT:    movgr2fr.d $fa1, $zero
-; CHECK-NEXT:    bl callee_float_in_fpr
+; CHECK-NEXT:    bl %plt(callee_float_in_fpr)
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
 ; CHECK-NEXT:    ret
   %1 = call i64 @callee_float_in_fpr(i64 1, float 0.0, double 0.0)
   ret i64 %1
 }
 
 ;; Check that the GPR is used once the FPRs are exhausted.

 ; CHECK-NEXT:    fld.d $fa5, $a1, 0
 ; CHECK-NEXT:    fld.d $fa6, $a0, 0
 ; CHECK-NEXT:    pcalau12i $a0, .LCPI21_6
 ; CHECK-NEXT:    addi.d $a0, $a0, .LCPI21_6
 ; CHECK-NEXT:    fld.d $fa7, $a0, 0
 ; CHECK-NEXT:    ori $a0, $zero, 0
 ; CHECK-NEXT:    lu32i.d $a0, 131072
 ; CHECK-NEXT:    lu52i.d $a0, $a0, 1026
-; CHECK-NEXT:    bl callee_double_in_gpr_exhausted_fprs
+; CHECK-NEXT:    bl %plt(callee_double_in_gpr_exhausted_fprs)
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
 ; CHECK-NEXT:    ret
   %1 = call i64 @callee_double_in_gpr_exhausted_fprs(
       double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0,
       double 7.0, double 8.0, double 9.0)
   ret i64 %1
 }
; CHECK-NEXT:    ret
   ret double 1.0
 }
 
 define i64 @caller_double_ret() nounwind {
 ; CHECK-LABEL: caller_double_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT:    bl callee_double_ret
+; CHECK-NEXT:    bl %plt(callee_double_ret)
 ; CHECK-NEXT:    movfr2gr.d $a0, $fa0
 ; CHECK-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 16
 ; CHECK-NEXT:    ret
   %1 = call double @callee_double_ret()
   %2 = bitcast double %1 to i64
   ret i64 %2
 }

llvm/test/CodeGen/LoongArch/eh-dwarf-cfa.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck --check-prefix=LA32 %s
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck --check-prefix=LA64 %s
 
 define void @dwarf() {
 ; LA32-LABEL: dwarf:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
 ; LA32-NEXT:    addi.w $a0, $sp, 16
-; LA32-NEXT:    bl foo
+; LA32-NEXT:    bl %plt(foo)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: dwarf:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    addi.d $sp, $sp, -16
 ; LA64-NEXT:    .cfi_def_cfa_offset 16
 ; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-NEXT:    .cfi_offset 1, -8
 ; LA64-NEXT:    addi.d $a0, $sp, 16
-; LA64-NEXT:    bl foo
+; LA64-NEXT:    bl %plt(foo)
 ; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-NEXT:    addi.d $sp, $sp, 16
 ; LA64-NEXT:    ret
 entry:
   %0 = call ptr @llvm.eh.dwarf.cfa(i32 0)
   call void @foo(ptr %0)
   ret void
 }
 
 declare void @foo(ptr)
 
 declare ptr @llvm.eh.dwarf.cfa(i32) nounwind

llvm/test/CodeGen/LoongArch/frame.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 %struct.key_t = type { i32, [16 x i8] }
 
 define i32 @test() nounwind {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -32
 ; CHECK-NEXT:    st.d $ra, $sp, 24 # 8-byte Folded Spill
 ; CHECK-NEXT:    st.w $zero, $sp, 16
 ; CHECK-NEXT:    st.d $zero, $sp, 8
 ; CHECK-NEXT:    st.d $zero, $sp, 0
 ; CHECK-NEXT:    addi.d $a0, $sp, 4
-; CHECK-NEXT:    bl test1
+; CHECK-NEXT:    bl %plt(test1)
 ; CHECK-NEXT:    move $a0, $zero
 ; CHECK-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 32
 ; CHECK-NEXT:    ret
   %key = alloca %struct.key_t, align 4
   call void @llvm.memset.p0i8.i64(ptr %key, i8 0, i64 20, i1 false)
   %1 = getelementptr inbounds %struct.key_t, ptr %key, i64 0, i32 1, i64 0
   call void @test1(ptr %1)
   ret i32 0
 }
 
 declare void @llvm.memset.p0i8.i64(ptr, i8, i64, i1)
 
 declare void @test1(ptr)

llvm/test/CodeGen/LoongArch/fsqrt.ll

; LA64D-NEXT:    ret
   ret float %1
 }
 
 define double @fsqrt_f64(double %a) nounwind {
 ; LA32F-LABEL: fsqrt_f64:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    addi.w $sp, $sp, -16
 ; LA32F-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32F-NEXT:    bl sqrt
+; LA32F-NEXT:    bl %plt(sqrt)
 ; LA32F-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32F-NEXT:    addi.w $sp, $sp, 16
 ; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: fsqrt_f64:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    fsqrt.d $fa0, $fa0
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: fsqrt_f64:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    addi.d $sp, $sp, -16
 ; LA64F-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64F-NEXT:    bl sqrt
+; LA64F-NEXT:    bl %plt(sqrt)
 ; LA64F-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64F-NEXT:    addi.d $sp, $sp, 16
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: fsqrt_f64:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    fsqrt.d $fa0, $fa0
 ; LA64D-NEXT:    ret
; LA64D-NEXT:    ret
   ret float %2
 }
 
 define double @frsqrt_f64(double %a) nounwind {
 ; LA32F-LABEL: frsqrt_f64:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    addi.w $sp, $sp, -16
 ; LA32F-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32F-NEXT:    bl sqrt
+; LA32F-NEXT:    bl %plt(sqrt)
 ; LA32F-NEXT:    move $a2, $a0
 ; LA32F-NEXT:    move $a3, $a1
 ; LA32F-NEXT:    lu12i.w $a1, 261888
 ; LA32F-NEXT:    move $a0, $zero
-; LA32F-NEXT:    bl __divdf3
+; LA32F-NEXT:    bl %plt(__divdf3)
 ; LA32F-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32F-NEXT:    addi.w $sp, $sp, 16
 ; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: frsqrt_f64:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    frsqrt.d $fa0, $fa0
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: frsqrt_f64:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    addi.d $sp, $sp, -16
 ; LA64F-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64F-NEXT:    bl sqrt
+; LA64F-NEXT:    bl %plt(sqrt)
 ; LA64F-NEXT:    move $a1, $a0
 ; LA64F-NEXT:    lu52i.d $a0, $zero, 1023
-; LA64F-NEXT:    bl __divdf3
+; LA64F-NEXT:    bl %plt(__divdf3)
 ; LA64F-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64F-NEXT:    addi.d $sp, $sp, 16
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: frsqrt_f64:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    frsqrt.d $fa0, $fa0
 ; LA64D-NEXT:    ret
   %1 = call double @llvm.sqrt.f64(double %a)
   %2 = fdiv double 1.0, %1
   ret double %2
 }

llvm/test/CodeGen/LoongArch/ir-instruction/call.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 < %s | FileCheck --check-prefix=LA32 %s
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck --check-prefix=LA64 %s
 
 declare i32 @external_function(i32)
 
 define i32 @test_call_external(i32 %a) nounwind {
 ; LA32-LABEL: test_call_external:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32-NEXT:    bl external_function
+; LA32-NEXT:    bl %plt(external_function)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_call_external:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $sp, $sp, -16
 ; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT:    bl external_function
+; LA64-NEXT:    bl %plt(external_function)
 ; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-NEXT:    addi.d $sp, $sp, 16
 ; LA64-NEXT:    ret
   %1 = call i32 @external_function(i32 %a)
   ret i32 %1
 }
 
 define i32 @defined_function(i32 %a) nounwind {
; LA64-NEXT:    ret
   ret i32 %1
 }
 
 define i32 @test_call_defined(i32 %a) nounwind {
 ; LA32-LABEL: test_call_defined:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32-NEXT:    bl defined_function
+; LA32-NEXT:    bl %plt(defined_function)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_call_defined:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.d $sp, $sp, -16
 ; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT:    bl defined_function
+; LA64-NEXT:    bl %plt(defined_function)
 ; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-NEXT:    addi.d $sp, $sp, 16
 ; LA64-NEXT:    ret
   %1 = call i32 @defined_function(i32 %a) nounwind
   ret i32 %1
 }
 
 define i32 @test_call_indirect(ptr %a, i32 %b) nounwind {

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

; LA64-NEXT:    ret
   ret double %1
 }
 
 define double @convert_i64_to_double(i64 %a) nounwind {
 ; LA32-LABEL: convert_i64_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32-NEXT:    bl __floatdidf
+; LA32-NEXT:    bl %plt(__floatdidf)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_i64_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.d $fa0, $a0
 ; LA64-NEXT:    ffint.d.l $fa0, $fa0
; LA64-NEXT:    ret
   ret i32 %1
 }
 
 define i64 @convert_double_to_i64(double %a) nounwind {
 ; LA32-LABEL: convert_double_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32-NEXT:    bl __fixdfdi
+; LA32-NEXT:    bl %plt(__fixdfdi)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_double_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ftintrz.l.d $fa0, $fa0
 ; LA64-NEXT:    movfr2gr.d $a0, $fa0
 ; LA64-NEXT:    ret
   %1 = fptosi double %a to i64
   ret i64 %1
 }
 
 define i64 @convert_double_to_u64(double %a) nounwind {
 ; LA32-LABEL: convert_double_to_u64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32-NEXT:    bl __fixunsdfdi
+; LA32-NEXT:    bl %plt(__fixunsdfdi)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_double_to_u64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    pcalau12i $a0, .LCPI9_0
 ; LA64-NEXT:    addi.d $a0, $a0, .LCPI9_0
; LA64-NEXT:    ret
   ret double %1
 }
 
 define double @convert_u64_to_double(i64 %a) nounwind {
 ; LA32-LABEL: convert_u64_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32-NEXT:    bl __floatundidf
+; LA32-NEXT:    bl %plt(__floatundidf)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: convert_u64_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    srli.d $a1, $a0, 32
 ; LA64-NEXT:    lu52i.d $a2, $zero, 1107

llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll

; LA64D-NEXT:    ret
   ret i32 %1
 }
 
 define i64 @convert_float_to_i64(float %a) nounwind {
 ; LA32F-LABEL: convert_float_to_i64:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    addi.w $sp, $sp, -16
 ; LA32F-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32F-NEXT:    bl __fixsfdi
+; LA32F-NEXT:    bl %plt(__fixsfdi)
 ; LA32F-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32F-NEXT:    addi.w $sp, $sp, 16
 ; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_float_to_i64:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    addi.w $sp, $sp, -16
 ; LA32D-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32D-NEXT:    bl __fixsfdi
+; LA32D-NEXT:    bl %plt(__fixsfdi)
 ; LA32D-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_float_to_i64:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    ftintrz.w.s $fa0, $fa0
 ; LA64F-NEXT:    movfr2gr.s $a0, $fa0
; LA64D-NEXT:    ret
   ret i32 %1
 }
 
 define i64 @convert_float_to_u64(float %a) nounwind {
 ; LA32F-LABEL: convert_float_to_u64:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    addi.w $sp, $sp, -16
 ; LA32F-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32F-NEXT:    bl __fixunssfdi
+; LA32F-NEXT:    bl %plt(__fixunssfdi)
 ; LA32F-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32F-NEXT:    addi.w $sp, $sp, 16
 ; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_float_to_u64:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    addi.w $sp, $sp, -16
 ; LA32D-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32D-NEXT:    bl __fixunssfdi
+; LA32D-NEXT:    bl %plt(__fixunssfdi)
 ; LA32D-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_float_to_u64:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    pcalau12i $a0, .LCPI7_0
 ; LA64F-NEXT:    addi.d $a0, $a0, .LCPI7_0
; LA64D-NEXT:    ret
   ret float %1
 }
 
 define float @convert_i64_to_float(i64 %a) nounwind {
 ; LA32F-LABEL: convert_i64_to_float:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    addi.w $sp, $sp, -16
 ; LA32F-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32F-NEXT:    bl __floatdisf
+; LA32F-NEXT:    bl %plt(__floatdisf)
 ; LA32F-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32F-NEXT:    addi.w $sp, $sp, 16
 ; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_i64_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    addi.w $sp, $sp, -16
 ; LA32D-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32D-NEXT:    bl __floatdisf
+; LA32D-NEXT:    bl %plt(__floatdisf)
 ; LA32D-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_i64_to_float:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    movgr2fr.w $fa0, $a0
 ; LA64F-NEXT:    ffint.s.w $fa0, $fa0
; LA64D-NEXT:    ret
   ret float %1
 }
 
 define float @convert_u64_to_float(i64 %a) nounwind {
 ; LA32F-LABEL: convert_u64_to_float:
 ; LA32F:       # %bb.0:
 ; LA32F-NEXT:    addi.w $sp, $sp, -16
 ; LA32F-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32F-NEXT:    bl __floatundisf
+; LA32F-NEXT:    bl %plt(__floatundisf)
 ; LA32F-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32F-NEXT:    addi.w $sp, $sp, 16
 ; LA32F-NEXT:    ret
 ;
 ; LA32D-LABEL: convert_u64_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    addi.w $sp, $sp, -16
 ; LA32D-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
-; LA32D-NEXT:    bl __floatundisf
+; LA32D-NEXT:    bl %plt(__floatundisf)
 ; LA32D-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32D-NEXT:    addi.w $sp, $sp, 16
 ; LA32D-NEXT:    ret
 ;
 ; LA64F-LABEL: convert_u64_to_float:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    srli.d $a1, $a0, 1
 ; LA64F-NEXT:    andi $a2, $a0, 1

llvm/test/CodeGen/LoongArch/ir-instruction/load-store-atomic.ll

 define i64 @load_acquire_i64(ptr %ptr) {
 ; LA32-LABEL: load_acquire_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
 ; LA32-NEXT:    ori $a1, $zero, 2
-; LA32-NEXT:    bl __atomic_load_8
+; LA32-NEXT:    bl %plt(__atomic_load_8)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: load_acquire_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.d $a0, $a0, 0
 ; LA64-NEXT:    dbar 0

 define void @store_release_i64(ptr %ptr, i64 %v) {
 ; LA32-LABEL: store_release_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
 ; LA32-NEXT:    ori $a3, $zero, 3
-; LA32-NEXT:    bl __atomic_store_8
+; LA32-NEXT:    bl %plt(__atomic_store_8)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: store_release_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    dbar 0
 ; LA64-NEXT:    st.d $a0, $a1, 0
 ; LA64-NEXT:    ret
   store atomic i64 %v, ptr %ptr release, align 8
   ret void
 }

llvm/test/CodeGen/LoongArch/ir-instruction/load-store.ll

 ; RUN: llc --mtriple=loongarch32 --mattr=+d --relocation-model=static < %s | FileCheck %s --check-prefixes=ALL,LA32NOPIC,LA32
 ; RUN: llc --mtriple=loongarch32 --mattr=+d --relocation-model=pic < %s | FileCheck %s --check-prefixes=ALL,LA32PIC,LA32
 ; RUN: llc --mtriple=loongarch64 --mattr=+d --relocation-model=static < %s | FileCheck %s --check-prefixes=ALL,LA64NOPIC,LA64
 ; RUN: llc --mtriple=loongarch64 --mattr=+d --relocation-model=pic < %s | FileCheck %s --check-prefixes=ALL,LA64PIC,LA64
 
 ;; Check load from and store to global variables.
 @G = dso_local global i32 zeroinitializer, align 4
 @arr = dso_local global [10 x i32] zeroinitializer, align 4
 
 define i32 @load_store_global() nounwind {
 ; ALL-LABEL:      load_store_global:
 ; ALL:            # %bb.0:
 
-; LA32NOPIC-NEXT:   pcalau12i $a0, G
-; LA32NOPIC-NEXT:   addi.w $a1, $a0, G
-; LA32PIC-NEXT:     pcalau12i $a0, .LG$local
-; LA32PIC-NEXT:     addi.w $a1, $a0, .LG$local
+; LA32NOPIC-NEXT:   pcalau12i $a0, %pc_hi20(G)
+; LA32NOPIC-NEXT:   addi.w $a1, $a0, %pc_lo12(G)
+; LA32PIC-NEXT:     pcalau12i $a0, %pc_hi20(.LG$local)
+; LA32PIC-NEXT:     addi.w $a1, $a0, %pc_lo12(.LG$local)
 ; LA32-NEXT:        ld.w $a0, $a1, 0
 ; LA32-NEXT:        addi.w $a0, $a0, 1
 ; LA32-NEXT:        st.w $a0, $a1, 0
 
-; LA64NOPIC-NEXT:   pcalau12i $a0, G
-; LA64NOPIC-NEXT:   addi.d $a1, $a0, G
-; LA64PIC-NEXT:     pcalau12i $a0, .LG$local
-; LA64PIC-NEXT:     addi.d $a1, $a0, .LG$local
+; LA64NOPIC-NEXT:   pcalau12i $a0, %pc_hi20(G)
+; LA64NOPIC-NEXT:   addi.d $a1, $a0, %pc_lo12(G)
+; LA64PIC-NEXT:     pcalau12i $a0, %pc_hi20(.LG$local)
+; LA64PIC-NEXT:     addi.d $a1, $a0, %pc_lo12(.LG$local)
 ; LA64-NEXT:        ld.w $a0, $a1, 0
 ; LA64-NEXT:        addi.d $a0, $a0, 1
 ; LA64-NEXT:        st.w $a0, $a1, 0
 
 ; ALL-NEXT:         ret
 
   %v = load i32, ptr @G
   %sum = add i32 %v, 1
   store i32 %sum, ptr @G
   ret i32 %sum
 }
 
 define i32 @load_store_global_array(i32 %a) nounwind {
 ; ALL-LABEL: load_store_global_array:
 ; ALL:       # %bb.0:
 
-; LA32NOPIC-NEXT:   pcalau12i $a1, arr
-; LA32NOPIC-NEXT:   addi.w $a2, $a1, arr
-; LA32PIC-NEXT:     pcalau12i $a1, .Larr$local
-; LA32PIC-NEXT:     addi.w $a2, $a1, .Larr$local
+; LA32NOPIC-NEXT:   pcalau12i $a1, %pc_hi20(arr)
+; LA32NOPIC-NEXT:   addi.w $a2, $a1, %pc_lo12(arr)
+; LA32PIC-NEXT:     pcalau12i $a1, %pc_hi20(.Larr$local)
+; LA32PIC-NEXT:     addi.w $a2, $a1, %pc_lo12(.Larr$local)
 ; LA32-NEXT:        ld.w $a1, $a2, 0
 ; LA32-NEXT:        st.w $a0, $a2, 0
 ; LA32NOPIC-NEXT:   ld.w $a3, $a2, 36
 ; LA32NOPIC-NEXT:   st.w $a0, $a2, 36
 ; LA32PIC-NEXT:     ld.w $a3, $a2, 36
 ; LA32PIC-NEXT:     st.w $a0, $a2, 36
 
-; LA64NOPIC-NEXT:   pcalau12i $a1, arr
-; LA64NOPIC-NEXT:   addi.d $a2, $a1, arr
-; LA64PIC-NEXT:     pcalau12i $a1, .Larr$local
-; LA64PIC-NEXT:     addi.d $a2, $a1, .Larr$local
+; LA64NOPIC-NEXT:   pcalau12i $a1, %pc_hi20(arr)
+; LA64NOPIC-NEXT:   addi.d $a2, $a1, %pc_lo12(arr)
+; LA64PIC-NEXT:     pcalau12i $a1, %pc_hi20(.Larr$local)
+; LA64PIC-NEXT:     addi.d $a2, $a1, %pc_lo12(.Larr$local)
 ; LA64-NEXT:        ld.w $a1, $a2, 0
 ; LA64-NEXT:        st.w $a0, $a2, 0
 ; LA64NOPIC-NEXT:   ld.w $a3, $a2, 36
 ; LA64NOPIC-NEXT:   st.w $a0, $a2, 36
 ; LA64PIC-NEXT:     ld.w $a3, $a2, 36
 ; LA64PIC-NEXT:     st.w $a0, $a2, 36
 
 ; ALL-NEXT:         move $a0, $a1

llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll

 
 define i64 @sdiv_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: sdiv_i64:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
-; LA32-NEXT:    bl __divdi3
+; LA32-NEXT:    bl %plt(__divdi3)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: sdiv_i64:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    div.d $a0, $a0, $a1
 ; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: sdiv_i64:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, -16
 ; LA32-TRAP-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-TRAP-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-TRAP-NEXT:    .cfi_offset 1, -4
-; LA32-TRAP-NEXT:    bl __divdi3
+; LA32-TRAP-NEXT:    bl %plt(__divdi3)
 ; LA32-TRAP-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, 16
 ; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: sdiv_i64:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    div.d $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB4_2

 
 define i64 @udiv_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: udiv_i64:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
-; LA32-NEXT:    bl __udivdi3
+; LA32-NEXT:    bl %plt(__udivdi3)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: udiv_i64:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    div.du $a0, $a0, $a1
 ; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: udiv_i64:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, -16
 ; LA32-TRAP-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-TRAP-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-TRAP-NEXT:    .cfi_offset 1, -4
-; LA32-TRAP-NEXT:    bl __udivdi3
+; LA32-TRAP-NEXT:    bl %plt(__udivdi3)
 ; LA32-TRAP-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, 16
 ; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: udiv_i64:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    div.du $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB9_2

 
 define i64 @srem_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: srem_i64:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
-; LA32-NEXT:    bl __moddi3
+; LA32-NEXT:    bl %plt(__moddi3)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: srem_i64:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    mod.d $a0, $a0, $a1
 ; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: srem_i64:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, -16
 ; LA32-TRAP-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-TRAP-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-TRAP-NEXT:    .cfi_offset 1, -4
-; LA32-TRAP-NEXT:    bl __moddi3
+; LA32-TRAP-NEXT:    bl %plt(__moddi3)
 ; LA32-TRAP-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, 16
 ; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: srem_i64:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    mod.d $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB14_2

 
 define i64 @urem_i64(i64 %a, i64 %b) {
 ; LA32-LABEL: urem_i64:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-NEXT:    .cfi_offset 1, -4
-; LA32-NEXT:    bl __umoddi3
+; LA32-NEXT:    bl %plt(__umoddi3)
 ; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: urem_i64:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    mod.du $a0, $a0, $a1
 ; LA64-NEXT:    ret
 ;
 ; LA32-TRAP-LABEL: urem_i64:
 ; LA32-TRAP:       # %bb.0: # %entry
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, -16
 ; LA32-TRAP-NEXT:    .cfi_def_cfa_offset 16
 ; LA32-TRAP-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
 ; LA32-TRAP-NEXT:    .cfi_offset 1, -4
-; LA32-TRAP-NEXT:    bl __umoddi3
+; LA32-TRAP-NEXT:    bl %plt(__umoddi3)
 ; LA32-TRAP-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
 ; LA32-TRAP-NEXT:    addi.w $sp, $sp, 16
 ; LA32-TRAP-NEXT:    ret
 ;
 ; LA64-TRAP-LABEL: urem_i64:
 ; LA64-TRAP:       # %bb.0: # %entry
 ; LA64-TRAP-NEXT:    mod.du $a0, $a0, $a1
 ; LA64-TRAP-NEXT:    bnez $a1, .LBB19_2
 ; LA64-TRAP-NEXT:  # %bb.1: # %entry
 ; LA64-TRAP-NEXT:    break 7
 ; LA64-TRAP-NEXT:  .LBB19_2: # %entry
 ; LA64-TRAP-NEXT:    ret
 entry:
   %r = urem i64 %a, %b
   ret i64 %r
 }

llvm/test/CodeGen/LoongArch/vararg.ll

 ; LA64-FPELIM-NEXT:    addi.d $a0, $fp, 16
 ; LA64-FPELIM-NEXT:    st.d $a0, $fp, -32
 ; LA64-FPELIM-NEXT:    addi.d $a0, $a1, 15
 ; LA64-FPELIM-NEXT:    addi.w $a1, $zero, -16
 ; LA64-FPELIM-NEXT:    and $a0, $a0, $a1
 ; LA64-FPELIM-NEXT:    st.d $s0, $fp, 8
 ; LA64-FPELIM-NEXT:    sub.d $a0, $sp, $a0
 ; LA64-FPELIM-NEXT:    move $sp, $a0
-; LA64-FPELIM-NEXT:    bl notdead
+; LA64-FPELIM-NEXT:    bl %plt(notdead)
 ; LA64-FPELIM-NEXT:    move $a0, $s0
 ; LA64-FPELIM-NEXT:    addi.d $sp, $fp, -32
 ; LA64-FPELIM-NEXT:    ld.d $s0, $sp, 8 # 8-byte Folded Reload
 ; LA64-FPELIM-NEXT:    ld.d $fp, $sp, 16 # 8-byte Folded Reload
 ; LA64-FPELIM-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
 ; LA64-FPELIM-NEXT:    addi.d $sp, $sp, 96
 ; LA64-FPELIM-NEXT:    ret
 ;

 ; LA64-WITHFP-NEXT:    addi.d $a0, $fp, 16
 ; LA64-WITHFP-NEXT:    st.d $a0, $fp, -32
 ; LA64-WITHFP-NEXT:    addi.d $a0, $a1, 15
 ; LA64-WITHFP-NEXT:    addi.w $a1, $zero, -16
 ; LA64-WITHFP-NEXT:    and $a0, $a0, $a1
 ; LA64-WITHFP-NEXT:    st.d $s0, $fp, 8
 ; LA64-WITHFP-NEXT:    sub.d $a0, $sp, $a0
 ; LA64-WITHFP-NEXT:    move $sp, $a0
-; LA64-WITHFP-NEXT:    bl notdead
+; LA64-WITHFP-NEXT:    bl %plt(notdead)
 ; LA64-WITHFP-NEXT:    move $a0, $s0
 ; LA64-WITHFP-NEXT:    addi.d $sp, $fp, -32
 ; LA64-WITHFP-NEXT:    ld.d $s0, $sp, 8 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    ld.d $fp, $sp, 16 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, 96
 ; LA64-WITHFP-NEXT:    ret
   %va = alloca ptr, align 8
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, i64
   %2 = alloca i8, i64 %1
   call void @notdead(ptr %2)
   call void @llvm.va_end(ptr %va)
   ret i64 %1
 }
 
 define void @va1_caller() nounwind {
 ; LA64-FPELIM-LABEL: va1_caller:
 ; LA64-FPELIM:       # %bb.0:
 ; LA64-FPELIM-NEXT:    addi.d $sp, $sp, -16
 ; LA64-FPELIM-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-FPELIM-NEXT:    lu52i.d $a1, $zero, 1023
 ; LA64-FPELIM-NEXT:    ori $a2, $zero, 2
-; LA64-FPELIM-NEXT:    bl va1
+; LA64-FPELIM-NEXT:    bl %plt(va1)
 ; LA64-FPELIM-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-FPELIM-NEXT:    addi.d $sp, $sp, 16
 ; LA64-FPELIM-NEXT:    ret
 ;
 ; LA64-WITHFP-LABEL: va1_caller:
 ; LA64-WITHFP:       # %bb.0:
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, -16
 ; LA64-WITHFP-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    st.d $fp, $sp, 0 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    addi.d $fp, $sp, 16
 ; LA64-WITHFP-NEXT:    lu52i.d $a1, $zero, 1023
 ; LA64-WITHFP-NEXT:    ori $a2, $zero, 2
-; LA64-WITHFP-NEXT:    bl va1
+; LA64-WITHFP-NEXT:    bl %plt(va1)
 ; LA64-WITHFP-NEXT:    ld.d $fp, $sp, 0 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, 16
 ; LA64-WITHFP-NEXT:    ret
   %1 = call i64 (ptr, ...) @va1(ptr undef, double 1.0, i64 2)
   ret void
 }
 

 ; LA64-FPELIM-NEXT:    lu52i.d $a4, $a0, -328
 ; LA64-FPELIM-NEXT:    lu12i.w $a0, -503317
 ; LA64-FPELIM-NEXT:    ori $a0, $a0, 2129
 ; LA64-FPELIM-NEXT:    lu32i.d $a0, 37355
 ; LA64-FPELIM-NEXT:    lu52i.d $a5, $a0, 1024
 ; LA64-FPELIM-NEXT:    ori $a0, $zero, 2
 ; LA64-FPELIM-NEXT:    ori $a1, $zero, 1111
 ; LA64-FPELIM-NEXT:    move $a2, $zero
-; LA64-FPELIM-NEXT:    bl va_aligned_register
+; LA64-FPELIM-NEXT:    bl %plt(va_aligned_register)
 ; LA64-FPELIM-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-FPELIM-NEXT:    addi.d $sp, $sp, 16
 ; LA64-FPELIM-NEXT:    ret
 ;
 ; LA64-WITHFP-LABEL: va_aligned_register_caller:
 ; LA64-WITHFP:       # %bb.0:
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, -16
 ; LA64-WITHFP-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    st.d $fp, $sp, 0 # 8-byte Folded Spill
 ; LA64-WITHFP-NEXT:    addi.d $fp, $sp, 16
 ; LA64-WITHFP-NEXT:    lu12i.w $a0, 335544
 ; LA64-WITHFP-NEXT:    ori $a0, $a0, 1311
 ; LA64-WITHFP-NEXT:    lu32i.d $a0, 335544
 ; LA64-WITHFP-NEXT:    lu52i.d $a4, $a0, -328
 ; LA64-WITHFP-NEXT:    lu12i.w $a0, -503317
 ; LA64-WITHFP-NEXT:    ori $a0, $a0, 2129
 ; LA64-WITHFP-NEXT:    lu32i.d $a0, 37355
 ; LA64-WITHFP-NEXT:    lu52i.d $a5, $a0, 1024
 ; LA64-WITHFP-NEXT:    ori $a0, $zero, 2
 ; LA64-WITHFP-NEXT:    ori $a1, $zero, 1111
 ; LA64-WITHFP-NEXT:    move $a2, $zero
-; LA64-WITHFP-NEXT:    bl va_aligned_register
+; LA64-WITHFP-NEXT:    bl %plt(va_aligned_register)
 ; LA64-WITHFP-NEXT:    ld.d $fp, $sp, 0 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, 16
 ; LA64-WITHFP-NEXT:    ret
  %1 = call i64 (i64, i128, ...) @va_aligned_register(i64 2, i128 1111,
    fp128 0xLEB851EB851EB851F400091EB851EB851)
  ret void
 }

 ; LA64-FPELIM-NEXT:    st.d $zero, $sp, 72
 ; LA64-FPELIM-NEXT:    ori $a1, $zero, 11
 ; LA64-FPELIM-NEXT:    addi.d $a2, $sp, 64
 ; LA64-FPELIM-NEXT:    ori $a3, $zero, 12
 ; LA64-FPELIM-NEXT:    ori $a4, $zero, 13
 ; LA64-FPELIM-NEXT:    ori $a0, $zero, 1
 ; LA64-FPELIM-NEXT:    move $a6, $zero
 ; LA64-FPELIM-NEXT:    move $a7, $a0
-; LA64-FPELIM-NEXT:    bl va_aligned_stack_callee
+; LA64-FPELIM-NEXT:    bl %plt(va_aligned_stack_callee)
 ; LA64-FPELIM-NEXT:    ld.d $ra, $sp, 104 # 8-byte Folded Reload
 ; LA64-FPELIM-NEXT:    addi.d $sp, $sp, 112
 ; LA64-FPELIM-NEXT:    ret
 ;
 ; LA64-WITHFP-LABEL: va_aligned_stack_caller:
 ; LA64-WITHFP:       # %bb.0:
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, -112
 ; LA64-WITHFP-NEXT:    st.d $ra, $sp, 104 # 8-byte Folded Spill

 ; LA64-WITHFP-NEXT:    st.d $zero, $fp, -40
 ; LA64-WITHFP-NEXT:    ori $a1, $zero, 11
 ; LA64-WITHFP-NEXT:    addi.d $a2, $fp, -48
 ; LA64-WITHFP-NEXT:    ori $a3, $zero, 12
 ; LA64-WITHFP-NEXT:    ori $a4, $zero, 13
 ; LA64-WITHFP-NEXT:    ori $a0, $zero, 1
 ; LA64-WITHFP-NEXT:    move $a6, $zero
 ; LA64-WITHFP-NEXT:    move $a7, $a0
-; LA64-WITHFP-NEXT:    bl va_aligned_stack_callee
+; LA64-WITHFP-NEXT:    bl %plt(va_aligned_stack_callee)
 ; LA64-WITHFP-NEXT:    ld.d $fp, $sp, 96 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    ld.d $ra, $sp, 104 # 8-byte Folded Reload
 ; LA64-WITHFP-NEXT:    addi.d $sp, $sp, 112
 ; LA64-WITHFP-NEXT:    ret
   %1 = call i32 (i32, ...) @va_aligned_stack_callee(i32 1, i32 11,
     i256 1000, i32 12, i32 13, i128 18446744073709551616, i32 14,
     fp128 0xLEB851EB851EB851F400091EB851EB851, i64 15,
     [2 x i64] [i64 16, i64 17])
   ret void
 }

llvm/test/MC/LoongArch/Basic/Integer/invalid.s

 # CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [0, 4095]
 ori $a0, $a0, 4096
 # CHECK: :[[#@LINE-1]]:15: error: immediate must be an integer in the range [0, 4095]
 xori $a0, $a0, 4096
 # CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [0, 4095]
 
 ## simm12
 addi.w $a0, $a0, -2049
-# CHECK: :[[#@LINE-1]]:18: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:18: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 slti $a0, $a0, -2049
-# CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:16: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 sltui $a0, $a0, 2048
-# CHECK: :[[#@LINE-1]]:17: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:17: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 preld 0, $a0, 2048
-# CHECK: :[[#@LINE-1]]:15: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:15: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 ld.b $a0, $a0, 2048
-# CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:16: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 ld.h $a0, $a0, 2048
-# CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:16: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 ld.w $a0, $a0, 2048
-# CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:16: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 ld.bu $a0, $a0, -2049
-# CHECK: :[[#@LINE-1]]:17: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:17: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 ld.hu $a0, $a0, -2049
-# CHECK: :[[#@LINE-1]]:17: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:17: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 st.b $a0, $a0, 2048
-# CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:16: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 st.h $a0, $a0, 2048
-# CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:16: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 st.w $a0, $a0, -2049
-# CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:16: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 
 ## simm14_lsl2
 ll.w $a0, $a0, -32772
 # CHECK: :[[#@LINE-1]]:16: error: immediate must be a multiple of 4 in the range [-32768, 32764]
 ll.w $a0, $a0, -32769
 # CHECK: :[[#@LINE-1]]:16: error: immediate must be a multiple of 4 in the range [-32768, 32764]
 sc.w $a0, $a0, 32767
 # CHECK: :[[#@LINE-1]]:16: error: immediate must be a multiple of 4 in the range [-32768, 32764]

 
 ## simm20
 lu12i.w $a0, -0x80001
 # CHECK: :[[#@LINE-1]]:14: error: immediate must be an integer in the range [-524288, 524287]
 pcaddi $a0, -0x80001
 # CHECK: :[[#@LINE-1]]:13: error: immediate must be an integer in the range [-524288, 524287]
 pcaddu12i $a0, 0x80000
 # CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [-524288, 524287]
+
+## simm20_pcalau12i
 pcalau12i $a0, 0x80000
-# CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [-524288, 524287]
+# CHECK: :[[#@LINE-1]]:16: error: operand must be a symbol with modifier (e.g. %pc_hi20) or an integer in the range [-524288, 524287]
 
 ## simm21_lsl2
 beqz $a0, -0x400001
 # CHECK: :[[#@LINE-1]]:11: error: immediate must be a multiple of 4 in the range [-4194304, 4194300]
 bnez $a0, -0x3FFFFF
 # CHECK: :[[#@LINE-1]]:11: error: immediate must be a multiple of 4 in the range [-4194304, 4194300]
 beqz $a0, 0x3FFFFF
 # CHECK: :[[#@LINE-1]]:11: error: immediate must be a multiple of 4 in the range [-4194304, 4194300]
 bnez $a0, 0x400000
 # CHECK: :[[#@LINE-1]]:11: error: immediate must be a multiple of 4 in the range [-4194304, 4194300]
 
 ## simm26_lsl2
 b -0x8000001
-# CHECK: :[[#@LINE-1]]:3: error: immediate must be a multiple of 4 in the range [-134217728, 134217724]
+# CHECK: :[[#@LINE-1]]:3: error: operand must be a bare symbol name or an immediate must be a multiple of 4 in the range [-134217728, 134217724]
 b 0x1
-# CHECK: :[[#@LINE-1]]:3: error: immediate must be a multiple of 4 in the range [-134217728, 134217724]
+# CHECK: :[[#@LINE-1]]:3: error: operand must be a bare symbol name or an immediate must be a multiple of 4 in the range [-134217728, 134217724]
 bl 0x7FFFFFF
-# CHECK: :[[#@LINE-1]]:4: error: immediate must be a multiple of 4 in the range [-134217728, 134217724]
+# CHECK: :[[#@LINE-1]]:4: error: operand must be a bare symbol name or an immediate must be a multiple of 4 in the range [-134217728, 134217724]
 bl 0x8000000
-# CHECK: :[[#@LINE-1]]:4: error: immediate must be a multiple of 4 in the range [-134217728, 134217724]
+# CHECK: :[[#@LINE-1]]:4: error: operand must be a bare symbol name or an immediate must be a multiple of 4 in the range [-134217728, 134217724]
 
 ## Invalid mnemonics
 nori $a0, $a0, 0
 # CHECK: :[[#@LINE-1]]:1: error: unrecognized instruction mnemonic
 andni $a0, $a0, 0
 # CHECK: :[[#@LINE-1]]:1: error: unrecognized instruction mnemonic
 orni $a0, $a0, 0
 # CHECK: :[[#@LINE-1]]:1: error: unrecognized instruction mnemonic

llvm/test/MC/LoongArch/Basic/Integer/invalid64.s

 # CHECK: :[[#@LINE-1]]:19: error: immediate must be an integer in the range [0, 63]
 bstrins.d $a0, $a0, 63, -1
 # CHECK: :[[#@LINE-1]]:25: error: immediate must be an integer in the range [0, 63]
 bstrpick.d $a0, $a0, 64, 0
 # CHECK: :[[#@LINE-1]]:22: error: immediate must be an integer in the range [0, 63]
 
 ## simm12
 addi.d $a0, $a0, -2049
-# CHECK: :[[#@LINE-1]]:18: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:18: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 lu52i.d $a0, $a0, -2049
-# CHECK: :[[#@LINE-1]]:19: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:19: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 ld.wu $a0, $a0, 2048
-# CHECK: :[[#@LINE-1]]:17: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:17: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 ld.d $a0, $a0, 2048
-# CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:16: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 st.d $a0, $a0, 2048
-# CHECK: :[[#@LINE-1]]:16: error: immediate must be an integer in the range [-2048, 2047]
+# CHECK: :[[#@LINE-1]]:16: error: operand must be a symbol with modifier (e.g. %pc_lo12) or an integer in the range [-2048, 2047]
 
 ## simm14_lsl2
 ldptr.w $a0, $a0, -32772
 # CHECK: :[[#@LINE-1]]:19: error: immediate must be a multiple of 4 in the range [-32768, 32764]
 ldptr.d $a0, $a0, -32772
 # CHECK: :[[#@LINE-1]]:19: error: immediate must be a multiple of 4 in the range [-32768, 32764]
 stptr.w $a0, $a0, -32769
 # CHECK: :[[#@LINE-1]]:19: error: immediate must be a multiple of 4 in the range [-32768, 32764]

llvm/test/MC/LoongArch/Relocations/relocations.s

+# RUN: llvm-mc --triple=loongarch64 < %s --show-encoding \
+# RUN:     | FileCheck --check-prefixes=INSTR,FIXUP %s
+# RUN: llvm-mc --filetype=obj --triple=loongarch64 < %s \
+# RUN:     | llvm-readobj -r - | FileCheck --check-prefix=RELOC %s
+
+## Check prefixes:
+## RELOC - Check the relocation in the object.
+## FIXUP - Check the fixup on the instruction.
+## INSTR - Check the instruction is handled properly by the ASMPrinter.
+
+.long foo
+# RELOC: R_LARCH_32 foo
+
+.quad foo
+# RELOC: R_LARCH_64 foo
+
+pcalau12i $t1, %pc_hi20(foo)
+# RELOC: R_LARCH_PCALA_HI20 foo 0x0
+# INSTR: pcalau12i $t1, %pc_hi20(foo)
+# FIXUP: fixup A - offset: 0, value: %pc_hi20(foo), kind: fixup_loongarch_pcala_hi20
+
+pcalau12i $t1, %pc_hi20(foo+4)
+# RELOC: R_LARCH_PCALA_HI20 foo 0x4
+# INSTR: pcalau12i $t1, %pc_hi20(foo+4)
+# FIXUP: fixup A - offset: 0, value: %pc_hi20(foo+4), kind: fixup_loongarch_pcala_hi20
+
+addi.d $t1, $t1, %pc_lo12(foo)
+# RELOC: R_LARCH_PCALA_LO12 foo 0x0
+# INSTR: addi.d  $t1, $t1, %pc_lo12(foo)
+# FIXUP: fixup A - offset: 0, value: %pc_lo12(foo), kind: fixup_loongarch_pcala_lo12
+
+addi.d $t1, $t1, %pc_lo12(foo+4)
+# RELOC: R_LARCH_PCALA_LO12 foo 0x4
+# INSTR: addi.d  $t1, $t1, %pc_lo12(foo+4)
+# FIXUP: fixup A - offset: 0, value: %pc_lo12(foo+4), kind: fixup_loongarch_pcala_lo12
+
+st.b $t1, $a2, %pc_lo12(foo)
+# RELOC: R_LARCH_PCALA_LO12 foo 0x0
+# INSTR: st.b  $t1, $a2, %pc_lo12(foo)
+# FIXUP: fixup A - offset: 0, value: %pc_lo12(foo), kind: fixup_loongarch_pcala_lo12
+
+st.b $t1, $a2, %pc_lo12(foo+4)
+# RELOC: R_LARCH_PCALA_LO12 foo 0x4
+# INSTR: st.b  $t1, $a2, %pc_lo12(foo+4)
+# FIXUP: fixup A - offset: 0, value: %pc_lo12(foo+4), kind: fixup_loongarch_pcala_lo12
+
+bl %plt(foo)
+# RELOC: R_LARCH_B26
+# INSTR: bl  %plt(foo)
+# FIXUP: fixup A - offset: 0, value: %plt(foo), kind: fixup_loongarch_b26
+
+bl foo
+# RELOC: R_LARCH_B26
+# INSTR: bl  foo
+# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_loongarch_b26

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_generated_funcs.ll.generated.expected

 ; CHECK-NEXT:    addi.w $sp, $sp, -32
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    st.w $ra, $sp, 28 # 4-byte Folded Spill
 ; CHECK-NEXT:    st.w $fp, $sp, 24 # 4-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset 1, -4
 ; CHECK-NEXT:    .cfi_offset 22, -8
 ; CHECK-NEXT:    addi.w $fp, $sp, 32
 ; CHECK-NEXT:    .cfi_def_cfa 22, 0
-; CHECK-NEXT:    pcalau12i $a0, x
-; CHECK-NEXT:    addi.w $a0, $a0, x
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(x)
+; CHECK-NEXT:    addi.w $a0, $a0, %pc_lo12(x)
 ; CHECK-NEXT:    ori $a1, $zero, 1
 ; CHECK-NEXT:    st.w $a1, $a0, 0
 ; CHECK-NEXT:    st.w $zero, $fp, -12
 ; CHECK-NEXT:    st.w $a1, $fp, -16
 ; CHECK-NEXT:    ori $a0, $zero, 2
 ; CHECK-NEXT:    st.w $a0, $fp, -20
 ; CHECK-NEXT:    ori $a2, $zero, 3
 ; CHECK-NEXT:    st.w $a2, $fp, -24

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/loongarch_generated_funcs.ll.nogenerated.expected

 ; CHECK-NEXT:    addi.w $sp, $sp, -32
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    st.w $ra, $sp, 28 # 4-byte Folded Spill
 ; CHECK-NEXT:    st.w $fp, $sp, 24 # 4-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset 1, -4
 ; CHECK-NEXT:    .cfi_offset 22, -8
 ; CHECK-NEXT:    addi.w $fp, $sp, 32
 ; CHECK-NEXT:    .cfi_def_cfa 22, 0
-; CHECK-NEXT:    pcalau12i $a0, x
-; CHECK-NEXT:    addi.w $a0, $a0, x
+; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(x)
+; CHECK-NEXT:    addi.w $a0, $a0, %pc_lo12(x)
 ; CHECK-NEXT:    ori $a1, $zero, 1
 ; CHECK-NEXT:    st.w $a1, $a0, 0
 ; CHECK-NEXT:    st.w $zero, $fp, -12
 ; CHECK-NEXT:    st.w $a1, $fp, -16
 ; CHECK-NEXT:    ori $a0, $zero, 2
 ; CHECK-NEXT:    st.w $a0, $fp, -20
 ; CHECK-NEXT:    ori $a2, $zero, 3
 ; CHECK-NEXT:    st.w $a2, $fp, -24