Combine cmp with zero and all versions of AND, ORR, EOR and BIC instructions into S-suffixed versions.
Related issue: https://github.com/llvm/llvm-project/issues/57122
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[ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr ClosedPublic Authored by fzhinkin on Aug 12 2022, 9:10 AM.
Details Summary Combine cmp with zero and all versions of AND, ORR, EOR and BIC instructions into S-suffixed versions. Related issue: https://github.com/llvm/llvm-project/issues/57122
Diff Detail
Event TimelineComment Actions Built stage2 binaries and executed clang and llvm tests, all passed: build.log.bz2538 KBDownload This comment was removed by fzhinkin. Comment Actions Sounds like a good patch. Are all the cases covered by the tests? It looks like they are, but it's a bit hard to tell from the current file.
Comment Actions Looks pretty good to me, but maybe give the other reviewers some time for another look. This revision is now accepted and ready to land.Sep 20 2022, 6:11 AM Comment Actions
Thank you! Closed by commit rG945a1468c922: [ARM] Support all versions of AND, ORR, EOR and BIC in optimizeCompareInstr (authored by fzhinkin). · Explain WhyOct 1 2022, 2:41 AM This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 464484 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/test/CodeGen/ARM/branch-on-zero.ll
llvm/test/CodeGen/ARM/cmp-peephole.ll
llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
llvm/test/CodeGen/ARM/icmp-shift-opt.ll
llvm/test/CodeGen/ARM/sadd_sat.ll
llvm/test/CodeGen/ARM/sadd_sat_plus.ll
llvm/test/CodeGen/ARM/sat-to-bitop.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
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Didn't support shifts as it seems very unlikely to see these instructions here.