[LLDB][RISCV] Add riscv software breakpoint trap code

[Emmmer]

Summary

Added:

• Take RISC-V ebreak instruction as breakpoint trap code, so our breakpoint works as expected now.

Further work:

• RISC-V does not support hardware single stepping yet. A software implementation may come in future PR.
• Add support for RVC extension (the trap code, etc.).

[DavidSpickett]

LGTM thanks again for splitting it up.

When you say riscv doesn't support hardware single stepping do you mean lldb on riscv? In https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf B.5 Single Step I see it described at least for bare metal debug, I don't know if that's available via ptrace yet. Just curious, not a blocker of any sort.

[Emmmer]

In D131566#3713046, @DavidSpickett wrote:

LGTM thanks again for splitting it up.

When you say riscv doesn't support hardware single stepping do you mean lldb on riscv? In https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf B.5 Single Step I see it described at least for bare metal debug, I don't know if that's available via ptrace yet. Just curious, not a blocker of any sort.

I look through the riscv's Linux kernel code, and it's a pity that the kernel does not support PTRACE_SINGLESTEP, which is used by lldb-server as hardware breakpoint implementation.

The riscv-debug-spec is still a draft, so it is not implemented by qemu (my only available platform)

lldb/source/Host/common/NativeProcessProtocol.cpp

 NativeProcessProtocol::GetSoftwareBreakpointTrapOpcode(size_t size_hint) {
   static const uint8_t g_aarch64_opcode[] = {0x00, 0x00, 0x20, 0xd4};
   static const uint8_t g_i386_opcode[] = {0xCC};
   static const uint8_t g_mips64_opcode[] = {0x00, 0x00, 0x00, 0x0d};
   static const uint8_t g_mips64el_opcode[] = {0x0d, 0x00, 0x00, 0x00};
   static const uint8_t g_s390x_opcode[] = {0x00, 0x01};
   static const uint8_t g_ppc_opcode[] = {0x7f, 0xe0, 0x00, 0x08}; // trap
   static const uint8_t g_ppcle_opcode[] = {0x08, 0x00, 0xe0, 0x7f}; // trap
+  static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
 
   switch (GetArchitecture().GetMachine()) {
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_32:
     return llvm::makeArrayRef(g_aarch64_opcode);
 
   case llvm::Triple::x86:
   case llvm::Triple::x86_64:
NativeProcessProtocol::GetSoftwareBreakpointTrapOpcode(size_t size_hint) {
 
   case llvm::Triple::ppc:
   case llvm::Triple::ppc64:
     return llvm::makeArrayRef(g_ppc_opcode);
 
   case llvm::Triple::ppc64le:
     return llvm::makeArrayRef(g_ppcle_opcode);
 
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64:
+    return llvm::makeArrayRef(g_riscv_opcode);
+
   default:
     return llvm::createStringError(llvm::inconvertibleErrorCode(),
                                    "CPU type not supported!");
   }
 }
 
 size_t NativeProcessProtocol::GetSoftwareBreakpointPCOffset() {
   switch (GetArchitecture().GetMachine()) {
   case llvm::Triple::x86:
   case llvm::Triple::x86_64:
   case llvm::Triple::systemz:
     // These architectures report increment the PC after breakpoint is hit.
     return cantFail(GetSoftwareBreakpointTrapOpcode(0)).size();
 
   case llvm::Triple::arm:
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_32:
   case llvm::Triple::mips64:
   case llvm::Triple::mips64el:
   case llvm::Triple::mips:
   case llvm::Triple::mipsel:
   case llvm::Triple::ppc:
   case llvm::Triple::ppc64:
   case llvm::Triple::ppc64le:
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64:
     // On these architectures the PC doesn't get updated for breakpoint hits.
     return 0;
 
   default:
     llvm_unreachable("CPU type not supported!");
   }
 }
 

lldb/source/Target/Platform.cpp

size_t Platform::GetSoftwareBreakpointTrapOpcode(Target &target,
 
   case llvm::Triple::x86:
   case llvm::Triple::x86_64: {
     static const uint8_t g_i386_opcode[] = {0xCC};
     trap_opcode = g_i386_opcode;
     trap_opcode_size = sizeof(g_i386_opcode);
   } break;
 
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64: {
+    static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
+    trap_opcode = g_riscv_opcode;
+    trap_opcode_size = sizeof(g_riscv_opcode);
+  } break;
+
   default:
     return 0;
   }
 
   assert(bp_site);
   if (bp_site->SetTrapOpcode(trap_opcode, trap_opcode_size))
     return trap_opcode_size;