[BranchRelaxation] Remove param BrOffset from TargetInstrInfo::insertIndirectBranch() [NFC]

[piggynl]

Summary

Parameter BrOffset in TargetInstrInfo::insertIndirectBranch() is initially added in rG6bc43d8627ca44465e7ce261a0828b70d3460e13 to tell whether the inserted branch is a forward branch or a backward branch. The conditional has been removed in D106445 and BrOffset is not used in any target now. This patch removes the parameter.

Because the offset between the branch instruction and the branch target could be changed in another iteration in BranchRelaxation::relaxBranchInstructions(), the MachineOperand for the branch target should be an MBB instead of a fixed number, thus there shouldn't be any usage of BrOffset, so I believe removing the parameter is safe. Also, I'm trying to write a patch to deduplicate restore blocks in BranchRelaxation::fixupUnconditionalBranch(). Removing this parameter would avoid some unnecessary offset calculations.

llvm/include/llvm/CodeGen/TargetInstrInfo.h

public:
 
   /// Insert an unconditional indirect branch at the end of \p MBB to \p
   /// NewDestBB. Optionally, insert the clobbered register restoring in \p
   /// RestoreBB. \p BrOffset indicates the offset of \p NewDestBB relative to
   /// the offset of the position to insert the new branch.
   virtual void insertIndirectBranch(MachineBasicBlock &MBB,
                                     MachineBasicBlock &NewDestBB,
                                     MachineBasicBlock &RestoreBB,
-                                    const DebugLoc &DL, int64_t BrOffset = 0,
+                                    const DebugLoc &DL,
                                     RegScavenger *RS = nullptr) const {
     llvm_unreachable("target did not implement");
   }
 
   /// Analyze the branching code at the end of MBB, returning
   /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
   /// implemented for a target).  Upon success, this returns false and returns
   /// with the following information in various cases:

llvm/lib/CodeGen/BranchRelaxation.cpp

bool BranchRelaxation::fixupUnconditionalBranch(MachineInstr &MI) {
   DebugLoc DL = MI.getDebugLoc();
   MI.eraseFromParent();
 
   // Create the optional restore block and, initially, place it at the end of
   // function. That block will be placed later if it's used; otherwise, it will
   // be erased.
   MachineBasicBlock *RestoreBB = createNewBlockAfter(MF->back());
 
-  TII->insertIndirectBranch(*BranchBB, *DestBB, *RestoreBB, DL,
-                            DestOffset - SrcOffset, RS.get());
+  TII->insertIndirectBranch(*BranchBB, *DestBB, *RestoreBB, DL, RS.get());
 
   BlockInfo[BranchBB->getNumber()].Size = computeBlockSize(*BranchBB);
   adjustBlockOffsets(*MBB);
 
   // If RestoreBB is required, try to place just before DestBB.
   if (!RestoreBB->empty()) {
     // TODO: For multiple far branches to the same destination, there are
     // chances that some restore blocks could be shared if they clobber the

llvm/lib/Target/AMDGPU/SIInstrInfo.h

public:
   bool isBranchOffsetInRange(unsigned BranchOpc,
                              int64_t BrOffset) const override;
 
   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
 
   void insertIndirectBranch(MachineBasicBlock &MBB,
                             MachineBasicBlock &NewDestBB,
                             MachineBasicBlock &RestoreBB, const DebugLoc &DL,
-                            int64_t BrOffset, RegScavenger *RS) const override;
+                            RegScavenger *RS) const override;
 
   bool analyzeBranchImpl(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator I,
                          MachineBasicBlock *&TBB,
                          MachineBasicBlock *&FBB,
                          SmallVectorImpl<MachineOperand> &Cond,
                          bool AllowModify) const;
 

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

MachineBasicBlock *SIInstrInfo::getBranchDestBlock(
   }
 
   return MI.getOperand(0).getMBB();
 }
 
 void SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
                                        MachineBasicBlock &DestBB,
                                        MachineBasicBlock &RestoreBB,
-                                       const DebugLoc &DL, int64_t BrOffset,
+                                       const DebugLoc &DL,
                                        RegScavenger *RS) const {
   assert(RS && "RegScavenger required for long branching");
   assert(MBB.empty() &&
          "new block should be inserted for expanding unconditional branch");
   assert(MBB.pred_size() == 1);
   assert(RestoreBB.empty() &&
          "restore block should be inserted for restoring clobbered registers");
 

llvm/lib/Target/AVR/AVRInstrInfo.h

public:
   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
 
   bool isBranchOffsetInRange(unsigned BranchOpc,
                              int64_t BrOffset) const override;
 
   void insertIndirectBranch(MachineBasicBlock &MBB,
                             MachineBasicBlock &NewDestBB,
                             MachineBasicBlock &RestoreBB, const DebugLoc &DL,
-                            int64_t BrOffset, RegScavenger *RS) const override;
+                            RegScavenger *RS) const override;
 
 private:
   const AVRRegisterInfo RI;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_AVR_INSTR_INFO_H

llvm/lib/Target/AVR/AVRInstrInfo.cpp

bool AVRInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
   case AVR::BRLTk:
     return isIntN(7, BrOffset);
   }
 }
 
 void AVRInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
                                         MachineBasicBlock &NewDestBB,
                                         MachineBasicBlock &RestoreBB,
-                                        const DebugLoc &DL, int64_t BrOffset,
+                                        const DebugLoc &DL,
                                         RegScavenger *RS) const {
   // This method inserts a *direct* branch (JMP), despite its name.
   // LLVM calls this method to fixup unconditional branches; it never calls
   // insertBranch or some hypothetical "insertDirectBranch".
   // See lib/CodeGen/RegisterRelaxation.cpp for details.
   // We end up here when a jump is too long for a RJMP instruction.
   BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
 }
 
 } // end of namespace llvm

llvm/lib/Target/RISCV/RISCVInstrInfo.h

public:
   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
                         const DebugLoc &dl,
                         int *BytesAdded = nullptr) const override;
 
   void insertIndirectBranch(MachineBasicBlock &MBB,
                             MachineBasicBlock &NewDestBB,
                             MachineBasicBlock &RestoreBB, const DebugLoc &DL,
-                            int64_t BrOffset, RegScavenger *RS) const override;
+                            RegScavenger *RS) const override;
 
   unsigned removeBranch(MachineBasicBlock &MBB,
                         int *BytesRemoved = nullptr) const override;
 
   bool
   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

unsigned RISCVInstrInfo::insertBranch(
   if (BytesAdded)
     *BytesAdded += getInstSizeInBytes(MI);
   return 2;
 }
 
 void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
                                           MachineBasicBlock &DestBB,
                                           MachineBasicBlock &RestoreBB,
-                                          const DebugLoc &DL, int64_t BrOffset,
+                                          const DebugLoc &DL,
                                           RegScavenger *RS) const {
   assert(RS && "RegScavenger required for long branching");
   assert(MBB.empty() &&
          "new block should be inserted for expanding unconditional branch");
   assert(MBB.pred_size() == 1);
 
   MachineFunction *MF = MBB.getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();