[MIPS] Expose the ZERO register as a constant physical register

[Carrot]

Summary

The ZERO register should be exposed as a constant physical register through the interface TargetRegisterInfo::isConstantPhysReg.

[MaskRay]

It seems not so easy to construct a test. I've tried

declare i64 @llvm.read_register.i64(metadata)
 
define i64 @get_gp() {
  %1 = call i64 @llvm.read_register.i64(metadata !0)
  %2 = call i64 @llvm.read_register.i64(metadata !0)
  %sub = sub i64 %1, %2
  ret i64 %sub
}
 
!0 = !{!"$28"}

which doesn't have benefit in another target which has implemented isConstantPhysReg.

[arsenm]

In D130932#3691969, @MaskRay wrote:

It seems not so easy to construct a test. I've tried

declare i64 @llvm.read_register.i64(metadata)
 
define i64 @get_gp() {
  %1 = call i64 @llvm.read_register.i64(metadata !0)
  %2 = call i64 @llvm.read_register.i64(metadata !0)
  %sub = sub i64 %1, %2
  ret i64 %sub
}
 
!0 = !{!"$28"}

which doesn't have benefit in another target which has implemented isConstantPhysReg.

Probably should try for a mir test

[Carrot]

In D130932#3691969, @MaskRay wrote:

It seems not so easy to construct a test. I've tried

declare i64 @llvm.read_register.i64(metadata)
 
define i64 @get_gp() {
  %1 = call i64 @llvm.read_register.i64(metadata !0)
  %2 = call i64 @llvm.read_register.i64(metadata !0)
  %sub = sub i64 %1, %2
  ret i64 %sub
}
 
!0 = !{!"$28"}

which doesn't have benefit in another target which has implemented isConstantPhysReg.

Because TargetRegisterInfo::isConstantPhysReg is rarely used directly. People usually call MachineRegisterInfo::isConstantPhysReg which calls TargetRegisterInfo::isConstantPhysReg again. Even TargetRegisterInfo::isConstantPhysReg returns false for Mips::ZERO_64, MachineRegisterInfo::isConstantPhysReg still checks if there is any definition of Mips::ZERO_64, and returns true if there is no def for it. So it's difficult to write a test for it.

I encountered a test case benefited from this patch when I worked on https://reviews.llvm.org/D130919.

llvm/lib/Target/Mips/MipsRegisterInfo.h

void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            RegScavenger *RS = nullptr) const override;
 
   // Stack realignment queries.
   bool canRealignStack(const MachineFunction &MF) const override;
 
   /// Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;
 
+  bool isConstantPhysReg(MCRegister PhysReg) const override;
+
   /// Return GPR register class.
   virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
 
 private:
   virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
                            int FrameIndex, uint64_t StackSize,
                            int64_t SPOffset) const = 0;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H

llvm/lib/Target/Mips/MipsRegisterInfo.cpp

bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
   // don't have variable sized objects.
   if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
     return true;
 
   // We have to reserve the base pointer register in the presence of variable
   // sized objects.
   return MF.getRegInfo().canReserveReg(BP);
 }
+
+bool MipsRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
+  return PhysReg == Mips::ZERO_64 || PhysReg == Mips::ZERO;
+}