[LoongArch] Offset folding for frameindex

[wangleiat]

Summary

This patch is for frameindex calculations.

[MaskRay]

Do you know why csky/hexagon need isOrEquivalentToAdd while other targets can produce efficient code without isOrEquivalentToAdd ?

[barannikov88]

In D130248#3674127, @MaskRay wrote:

Do you know why csky/hexagon need isOrEquivalentToAdd while other targets can produce efficient code without isOrEquivalentToAdd ?

Other targets just do that manually in *ISelDAGToDAG.cpp file. E.g. X86:

case ISD::OR:
  // We want to look through a transform in InstCombine and DAGCombiner that
  // turns 'add' into 'or', so we can treat this 'or' exactly like an 'add'.
  // Example: (or (and x, 1), (shl y, 3)) --> (add (and x, 1), (shl y, 3))
  // An 'lea' can then be used to match the shift (multiply) and add:
  // and $1, %esi
  // lea (%rsi, %rdi, 8), %rax
  if (CurDAG->haveNoCommonBitsSet(N.getOperand(0), N.getOperand(1)) &&
      !matchAdd(N, AM, Depth))
    return false;
  break;

ARM:

// Determine whether an ISD::OR's operands are suitable to turn the operation
// into an addition, which often has more compact encodings.
bool ARMDAGToDAGISel::SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out) {
  assert(Parent->getOpcode() == ISD::OR && "unexpected parent");
  Out = N;
  return CurDAG->haveNoCommonBitsSet(N, Parent->getOperand(1));
}

[barannikov88]

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

591

You can check for both ADD and OR in one PatFrags, e.g.:

def add_like : PatFrags<(ops node:$lhs, node:$rhs),
                        [(add $lhs, $rhs), (or $lhs, $rhs)], [{
  return N->getOpcode() == ISD::ADD || isOrEquivalentToAdd(N);
}]>;

This will halve the number of patterns. Up to you, of course.

[wangleiat]

In D130248#3674149, @barannikov88 wrote:

In D130248#3674127, @MaskRay wrote:

Do you know why csky/hexagon need isOrEquivalentToAdd while other targets can produce efficient code without isOrEquivalentToAdd ?

Other targets just do that manually in *ISelDAGToDAG.cpp file. E.g. X86:

case ISD::OR:
  // We want to look through a transform in InstCombine and DAGCombiner that
  // turns 'add' into 'or', so we can treat this 'or' exactly like an 'add'.
  // Example: (or (and x, 1), (shl y, 3)) --> (add (and x, 1), (shl y, 3))
  // An 'lea' can then be used to match the shift (multiply) and add:
  // and $1, %esi
  // lea (%rsi, %rdi, 8), %rax
  if (CurDAG->haveNoCommonBitsSet(N.getOperand(0), N.getOperand(1)) &&
      !matchAdd(N, AM, Depth))
    return false;
  break;

ARM:

// Determine whether an ISD::OR's operands are suitable to turn the operation
// into an addition, which often has more compact encodings.
bool ARMDAGToDAGISel::SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out) {
  assert(Parent->getOpcode() == ISD::OR && "unexpected parent");
  Out = N;
  return CurDAG->haveNoCommonBitsSet(N, Parent->getOperand(1));
}

Agree, The DAGCombiner will almost certainly be generated ISD::OR operator for frameindex. (natural alignment attribute?)

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

591

You can check for both ADD and OR in one PatFrags, e.g.:

def add_like : PatFrags<(ops node:$lhs, node:$rhs),
                        [(add $lhs, $rhs), (or $lhs, $rhs)], [{
  return N->getOpcode() == ISD::ADD || isOrEquivalentToAdd(N);
}]>;

This will halve the number of patterns. Up to you, of course.

Thanks, I will do that.

[wangleiat]

Address @barannikov88's comment.

[barannikov88]

Looks good to me, although I'm not familiar with the architecture.

[SixWeining]

LGTM.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 
 class PatGprImm<SDPatternOperator OpNode, LAInst Inst, Operand ImmOpnd>
     : Pat<(OpNode GPR:$rj, ImmOpnd:$imm),
           (Inst GPR:$rj, ImmOpnd:$imm)>;
 class PatGprImm_32<SDPatternOperator OpNode, LAInst Inst, Operand ImmOpnd>
     : Pat<(sext_inreg (OpNode GPR:$rj, ImmOpnd:$imm), i32),
           (Inst GPR:$rj, ImmOpnd:$imm)>;
 
+/// Predicates
+def AddLike: PatFrags<(ops node:$A, node:$B),
+                      [(add node:$A, node:$B), (or node:$A, node:$B)], [{
+    return N->getOpcode() == ISD::ADD || isOrEquivalentToAdd(N);
+}]>;
+
 /// Simple arithmetic operations
 
 // Match both a plain shift and one where the shift amount is masked (this is
 // typically introduced when the legalizer promotes the shift amount and
 // zero-extends it). For LoongArch, the mask is unnecessary as shifts in the
 // base ISA only read the least significant 5 bits (LA32) or 6 bits (LA64).
 def shiftMaskGRLen
     : ComplexPattern<GRLenVT, 1, "selectShiftMaskGRLen", [], [], 0>;

 
 def : PatGprGpr<and, AND>;
 def : PatGprImm<and, ANDI, uimm12>;
 def : PatGprGpr<or, OR>;
 def : PatGprImm<or, ORI, uimm12>;
 def : PatGprGpr<xor, XOR>;
 def : PatGprImm<xor, XORI, uimm12>;
 
+/// FrameIndex calculations
+let Predicates = [IsLA32] in {
+def : Pat<(AddLike (i32 BaseAddr:$rj), simm12:$imm12),
+          (ADDI_W (i32 BaseAddr:$rj), simm12:$imm12)>;
+} // Predicates = [IsLA32]
+let Predicates = [IsLA64] in {
+def : Pat<(AddLike (i64 BaseAddr:$rj), simm12:$imm12),
+          (ADDI_D (i64 BaseAddr:$rj), simm12:$imm12)>;
+} // Predicates = [IsLA64]
+
 /// Shift
 
 let Predicates = [IsLA32] in {
 def : PatGprGpr<shiftop<shl>, SLL_W>;
 def : PatGprGpr<shiftop<sra>, SRA_W>;
 def : PatGprGpr<shiftop<srl>, SRL_W>;
 def : PatGprImm<shl, SLLI_W, uimm5>;
 def : PatGprImm<sra, SRAI_W, uimm5>;

 def : Pat<(loongarch_bstrpick GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
           (BSTRPICK_D GPR:$rj, uimm6:$msbd, uimm6:$lsbd)>;
 } // Predicates = [IsLA64]
 
 /// Loads
 
 multiclass LdPat<PatFrag LoadOp, LAInst Inst, ValueType vt = GRLenVT> {
   def : Pat<(vt (LoadOp BaseAddr:$rj)), (Inst BaseAddr:$rj, 0)>;
-  def : Pat<(vt (LoadOp (add BaseAddr:$rj, simm12:$imm12))),
+  def : Pat<(vt (LoadOp (AddLike BaseAddr:$rj, simm12:$imm12))),
             (Inst BaseAddr:$rj, simm12:$imm12)>;
 }
 
 defm : LdPat<sextloadi8, LD_B>;
 defm : LdPat<extloadi8, LD_B>;
 defm : LdPat<sextloadi16, LD_H>;
 defm : LdPat<extloadi16, LD_H>;
 defm : LdPat<load, LD_W>, Requires<[IsLA32]>;
 defm : LdPat<zextloadi8, LD_BU>;
 defm : LdPat<zextloadi16, LD_HU>;
 let Predicates = [IsLA64] in {
 defm : LdPat<sextloadi32, LD_W, i64>;
 defm : LdPat<extloadi32, LD_W, i64>;
 defm : LdPat<zextloadi32, LD_WU, i64>;
 defm : LdPat<load, LD_D, i64>;
 } // Predicates = [IsLA64]
 
 /// Stores
 
 multiclass StPat<PatFrag StoreOp, LAInst Inst, RegisterClass StTy,
                  ValueType vt> {
   def : Pat<(StoreOp (vt StTy:$rd), BaseAddr:$rj),
             (Inst StTy:$rd, BaseAddr:$rj, 0)>;
-  def : Pat<(StoreOp (vt StTy:$rd), (add BaseAddr:$rj, simm12:$imm12)),
+  def : Pat<(StoreOp (vt StTy:$rd), (AddLike BaseAddr:$rj, simm12:$imm12)),
             (Inst StTy:$rd, BaseAddr:$rj, simm12:$imm12)>;
 }
 
 defm : StPat<truncstorei8, ST_B, GPR, GRLenVT>;
 defm : StPat<truncstorei16, ST_H, GPR, GRLenVT>;
 defm : StPat<store, ST_W, GPR, i32>, Requires<[IsLA32]>;
 let Predicates = [IsLA64] in {
 defm : StPat<truncstorei32, ST_W, GPR, i64>;

llvm/test/CodeGen/LoongArch/frame.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 %struct.key_t = type { i32, [16 x i8] }
 
 define i32 @test() nounwind {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi.d $sp, $sp, -32
 ; CHECK-NEXT:    st.d $ra, $sp, 24 # 8-byte Folded Spill
 ; CHECK-NEXT:    st.w $zero, $sp, 16
 ; CHECK-NEXT:    st.d $zero, $sp, 8
 ; CHECK-NEXT:    st.d $zero, $sp, 0
-; CHECK-NEXT:    addi.d $a0, $sp, 0
-; CHECK-NEXT:    ori $a0, $a0, 4
+; CHECK-NEXT:    addi.d $a0, $sp, 4
 ; CHECK-NEXT:    bl test1
 ; CHECK-NEXT:    move $a0, $zero
 ; CHECK-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
 ; CHECK-NEXT:    addi.d $sp, $sp, 32
 ; CHECK-NEXT:    jirl $zero, $ra, 0
   %key = alloca %struct.key_t, align 4
   call void @llvm.memset.p0i8.i64(ptr %key, i8 0, i64 20, i1 false)
   %1 = getelementptr inbounds %struct.key_t, ptr %key, i64 0, i32 1, i64 0
   call void @test1(ptr %1)
   ret i32 0
 }
 
 declare void @llvm.memset.p0i8.i64(ptr, i8, i64, i1)
 
 declare void @test1(ptr)

llvm/test/CodeGen/LoongArch/ir-instruction/double-convert.ll

; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = uitofp i16 %a to double
   ret double %1
 }
 
 define double @convert_u32_to_double(i32 %a) nounwind {
 ; LA32-LABEL: convert_u32_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
-; LA32-NEXT:    addi.w $a1, $sp, 8
-; LA32-NEXT:    ori $a1, $a1, 4
-; LA32-NEXT:    lu12i.w $a2, 275200
-; LA32-NEXT:    st.w $a2, $a1, 0
+; LA32-NEXT:    lu12i.w $a1, 275200
+; LA32-NEXT:    st.w $a1, $sp, 12
 ; LA32-NEXT:    st.w $a0, $sp, 8
 ; LA32-NEXT:    pcalau12i $a0, .LCPI12_0
 ; LA32-NEXT:    addi.w $a0, $a0, .LCPI12_0
 ; LA32-NEXT:    fld.d $fa0, $a0, 0
 ; LA32-NEXT:    fld.d $fa1, $sp, 8
 ; LA32-NEXT:    fsub.d $fa0, $fa1, $fa0
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    jirl $zero, $ra, 0
; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = uitofp i64 %a to double
   ret double %1
 }
 
 define double @bitcast_i64_to_double(i64 %a, i64 %b) nounwind {
 ; LA32-LABEL: bitcast_i64_to_double:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
-; LA32-NEXT:    addi.w $a2, $sp, 8
-; LA32-NEXT:    ori $a2, $a2, 4
-; LA32-NEXT:    st.w $a1, $a2, 0
+; LA32-NEXT:    st.w $a1, $sp, 12
 ; LA32-NEXT:    st.w $a0, $sp, 8
 ; LA32-NEXT:    fld.d $fa0, $sp, 8
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: bitcast_i64_to_double:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.d $fa0, $a0
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = bitcast i64 %a to double
   ret double %1
 }
 
 define i64 @bitcast_double_to_i64(double %a) nounwind {
 ; LA32-LABEL: bitcast_double_to_i64:
 ; LA32:       # %bb.0:
 ; LA32-NEXT:    addi.w $sp, $sp, -16
 ; LA32-NEXT:    fst.d $fa0, $sp, 8
-; LA32-NEXT:    addi.w $a0, $sp, 8
-; LA32-NEXT:    ori $a0, $a0, 4
-; LA32-NEXT:    ld.w $a1, $a0, 0
 ; LA32-NEXT:    ld.w $a0, $sp, 8
+; LA32-NEXT:    ld.w $a1, $sp, 12
 ; LA32-NEXT:    addi.w $sp, $sp, 16
 ; LA32-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA64-LABEL: bitcast_double_to_i64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movfr2gr.d $a0, $fa0
 ; LA64-NEXT:    jirl $zero, $ra, 0
   %1 = bitcast double %a to i64
   ret i64 %1
 }

llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll

 ; LA32F-NEXT:    movgr2fr.w $fa1, $a0
 ; LA32F-NEXT:    ffint.s.w $fa1, $fa1
 ; LA32F-NEXT:    fsel $fa0, $fa1, $fa0, $fcc0
 ; LA32F-NEXT:    jirl $zero, $ra, 0
 ;
 ; LA32D-LABEL: convert_u32_to_float:
 ; LA32D:       # %bb.0:
 ; LA32D-NEXT:    addi.w $sp, $sp, -16
-; LA32D-NEXT:    addi.w $a1, $sp, 8
-; LA32D-NEXT:    ori $a1, $a1, 4
-; LA32D-NEXT:    lu12i.w $a2, 275200
-; LA32D-NEXT:    st.w $a2, $a1, 0
+; LA32D-NEXT:    lu12i.w $a1, 275200
+; LA32D-NEXT:    st.w $a1, $sp, 12
 ; LA32D-NEXT:    st.w $a0, $sp, 8
 ; LA32D-NEXT:    pcalau12i $a0, .LCPI14_0
 ; LA32D-NEXT:    addi.w $a0, $a0, .LCPI14_0
 ; LA32D-NEXT:    fld.d $fa0, $a0, 0
 ; LA32D-NEXT:    fld.d $fa1, $sp, 8
 ; LA32D-NEXT:    fsub.d $fa0, $fa1, $fa0
 ; LA32D-NEXT:    fcvt.s.d $fa0, $fa0
 ; LA32D-NEXT:    addi.w $sp, $sp, 16