[RISCV] Add isel pattern for (mul (and X, 0xffffffff), 3<<C) with Zba.

[craig.topper]

Summary

We can use slli.uw by C followed by sh1add. Similar can be done
for multiples of 5 and 9. We need to make sure that C is less than
32 to stay in bounds of the 5-bit immediate for slli.uw.

We have existing patterns for (mul X, 3<<C) that use sh1add
followed by slli. That order doesn't allow the and to be folded.

[craig.topper]

Ping

[craig.topper]

Rebase on pre-committed tests

[reames]

LGTM - I really want to say there's a more generic way to handle this, but after a bit of thought, I don't have any specific suggestions. Given that, land this and we can generalize later if needed.

[reames]

Went and glanced at surrounding code again, a couple of thoughts for follow up.

There's a whole bunch of mul by constant patterns. It'd be really nice to sink the shift before those for e.g. 11 << 2 and variants.

Not sure how to write this, but the general form of this would be something like:
if (is interesting constant after shifting and not before) {

emit shift
match shifted constant pattern

}

Not sure how worthwhile this is, just thinking about generality of code structure.

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

def C5LeftShift : PatLeaf<(imm), [{
   return C > 5 && ((C % 5) == 0) && isPowerOf2_64(C / 5);
 }]>;
 
 def C9LeftShift : PatLeaf<(imm), [{
   uint64_t C = N->getZExtValue();
   return C > 9 && ((C % 9) == 0) && isPowerOf2_64(C / 9);
 }]>;
 
+// Constant of the form (3 << C) where C is less than 32.
+def C3LeftShiftUW : PatLeaf<(imm), [{
+  uint64_t C = N->getZExtValue();
+  if (C <= 3 || (C % 3) != 0)
+    return false;
+  C /= 3;
+  return isPowerOf2_64(C) && C < (1ULL << 32);
+}]>;
+
+// Constant of the form (5 << C) where C is less than 32.
+def C5LeftShiftUW : PatLeaf<(imm), [{
+  uint64_t C = N->getZExtValue();
+  if (C <= 5 || (C % 5) != 0)
+    return false;
+  C /= 5;
+  return isPowerOf2_64(C) && C < (1ULL << 32);
+}]>;
+
+// Constant of the form (9 << C) where C is less than 32.
+def C9LeftShiftUW : PatLeaf<(imm), [{
+  uint64_t C = N->getZExtValue();
+  if (C <= 9 || (C % 9) != 0)
+    return false;
+  C /= 9;
+  return isPowerOf2_64(C) && C < (1ULL << 32);
+}]>;
+
 def CSImm12MulBy4 : PatLeaf<(imm), [{
   if (!N->hasOneUse())
     return false;
   int64_t C = N->getSExtValue();
   // Skip if C is simm12 or can be optimized by the PatLeaf AddiPair.
   return !isInt<13>(C) && isShiftedInt<12, 2>(C);
 }]>;
 

 
 // Use SRLI to clear the LSBs and SHXADD_UW to mask and shift.
 def : Pat<(i64 (add (and GPR:$rs1, 0x1FFFFFFFE), non_imm12:$rs2)),
           (SH1ADD_UW (SRLI GPR:$rs1, 1), GPR:$rs2)>;
 def : Pat<(i64 (add (and GPR:$rs1, 0x3FFFFFFFC), non_imm12:$rs2)),
           (SH2ADD_UW (SRLI GPR:$rs1, 2), GPR:$rs2)>;
 def : Pat<(i64 (add (and GPR:$rs1, 0x7FFFFFFF8), non_imm12:$rs2)),
           (SH3ADD_UW (SRLI GPR:$rs1, 3), GPR:$rs2)>;
+
+def : Pat<(mul (binop_oneuse<and> GPR:$r, 0xFFFFFFFF), C3LeftShiftUW:$i),
+          (SH1ADD (SLLI_UW GPR:$r, (TrailingZerosXForm C3LeftShiftUW:$i)),
+                  (SLLI_UW GPR:$r, (TrailingZerosXForm C3LeftShiftUW:$i)))>;
+def : Pat<(mul (binop_oneuse<and> GPR:$r, 0xFFFFFFFF), C5LeftShiftUW:$i),
+          (SH2ADD (SLLI_UW GPR:$r, (TrailingZerosXForm C5LeftShiftUW:$i)),
+                  (SLLI_UW GPR:$r, (TrailingZerosXForm C5LeftShiftUW:$i)))>;
+def : Pat<(mul (binop_oneuse<and> GPR:$r, 0xFFFFFFFF), C9LeftShiftUW:$i),
+          (SH3ADD (SLLI_UW GPR:$r, (TrailingZerosXForm C9LeftShiftUW:$i)),
+                  (SLLI_UW GPR:$r, (TrailingZerosXForm C9LeftShiftUW:$i)))>;
 } // Predicates = [HasStdExtZba, IsRV64]
 
 let Predicates = [HasStdExtZbcOrZbkc] in {
 def : PatGprGpr<int_riscv_clmul, CLMUL>;
 def : PatGprGpr<int_riscv_clmulh, CLMULH>;
 } // Predicates = [HasStdExtZbcOrZbkc]
 
 let Predicates = [HasStdExtZbc] in

llvm/test/CodeGen/RISCV/rv64zba.ll

 ; RV64I-NEXT:    li a1, 3
 ; RV64I-NEXT:    slli a1, a1, 37
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    mulhu a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_mul96:
 ; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    zext.w a0, a0
+; RV64ZBA-NEXT:    slli.uw a0, a0, 5
 ; RV64ZBA-NEXT:    sh1add a0, a0, a0
-; RV64ZBA-NEXT:    slli a0, a0, 5
 ; RV64ZBA-NEXT:    ret
   %b = zext i32 %a to i64
   %c = mul i64 %b, 96
   ret i64 %c
 }
 
 define i64 @zext_mul160(i32 signext %a) {
 ; RV64I-LABEL: zext_mul160:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, 5
 ; RV64I-NEXT:    slli a1, a1, 37
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    mulhu a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_mul160:
 ; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    zext.w a0, a0
+; RV64ZBA-NEXT:    slli.uw a0, a0, 5
 ; RV64ZBA-NEXT:    sh2add a0, a0, a0
-; RV64ZBA-NEXT:    slli a0, a0, 5
 ; RV64ZBA-NEXT:    ret
   %b = zext i32 %a to i64
   %c = mul i64 %b, 160
   ret i64 %c
 }
 
 define i64 @zext_mul288(i32 signext %a) {
 ; RV64I-LABEL: zext_mul288:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, 9
 ; RV64I-NEXT:    slli a1, a1, 37
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    mulhu a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_mul288:
 ; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    zext.w a0, a0
+; RV64ZBA-NEXT:    slli.uw a0, a0, 5
 ; RV64ZBA-NEXT:    sh3add a0, a0, a0
-; RV64ZBA-NEXT:    slli a0, a0, 5
 ; RV64ZBA-NEXT:    ret
   %b = zext i32 %a to i64
   %c = mul i64 %b, 288
   ret i64 %c
 }
 
 ; We can't use slli.uw becaues the shift amount is more than 31.
 ; FIXME: The zext.w is unneeded.