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Differential D129957

[RISCV] Add isel patterns for ineg+setge/le/uge/ule.
ClosedPublic

Authored by craig.topper on Jul 17 2022, 12:12 AM.

Details

Reviewers
reames
asb
luismarques
Commits
rG7c0b9b379b0e: [RISCV] Add isel patterns for ineg+setge/le/uge/ule.
Summary

setge/le/uge/ule selected by themselves require an xori with 1.
If we're negating the setcc, we can fold the xori with the neg
to create an addi with -1.

This works because xori X, 1 is equivalent to 1 - X if X is either
0 or 1. So we're doing -(1 - X) which is X-1 or X+-1.

This improves the code for selecting between 0 and -1 based on a
condition for some conditions.

Diff Detail

Event Timeline

craig.topper created this revision.Jul 17 2022, 12:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 17 2022, 12:12 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 28 others. · View Herald Transcript
craig.topper requested review of this revision.Jul 17 2022, 12:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 17 2022, 12:12 AM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B175876: Diff 445296.Jul 17 2022, 1:03 AM
asb added a comment.Jul 17 2022, 8:03 AM

This LGTM if an explanatory comment is added.

llvm/lib/Target/RISCV/RISCVInstrInfo.td
1280–1287

It would be good to add a comment here that expresses some of the same information used in the patch description, explaining why this pattern is valid.

llvm/test/CodeGen/RISCV/select-const.ll
870

Nit: Unwanted additional blank line

craig.topper updated this revision to Diff 445337.Jul 17 2022, 11:10 AM

Address review comments

Harbormaster completed remote builds in B175908: Diff 445337.Jul 17 2022, 11:58 AM
asb accepted this revision.Jul 18 2022, 2:47 AM

LGTM.

This revision is now accepted and ready to land.Jul 18 2022, 2:47 AM
This revision was landed with ongoing or failed builds.Jul 18 2022, 9:55 AM
Closed by commit rG7c0b9b379b0e: [RISCV] Add isel patterns for ineg+setge/le/uge/ule. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG7c0b9b379b0e: [RISCV] Add isel patterns for ineg+setge/le/uge/ule..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
7 lines
test/
CodeGen/
RISCV/
546 lines

Diff 445551

llvm/lib/Target/RISCV/RISCVInstrInfo.td

Show First 20 Lines • Show All 1,271 Lines • ▼ Show 20 Lines
def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>; def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;
def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>; def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>; def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>; def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
def : Pat<(setgt GPR:$rs1, simm12_minus1_nonzero:$imm), def : Pat<(setgt GPR:$rs1, simm12_minus1_nonzero:$imm),
(XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>; (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>;
def : Pat<(setugt GPR:$rs1, simm12_minus1_nonzero:$imm), def : Pat<(setugt GPR:$rs1, simm12_minus1_nonzero:$imm),
(XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>; (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>;
// If negating a pattern that requires an XORI above, we can fold the XORI with
// the NEG. The XORI is equivalent to 1-X and negating gives X-1.
def : Pat<(ineg (setuge GPR:$rs1, GPR:$rs2)), (ADDI (SLTU GPR:$rs1, GPR:$rs2), -1)>;
def : Pat<(ineg (setule GPR:$rs1, GPR:$rs2)), (ADDI (SLTU GPR:$rs2, GPR:$rs1), -1)>;
def : Pat<(ineg (setge GPR:$rs1, GPR:$rs2)), (ADDI (SLT GPR:$rs1, GPR:$rs2), -1)>;
def : Pat<(ineg (setle GPR:$rs1, GPR:$rs2)), (ADDI (SLT GPR:$rs2, GPR:$rs1), -1)>;
asbUnsubmitted
Not Done
ReplyInline Actions

It would be good to add a comment here that expresses some of the same information used in the patch description, explaining why this pattern is valid.

asb: It would be good to add a comment here that expresses some of the same information used in the…
def IntCCtoRISCVCC : SDNodeXForm<riscv_selectcc, [{ def IntCCtoRISCVCC : SDNodeXForm<riscv_selectcc, [{
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
RISCVCC::CondCode BrCC = getRISCVCCForIntCC(CC); RISCVCC::CondCode BrCC = getRISCVCCForIntCC(CC);
return CurDAG->getTargetConstant(BrCC, SDLoc(N), Subtarget->getXLenVT()); return CurDAG->getTargetConstant(BrCC, SDLoc(N), Subtarget->getXLenVT());
}]>; }]>;
def riscv_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc, def riscv_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc,
node:$truev, node:$falsev), node:$truev, node:$falsev),
▲ Show 20 Lines • Show All 393 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/select-const.ll

Show First 20 Lines • Show All 315 Lines • ▼ Show 20 Lines
; RV64IFDBT-NEXT: .LBB4_2: ; RV64IFDBT-NEXT: .LBB4_2:
; RV64IFDBT-NEXT: lui a0, %hi(.LCPI4_1) ; RV64IFDBT-NEXT: lui a0, %hi(.LCPI4_1)
; RV64IFDBT-NEXT: flw ft0, %lo(.LCPI4_1)(a0) ; RV64IFDBT-NEXT: flw ft0, %lo(.LCPI4_1)(a0)
; RV64IFDBT-NEXT: fmv.x.w a0, ft0 ; RV64IFDBT-NEXT: fmv.x.w a0, ft0
; RV64IFDBT-NEXT: ret ; RV64IFDBT-NEXT: ret
%1 = select i1 %a, float 3.0, float 4.0 %1 = select i1 %a, float 3.0, float 4.0
ret float %1 ret float %1
} }
define signext i32 @select_eq_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32I-LABEL: select_eq_zero_negone:
; RV32I: # %bb.0:
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_eq_zero_negone:
; RV32IF: # %bb.0:
; RV32IF-NEXT: xor a0, a0, a1
; RV32IF-NEXT: seqz a0, a0
; RV32IF-NEXT: neg a0, a0
; RV32IF-NEXT: ret
;
; RV32IBT-LABEL: select_eq_zero_negone:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: xor a0, a0, a1
; RV32IBT-NEXT: seqz a0, a0
; RV32IBT-NEXT: neg a0, a0
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_eq_zero_negone:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: xor a0, a0, a1
; RV32IFBT-NEXT: seqz a0, a0
; RV32IFBT-NEXT: neg a0, a0
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_eq_zero_negone:
; RV64I: # %bb.0:
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_eq_zero_negone:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: xor a0, a0, a1
; RV64IFD-NEXT: seqz a0, a0
; RV64IFD-NEXT: neg a0, a0
; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_eq_zero_negone:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: xor a0, a0, a1
; RV64IBT-NEXT: seqz a0, a0
; RV64IBT-NEXT: neg a0, a0
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_eq_zero_negone:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: xor a0, a0, a1
; RV64IFDBT-NEXT: seqz a0, a0
; RV64IFDBT-NEXT: neg a0, a0
; RV64IFDBT-NEXT: ret
%1 = icmp eq i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_ne_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32I-LABEL: select_ne_zero_negone:
; RV32I: # %bb.0:
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_ne_zero_negone:
; RV32IF: # %bb.0:
; RV32IF-NEXT: xor a0, a0, a1
; RV32IF-NEXT: snez a0, a0
; RV32IF-NEXT: neg a0, a0
; RV32IF-NEXT: ret
;
; RV32IBT-LABEL: select_ne_zero_negone:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: xor a0, a0, a1
; RV32IBT-NEXT: snez a0, a0
; RV32IBT-NEXT: neg a0, a0
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_ne_zero_negone:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: xor a0, a0, a1
; RV32IFBT-NEXT: snez a0, a0
; RV32IFBT-NEXT: neg a0, a0
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_ne_zero_negone:
; RV64I: # %bb.0:
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_ne_zero_negone:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: xor a0, a0, a1
; RV64IFD-NEXT: snez a0, a0
; RV64IFD-NEXT: neg a0, a0
; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_ne_zero_negone:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: xor a0, a0, a1
; RV64IBT-NEXT: snez a0, a0
; RV64IBT-NEXT: neg a0, a0
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_ne_zero_negone:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: xor a0, a0, a1
; RV64IFDBT-NEXT: snez a0, a0
; RV64IFDBT-NEXT: neg a0, a0
; RV64IFDBT-NEXT: ret
%1 = icmp ne i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_sgt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32I-LABEL: select_sgt_zero_negone:
; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a1, a0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_sgt_zero_negone:
; RV32IF: # %bb.0:
; RV32IF-NEXT: slt a0, a1, a0
; RV32IF-NEXT: neg a0, a0
; RV32IF-NEXT: ret
;
; RV32IBT-LABEL: select_sgt_zero_negone:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: slt a0, a1, a0
; RV32IBT-NEXT: neg a0, a0
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_sgt_zero_negone:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: slt a0, a1, a0
; RV32IFBT-NEXT: neg a0, a0
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_sgt_zero_negone:
; RV64I: # %bb.0:
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_sgt_zero_negone:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: slt a0, a1, a0
; RV64IFD-NEXT: neg a0, a0
; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_sgt_zero_negone:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: slt a0, a1, a0
; RV64IBT-NEXT: neg a0, a0
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_sgt_zero_negone:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: slt a0, a1, a0
; RV64IFDBT-NEXT: neg a0, a0
; RV64IFDBT-NEXT: ret
%1 = icmp sgt i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_slt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32I-LABEL: select_slt_zero_negone:
; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_slt_zero_negone:
; RV32IF: # %bb.0:
; RV32IF-NEXT: slt a0, a0, a1
; RV32IF-NEXT: neg a0, a0
; RV32IF-NEXT: ret
;
; RV32IBT-LABEL: select_slt_zero_negone:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: slt a0, a0, a1
; RV32IBT-NEXT: neg a0, a0
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_slt_zero_negone:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: slt a0, a0, a1
; RV32IFBT-NEXT: neg a0, a0
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_slt_zero_negone:
; RV64I: # %bb.0:
; RV64I-NEXT: slt a0, a0, a1
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_slt_zero_negone:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: slt a0, a0, a1
; RV64IFD-NEXT: neg a0, a0
; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_slt_zero_negone:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: slt a0, a0, a1
; RV64IBT-NEXT: neg a0, a0
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_slt_zero_negone:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: slt a0, a0, a1
; RV64IFDBT-NEXT: neg a0, a0
; RV64IFDBT-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_sge_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32I-LABEL: select_sge_zero_negone:
; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_sge_zero_negone:
; RV32IF: # %bb.0:
; RV32IF-NEXT: slt a0, a0, a1
; RV32IF-NEXT: addi a0, a0, -1
; RV32IF-NEXT: ret
;
; RV32IBT-LABEL: select_sge_zero_negone:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: slt a0, a0, a1
; RV32IBT-NEXT: addi a0, a0, -1
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_sge_zero_negone:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: slt a0, a0, a1
; RV32IFBT-NEXT: addi a0, a0, -1
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_sge_zero_negone:
; RV64I: # %bb.0:
; RV64I-NEXT: slt a0, a0, a1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_sge_zero_negone:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: slt a0, a0, a1
; RV64IFD-NEXT: addi a0, a0, -1
; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_sge_zero_negone:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: slt a0, a0, a1
; RV64IBT-NEXT: addi a0, a0, -1
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_sge_zero_negone:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: slt a0, a0, a1
; RV64IFDBT-NEXT: addi a0, a0, -1
; RV64IFDBT-NEXT: ret
%1 = icmp sge i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_sle_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32I-LABEL: select_sle_zero_negone:
; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a1, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_sle_zero_negone:
; RV32IF: # %bb.0:
; RV32IF-NEXT: slt a0, a1, a0
; RV32IF-NEXT: addi a0, a0, -1
; RV32IF-NEXT: ret
;
; RV32IBT-LABEL: select_sle_zero_negone:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: slt a0, a1, a0
; RV32IBT-NEXT: addi a0, a0, -1
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_sle_zero_negone:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: slt a0, a1, a0
; RV32IFBT-NEXT: addi a0, a0, -1
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_sle_zero_negone:
; RV64I: # %bb.0:
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_sle_zero_negone:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: slt a0, a1, a0
; RV64IFD-NEXT: addi a0, a0, -1
; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_sle_zero_negone:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: slt a0, a1, a0
; RV64IBT-NEXT: addi a0, a0, -1
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_sle_zero_negone:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: slt a0, a1, a0
; RV64IFDBT-NEXT: addi a0, a0, -1
; RV64IFDBT-NEXT: ret
%1 = icmp sle i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_ugt_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32I-LABEL: select_ugt_zero_negone:
; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_ugt_zero_negone:
; RV32IF: # %bb.0:
; RV32IF-NEXT: sltu a0, a1, a0
; RV32IF-NEXT: neg a0, a0
; RV32IF-NEXT: ret
;
; RV32IBT-LABEL: select_ugt_zero_negone:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: sltu a0, a1, a0
; RV32IBT-NEXT: neg a0, a0
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_ugt_zero_negone:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: sltu a0, a1, a0
; RV32IFBT-NEXT: neg a0, a0
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_ugt_zero_negone:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_ugt_zero_negone:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: sltu a0, a1, a0
; RV64IFD-NEXT: neg a0, a0
; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_ugt_zero_negone:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: sltu a0, a1, a0
; RV64IBT-NEXT: neg a0, a0
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_ugt_zero_negone:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: sltu a0, a1, a0
; RV64IFDBT-NEXT: neg a0, a0
; RV64IFDBT-NEXT: ret
%1 = icmp ugt i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_ult_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32I-LABEL: select_ult_zero_negone:
; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_ult_zero_negone:
; RV32IF: # %bb.0:
; RV32IF-NEXT: sltu a0, a0, a1
; RV32IF-NEXT: neg a0, a0
; RV32IF-NEXT: ret
;
; RV32IBT-LABEL: select_ult_zero_negone:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: sltu a0, a0, a1
; RV32IBT-NEXT: neg a0, a0
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_ult_zero_negone:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: sltu a0, a0, a1
; RV32IFBT-NEXT: neg a0, a0
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_ult_zero_negone:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: neg a0, a0
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_ult_zero_negone:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: sltu a0, a0, a1
; RV64IFD-NEXT: neg a0, a0
; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_ult_zero_negone:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: sltu a0, a0, a1
; RV64IBT-NEXT: neg a0, a0
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_ult_zero_negone:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: sltu a0, a0, a1
; RV64IFDBT-NEXT: neg a0, a0
; RV64IFDBT-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_uge_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32I-LABEL: select_uge_zero_negone:
; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_uge_zero_negone:
; RV32IF: # %bb.0:
; RV32IF-NEXT: sltu a0, a0, a1
; RV32IF-NEXT: addi a0, a0, -1
; RV32IF-NEXT: ret
;
; RV32IBT-LABEL: select_uge_zero_negone:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: sltu a0, a0, a1
; RV32IBT-NEXT: addi a0, a0, -1
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_uge_zero_negone:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: sltu a0, a0, a1
; RV32IFBT-NEXT: addi a0, a0, -1
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_uge_zero_negone:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_uge_zero_negone:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: sltu a0, a0, a1
; RV64IFD-NEXT: addi a0, a0, -1
; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_uge_zero_negone:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: sltu a0, a0, a1
; RV64IBT-NEXT: addi a0, a0, -1
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_uge_zero_negone:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: sltu a0, a0, a1
; RV64IFDBT-NEXT: addi a0, a0, -1
; RV64IFDBT-NEXT: ret
%1 = icmp uge i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
define signext i32 @select_ule_zero_negone(i32 signext %a, i32 signext %b) nounwind {
; RV32I-LABEL: select_ule_zero_negone:
; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_ule_zero_negone:
; RV32IF: # %bb.0:
; RV32IF-NEXT: sltu a0, a1, a0
; RV32IF-NEXT: addi a0, a0, -1
; RV32IF-NEXT: ret
;
; RV32IBT-LABEL: select_ule_zero_negone:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: sltu a0, a1, a0
; RV32IBT-NEXT: addi a0, a0, -1
; RV32IBT-NEXT: ret
;
; RV32IFBT-LABEL: select_ule_zero_negone:
; RV32IFBT: # %bb.0:
; RV32IFBT-NEXT: sltu a0, a1, a0
; RV32IFBT-NEXT: addi a0, a0, -1
; RV32IFBT-NEXT: ret
;
; RV64I-LABEL: select_ule_zero_negone:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_ule_zero_negone:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: sltu a0, a1, a0
; RV64IFD-NEXT: addi a0, a0, -1
; RV64IFD-NEXT: ret
;
; RV64IBT-LABEL: select_ule_zero_negone:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: sltu a0, a1, a0
; RV64IBT-NEXT: addi a0, a0, -1
; RV64IBT-NEXT: ret
;
; RV64IFDBT-LABEL: select_ule_zero_negone:
; RV64IFDBT: # %bb.0:
; RV64IFDBT-NEXT: sltu a0, a1, a0
; RV64IFDBT-NEXT: addi a0, a0, -1
; RV64IFDBT-NEXT: ret
%1 = icmp ule i32 %a, %b
%2 = select i1 %1, i32 -1, i32 0
ret i32 %2
}
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