[ARM] Correct features on pacbti tests. NFC

[dmgreen]

Summary

Given a patch like D129506, using instructions not valid for the current feature set becomes an error. This updates the Arm tests for pac/bti to use a thumbv8.1-m.main to make the instructions they produce valid. It requires altering some of the tests for the updated codegen.

[chill]

Is something breaking somewhere?
The compiler ought to generate valid PACBTI-M code for the v7-m architecture too, choosing only instructions from the NOP-space.

[dmgreen]

Oh I had that backwards then. The issue is that the instructions that it uses are all marked as requiring Armv8.1-m, so cannot be used validly in a Armv7-m build.

Should the instructions be available when assembling for thumbv7m? If so I can just change the predicates on the PACBTIHintSpaceInst instructions. If not they may need to use HINT's or use some pseudos.

[chill]

In D129692#3658852, @dmgreen wrote:

Oh I had that backwards then. The issue is that the instructions that it uses are all marked as requiring Armv8.1-m, so cannot be used validly in a Armv7-m build.

Should the instructions be available when assembling for thumbv7m? If so I can just change the predicates on the PACBTIHintSpaceInst instructions. If not they may need to use HINT's or use some pseudos.

Ideally, we would like mnemonics (for NOP-space instructions only) to be available in v-7m and up, even though they were introduced in v8.1-m.

[dmgreen]

Thanks - then this patch now sets the predicate on the Hint Space PACBTI instructions to thumbv7m. The test has been adjusted too, to show the instructions assembling/disassembling.

[chill]

LGTM, but let Victor take a look too.

[vhscampos]

It LGTM too. Thanks.

llvm/test/CodeGen/Thumb2/bti-const-island.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=thumbv7m-arm-none-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s
+# RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s
 
 # This test checks that the ARM Constant Island pass correctly handles BTI
 # instructions when adding new BBs to jump tables.
 #
 # Specifically the pass will replace bb.1.bb42.i in the jump table with a new
 # BB which will contain an unconditional branch to bb.1.bb42.i.
 # We expect that a BTI instruction will be added to the new BB and removed from
 # bb.1.bb42.i.

llvm/test/CodeGen/Thumb2/bti-entry-blocks.ll

-; RUN: llc < %s -mtriple=thumbv7m-arm-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv8.1m.main-arm-none-eabi | FileCheck %s
 
 define hidden i32 @linkage_external() local_unnamed_addr {
 ; CHECK-LABEL: linkage_external:
 ; CHECK: bti
 ; CHECK-NEXT: movs r0, #1
 ; CHECK-NEXT: bx lr
 entry:
   ret i32 1

llvm/test/CodeGen/Thumb2/bti-indirect-branches.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=thumbv7m-arm-none-eabi | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv8.1m.main-arm-none-eabi | FileCheck %s
 
 define internal i32 @table_switch(i32 %x) {
 ; CHECK-LABEL: table_switch:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    bti
 ; CHECK-NEXT:    subs r1, r0, #1
 ; CHECK-NEXT:    cmp r1, #3
 ; CHECK-NEXT:    bhi .LBB0_4

llvm/test/CodeGen/Thumb2/bti-jump-table.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc < %s -x mir -mtriple=thumbv7m-arm-none-eabi -run-pass=arm-branch-targets | FileCheck %s
+# RUN: llc < %s -x mir -mtriple=thumbv8.1m.main-arm-none-eabi -run-pass=arm-branch-targets | FileCheck %s
 --- |
   define internal i32 @table_switch(i32 %x) {
   entry:
     switch i32 %x, label %sw.epilog [
       i32 1, label %return
       i32 2, label %bb2
       i32 3, label %bb3
       i32 4, label %bb4

llvm/test/CodeGen/Thumb2/bti-outliner-1.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-eabi %s -o - | FileCheck %s
 
 ; Check that each outlining candidate and the outlined function are in agreement
 ; with regard to whether BTI insertion is enabled or not.
 
 ; volatile int a, b, c, d, e, f;
 ;
 ; int x(int p) {
 ;   int r = (a + b) / (c + d) * e + f;

llvm/test/CodeGen/Thumb2/bti-outliner-2.ll

-; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-eabi %s -o - | FileCheck %s
 
 ; See bti-outliner-1.ll
 ; Difference is the BTI placement is enabled by default for the entire module.
 
 @a = hidden global i32 0, align 4
 @b = hidden global i32 0, align 4
 @c = hidden global i32 0, align 4
 @d = hidden global i32 0, align 4

llvm/test/CodeGen/Thumb2/bti-outliner-cost-1.ll

-; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-eabi %s -o - | FileCheck %s
 
 ; Check an edge case of the outlining costs -
 ; outlining occurs in this test and does not in `bti-outliner-cost-2.ll`
 ; the only difference being the branch target enforcement is enabled in the
 ; latter one.
 
 ; volatile int a, b, c, d, e;
 ;

llvm/test/CodeGen/Thumb2/bti-outliner-cost-2.ll

-; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-eabi %s -o - | FileCheck %s
 
 ; See `bti-outliner-cost-1.ll`
 
 @a = hidden global i32 0, align 4
 @b = hidden global i32 0, align 4
 @c = hidden global i32 0, align 4
 @d = hidden global i32 0, align 4
 @e = hidden global i32 0, align 4

llvm/test/CodeGen/Thumb2/pacbti-m-basic.ll

 ; RUN: llc --force-dwarf-frame-section %s -o - | FileCheck %s
 ; RUN: llc --filetype=obj %s -o - | llvm-readelf -s --unwind - | FileCheck %s --check-prefix=UNWIND
 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
-target triple = "thumbv8m.main-none-none-eabi"
+target triple = "thumbv8.1m.main-none-none-eabi"
 
 ; int g(int);
 ;
 ; #if __ARM_FEATURE_CMSE == 3
 ; #define ENTRY __attribute__((cmse_nonsecure_entry))
 ; #else
 ; #define ENTRY
 ; #endif

 entry:
   %sub = add nsw i32 %x, -1
   %call = tail call i32 @g(i32 %sub)
   %add = add nsw i32 %call, 1
   ret i32 %add
 }
 ; CHECK-LABEL: f2:
 ; CHECK:       pac    r12, lr, sp
+; CHECK-NEXT:  vstr    fpcxtns, [sp, #-4]!
+; CHECK-NEXT:  .cfi_def_cfa_offset 4
 ; CHECK-NEXT:  .save  {r7, lr}
 ; CHECK-NEXT:  push   {r7, lr}
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: .cfi_offset lr, -4
-; CHECK-NEXT: .cfi_offset r7, -8
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: .cfi_offset lr, -8
+; CHECK-NEXT: .cfi_offset r7, -12
 ; CHECK-NEXT:  .save  {ra_auth_code}
 ; CHECK-NEXT:  str    r12, [sp, #-4]!
-; CHECK-NEXT: .cfi_def_cfa_offset 12
-; CHECK-NEXT: .cfi_offset ra_auth_code, -12
-; CHECK-NEXT:  .pad   #4
-; CHECK-NEXT:  sub    sp, #4
-; CHECK-NEXT:  .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset ra_auth_code, -16
 ; ...
-; CHECK:       add    sp, #4
-; CHECK-NEXT:  ldr    r12, [sp], #4
+; CHECK:  ldr    r12, [sp], #4
 ; CHECK-NEXT:  pop.w  {r7, lr}
+; CHECK-NEXT:  vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr} 
+; CHECK-NEXT:  vldr fpcxtns, [sp], #4 
 ; CHECK-NEXT:  aut    r12, lr, sp
-; CHECK-NEXT:  mrs    r12, control
-; ...
-; CHECK:       bxns    lr
+; CHECK-NEXT:  clrm {r1, r2, r3, r12, apsr}
+; CHECK-NEXT:  bxns    lr
 
 declare dso_local i32 @g(i32) local_unnamed_addr
 
-attributes #0 = { "cmse_nonsecure_entry" "target-features"="+8msecext,+armv8.1-m.main"}
-attributes #1 = { "cmse_nonsecure_entry" "target-features"="+8msecext,+armv8-m.main,+fp-armv8d16"}
+attributes #0 = { "cmse_nonsecure_entry" "target-features"="+8msecext"}
+attributes #1 = { "cmse_nonsecure_entry" "target-features"="+8msecext,+fp-armv8d16"}
 
 !llvm.module.flags = !{!0, !1, !2}
 
 !0 = !{i32 8, !"branch-target-enforcement", i32 0}
 !1 = !{i32 8, !"sign-return-address", i32 1}
 !2 = !{i32 8, !"sign-return-address-all", i32 0}
 
 ; UNWIND-LABEL: FunctionAddress: 0x0
 ; UNWIND:       0x00      ; vsp = vsp + 4
 ; UNWIND-NEXT:  0xB4      ; pop ra_auth_code
 ; UNWIND-NEXT:  0x84 0x08 ; pop {r7, lr}
 ; UNWIND-NEXT:  0xB0      ; finish
 ; UNWIND-NEXT:  0xB0      ; finish
 
 ; UNWIND-LABEL: FunctionAddress: 0x24
 ; UNWIND:       0xB4      ; pop ra_auth_code
 ; UNWIND-NEXT:  0x84 0x08 ; pop {r7, lr}
 
 ; UNWIND-LABEL: FunctionAddress: 0x54
-; UNWIND:       0x00      ; vsp = vsp + 4
-; UNWIND-NEXT:  0xB4      ; pop ra_auth_code
+; UNWIND:       0xB4      ; pop ra_auth_code
 ; UNWIND-NEXT:  0x84 0x08 ; pop {r7, lr}
-; UNWIND-NEXT:  0xB0      ; finish
-; UNWIND-NEXT:  0xB0      ; finish
 
 ; UNWIND-LABEL: 00000001 {{.*}} f0
 ; UNWIND-LABEL: 00000025 {{.*}} f1
 ; UNWIND-LABEL: 00000055 {{.*}} f2

llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll

 ; RUN: llc --force-dwarf-frame-section --exception-model=arm %s -o - | FileCheck %s
 ; RUN: llc --filetype=obj %s --exception-model=arm -o - | llvm-readelf -s --unwind - | FileCheck %s --check-prefix=UNWIND
 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
 
 ; Triple tweaked so we get 16-byte stack alignment and better test coverage.
-target triple = "armv7m-none-nacl-android"
+target triple = "thumbv8.1m.main-none-nacl-android"
 
 ; -Oz
 ; volatile int a, b, c, d, e, f, g, h, i;
 ;
 ; int x() {
 ;   int r = (a + b) / (c + d) + e + f / g + h + i;
 ;   return r + 1;
 ; }

llvm/test/CodeGen/Thumb2/pacbti-m-outliner-3.ll

 ; RUN: llc --force-dwarf-frame-section %s -o - | FileCheck %s
 ; RUN: llc --filetype=obj %s -o - | llvm-readelf -s --unwind - | FileCheck %s --check-prefix=UNWIND
 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
-target triple = "thumbv7m-arm-none-eabi"
+target triple = "thumbv8.1m.main-arm-none-eabi"
 
 ; -Oz
 ; __attribute__((noinline)) int h(int a, int b) { return a + b; }
 ;
 ; int f(int a, int b, int c, int d) {
 ;   if (a < 0)
 ;     return -1;
 ;   a = h(11 * a - b, b);

llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll

 ; RUN: llc --force-dwarf-frame-section %s -o - | FileCheck %s
 ; RUN: llc --filetype=obj %s -o - | llvm-readelf -s --unwind - | FileCheck %s --check-prefix=UNWIND
 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
-target triple = "thumbv7m-arm-none-eabi"
+target triple = "thumbv8.1m.main-arm-none-eabi"
 
 ; C++, -Oz
 ; __attribute__((noinline)) int h(int a, int b) {
 ;   if (a < 0)
 ;     throw 1;
 ;   return a + b;
 ; }
 ;

 ; CHECK-NEXT:    bx    lr
 
 
 ; CHEK-LABEL: OUTLINED_FUNCTION_0:
 ; CHECK-NOT: pac
 ; CHECK-NOT: aut
 ; CHECK:        b    _Z1hii
 
-attributes #0 = { minsize noinline optsize "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m3" "target-features"="+armv7-m,+hwdiv,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { minsize noinline optsize "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+hwdiv,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { nounwind }
 attributes #2 = { noreturn }
 
 
 !llvm.module.flags = !{!0, !1, !2}
 
 !0 = !{i32 8, !"branch-target-enforcement", i32 0}
 !1 = !{i32 8, !"sign-return-address", i32 1}

llvm/test/CodeGen/Thumb2/pacbti-m-outliner-5.ll

 ; RUN: llc %s -o - | FileCheck %s
 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
-target triple = "thumbv7m-arm-none-eabi"
+target triple = "thumbv8.1m.main-arm-none-eabi"
 
 ; CHECK-LABEL: x:
 ; CHECK: bl OUTLINED_FUNCTION
 ; CHECK-LABEL: y:
 ; CHECK: bl OUTLINED_FUNCTION
 ; CHECK-LABEL: z:
 ; CHECK-NOT: bl OUTLINED_FUNCTION
 

llvm/test/CodeGen/Thumb2/pacbti-m-unsupported-arch.ll

 ; RUN: llc -mtriple thumbv6m-eabi      %s -o - | FileCheck %s
 ; RUN: llc -mtriple thumbv8m.base-eabi %s -o - | FileCheck %s
 ; RUN: llc -mtriple thumbv7a-eabi %s      -o - | FileCheck %s
-; RUN: llc -mtriple thumbv7m-eabi      %s -o - | FileCheck %s --check-prefix=CHECK-PACBTI
+; RUN: llc -mtriple thumbv8.1m.main-eabi %s -o - | FileCheck %s --check-prefix=CHECK-PACBTI
 
 ; Check we don't emit PACBTI-M instructions for architectures
 ; that do not support them.
 define hidden i32 @f(i32 %x) #0 {
 entry:
   %x.addr = alloca i32, align 4
   store i32 %x, i32* %x.addr, align 4
   %0 = load i32, i32* %x.addr, align 4