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[clang-format] Handle Verilog modules
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Authored by sstwcw on Jun 28 2022, 1:31 AM.

Details

Summary

Now things inside hierarchies like modules and interfaces are
indented. When the module header spans multiple lines, all except the
first line are indented as continuations. We added the property
IsContinuation to mark lines that should be indented this way.

In order that the colons inside square brackets don't get labeled as
TT_ObjCMethodExpr, we added a check to only use this type when the
language is not Verilog.

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sstwcw created this revision.Jun 28 2022, 1:31 AM
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sstwcw requested review of this revision.Jun 28 2022, 1:31 AM
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clang/lib/Format/FormatToken.h
1742

Please write it out.

For a german hier has a different meaning. ;)

clang/lib/Format/TokenAnnotator.cpp
241

?

I don't know where this is also used.

Let's see what the others say.

766

See above.

sstwcw edited the summary of this revision. (Show Details)Jun 28 2022, 6:38 PM
sstwcw updated this revision to Diff 443605.Jul 11 2022, 5:17 AM
sstwcw edited the summary of this revision. (Show Details)
sstwcw marked 3 inline comments as done.
clang/lib/Format/UnwrappedLineParser.cpp
4042

I prefer to make such checks before calling the function.
But others have a different opinion.

No blocker for me.

4074

Using bools in integer expressions has caused some trouble in code I've seen. I'd prefer to use it as boolean.

sstwcw updated this revision to Diff 443791.Jul 11 2022, 5:11 PM
  • take out check
  • use boolean as boolean
sstwcw marked 2 inline comments as done.Jul 11 2022, 5:13 PM
sstwcw added inline comments.
clang/lib/Format/UnwrappedLineParser.cpp
4074

I am sorry. I should have fixed it myself since you had already pointed it out several times.

sstwcw marked an inline comment as done.Jul 11 2022, 5:14 PM
This revision is now accepted and ready to land.Jul 12 2022, 1:19 PM
This revision was automatically updated to reflect the committed changes.