[clang-format] Handle Verilog blocks

[sstwcw]

Summary

Now stuff inside begin-end blocks get indented.

Some tests are moved into FormatTestVerilog.Block from
FormatTestVerilog.If because they have nothing to do with if statements.

clang/lib/Format/FormatToken.h

#define LIST_TOKEN_TYPES                                                       \
   TYPE(TrailingAnnotation)                                                     \
   TYPE(TrailingReturnArrow)                                                    \
   TYPE(TrailingUnaryOperator)                                                  \
   TYPE(TypeDeclarationParen)                                                   \
   TYPE(TypenameMacro)                                                          \
   TYPE(UnaryOperator)                                                          \
   TYPE(UnionLBrace)                                                            \
   TYPE(UntouchableMacroFunc)                                                   \
+  /* like in begin : block */                                                  \
+  TYPE(VerilogBlockLabelColon)                                                 \
   /* for the base in a number literal, not including the quote */              \
   TYPE(VerilogNumberBase)                                                      \
   TYPE(Unknown)
 
 /// Determines the semantic type of a syntactic token, e.g. whether "<" is a
 /// template opener or binary operator.
 enum TokenType : uint8_t {
 #define TYPE(X) TT_##X,
AdditionalKeywords(IdentifierTable &IdentTable) {
     kw_uint = &IdentTable.get("uint");
     kw_ulong = &IdentTable.get("ulong");
     kw_unchecked = &IdentTable.get("unchecked");
     kw_unsafe = &IdentTable.get("unsafe");
     kw_ushort = &IdentTable.get("ushort");
     kw_when = &IdentTable.get("when");
     kw_where = &IdentTable.get("where");
 
+    // Verilog keywords
     kw_always = &IdentTable.get("always");
     kw_always_comb = &IdentTable.get("always_comb");
     kw_always_ff = &IdentTable.get("always_ff");
     kw_always_latch = &IdentTable.get("always_latch");
     kw_assign = &IdentTable.get("assign");
     kw_assume = &IdentTable.get("assume");
     kw_automatic = &IdentTable.get("automatic");
     kw_before = &IdentTable.get("before");

clang/lib/Format/TokenAnnotator.cpp

case tok::colon:
         if (Contexts.back().InCSharpAttributeSpecifier) {
           Tok->setType(TT_AttributeColon);
           break;
         }
         if (Contexts.back().ContextKind == tok::l_paren) {
           Tok->setType(TT_CSharpNamedArgumentColon);
           break;
         }
+      } else if (Style.isVerilog() && Tok->isNot(TT_BinaryOperator)) {
+        if (Keywords.isVerilogEnd(*Tok->Previous) ||
+            Keywords.isVerilogBegin(*Tok->Previous)) {
+          Tok->setType(TT_VerilogBlockLabelColon);
+        }
+        break;
       }
       if (Line.First->isOneOf(Keywords.kw_module, Keywords.kw_import) ||
           Line.First->startsSequence(tok::kw_export, Keywords.kw_module) ||
           Line.First->startsSequence(tok::kw_export, Keywords.kw_import)) {
         Tok->setType(TT_ModulePartitionColon);
       } else if (Contexts.back().ColonIsDictLiteral ||
                  Style.Language == FormatStyle::LK_Proto ||
                  Style.Language == FormatStyle::LK_TextProto) {

clang/lib/Format/UnwrappedLineParser.cpp

case tok::identifier: {
             break;
           }
         }
         parseRecord();
         addUnwrappedLine();
         return;
       }
 
+      if (Style.isVerilog()) {
+        if (Keywords.isVerilogBegin(*FormatTok)) {
+          parseBlock();
+          addUnwrappedLine();
+          return;
+        }
+      }
+
       if (FormatTok->is(Keywords.kw_interface)) {
         if (parseStructLike())
           return;
         break;
       }
 
       if (Style.isCpp() && FormatTok->is(TT_StatementMacro)) {
         parseStatementMacro();

clang/unittests/Format/FormatTestVerilog.cpp

TEST_F(FormatTestVerilog, BasedLiteral) {
   verifyFormat("x = 12'hx;");
   verifyFormat("x = 16'hz;");
   verifyFormat("x = -8'd6;");
   verifyFormat("x = 4'shf;");
   verifyFormat("x = -4'sd15;");
   verifyFormat("x = 16'sd?;");
 }
 
+TEST_F(FormatTestVerilog, Block) {
+  verifyFormat("begin\n"
+               "  x = x;\n"
+               "end");
+  verifyFormat("begin : x\n"
+               "  x = x;\n"
+               "end : x");
+  verifyFormat("begin\n"
+               "  x = x;\n"
+               "  x = x;\n"
+               "end");
+  verifyFormat("fork\n"
+               "  x = x;\n"
+               "join");
+  verifyFormat("fork\n"
+               "  x = x;\n"
+               "join_any");
+  verifyFormat("fork\n"
+               "  x = x;\n"
+               "join_none");
+  verifyFormat("generate\n"
+               "  x = x;\n"
+               "endgenerate");
+  verifyFormat("generate : x\n"
+               "  x = x;\n"
+               "endgenerate : x");
+  // Nested blocks.
+  verifyFormat("begin\n"
+               "  begin\n"
+               "  end\n"
+               "end");
+  verifyFormat("begin : x\n"
+               "  begin\n"
+               "  end\n"
+               "end : x");
+  verifyFormat("begin : x\n"
+               "  begin : x\n"
+               "  end : x\n"
+               "end : x");
+  verifyFormat("begin\n"
+               "  begin : x\n"
+               "  end : x\n"
+               "end");
+  // Test that 'disable fork' and 'rand join' don't get mistaken as blocks.
+  verifyFormat("disable fork;\n"
+               "x = x;");
+  verifyFormat("rand join x x;\n"
+               "x = x;");
+}
+
 TEST_F(FormatTestVerilog, Delay) {
   // Delay by the default unit.
   verifyFormat("#0;");
   verifyFormat("#1;");
   verifyFormat("#10;");
   verifyFormat("#1.5;");
   // Explicit unit.
   verifyFormat("#1fs;");
verifyFormat("if (x) begin\n"
                "end");
   verifyFormat("if (x) begin : x\n"
                "  x = x;\n"
                "end : x");
   verifyFormat("if (x) begin\n"
                "  x = x;\n"
                "  x = x;\n"
                "end");
-  verifyFormat("disable fork;\n"
-               "x = x;");
-  verifyFormat("rand join x x;\n"
-               "x = x;");
   verifyFormat("if (x) fork\n"
                "  x = x;\n"
                "join");
   verifyFormat("if (x) fork\n"
                "  x = x;\n"
                "join_any");
   verifyFormat("if (x) fork\n"
                "  x = x;\n"

clang/unittests/Format/TokenAnnotatorTest.cpp

TEST_F(TokenAnnotatorTest, UnderstandsVerilogOperators) {
   Tokens = Annotate("x = ~&x;");
   ASSERT_EQ(Tokens.size(), 7u) << Tokens;
   EXPECT_TOKEN(Tokens[2], tok::tilde, TT_UnaryOperator);
   EXPECT_TOKEN(Tokens[3], tok::amp, TT_UnaryOperator);
   Tokens = Annotate("x = ~|x;");
   ASSERT_EQ(Tokens.size(), 7u) << Tokens;
   EXPECT_TOKEN(Tokens[2], tok::tilde, TT_UnaryOperator);
   EXPECT_TOKEN(Tokens[3], tok::pipe, TT_UnaryOperator);
+  // Test for block label colons.
+  Tokens = Annotate("begin : x\n"
+                    "end : x");
+  ASSERT_EQ(Tokens.size(), 7u);
+  EXPECT_TOKEN(Tokens[1], tok::colon, TT_VerilogBlockLabelColon);
+  EXPECT_TOKEN(Tokens[4], tok::colon, TT_VerilogBlockLabelColon);
 }
 
 } // namespace
 } // namespace format
 } // namespace clang