[SelectionDAG] Teach computeKnownBits that a nsw self multiply produce a positive value.

[craig.topper]

Summary

This matches what we do in IR. For the RISC-V test case, this allows
us to use -8 for the AND mask instead of materializing a constant in a register.

[spatel]

LGTM

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

29

typo: convert

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

case ISD::MUL: {
     Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     bool SelfMultiply = Op.getOperand(0) == Op.getOperand(1);
     // TODO: SelfMultiply can be poison, but not undef.
     if (SelfMultiply)
       SelfMultiply &= isGuaranteedNotToBeUndefOrPoison(
           Op.getOperand(0), DemandedElts, false, Depth + 1);
     Known = KnownBits::mul(Known, Known2, SelfMultiply);
+
+    // If the multiplication is known not to overflow, the product of a number
+    // with itself is non-negative. Only do this if we didn't already computed
+    // the opposite value for the sign bit.
+    if (Op->getFlags().hasNoSignedWrap() &&
+        Op.getOperand(0) == Op.getOperand(1) &&
+        !Known.isNegative())
+      Known.makeNonNegative();
     break;
   }
   case ISD::MULHU: {
     Known = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known = KnownBits::mulhu(Known, Known2);
     break;
   }

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

; CHECK-NEXT:    ret
   %b = mul i32 %x, %x
   %c = add i32 %b, 1
   %d = mul i32 %c, %c
   %e = add i32 %d, %z
   %f = add i32 %e, 1
   %g = shl i32 %f, %y
   ret i32 %g
 }
+
+; The sign bit of an nsw self multiply is 0. Make sure we can use this to
+; convert the AND constant to -8.
+define i64 @mul_self_nsw_sign(i64 %x) {
+; CHECK-LABEL: mul_self_nsw_sign:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mul a0, a0, a0
+; CHECK-NEXT:    andi a0, a0, -8
+; CHECK-NEXT:    ret
+  %a = mul nsw i64 %x, %x
+  %b = and i64 %a, 9223372036854775800
+  ret i64 %b
+}

llvm/test/CodeGen/Thumb2/mve-vqdmulh-minmax.ll

for.cond.cleanup:                                 ; preds = %vector.body
   ret void
 }
 
 define i32 @scalar(i16 %a) {
 ; CHECK-LABEL: scalar:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    smulbb r1, r0, r0
 ; CHECK-NEXT:    movs r0, #127
-; CHECK-NEXT:    asrs r2, r1, #7
+; CHECK-NEXT:    lsrs r2, r1, #7
 ; CHECK-NEXT:    cmp r2, #127
 ; CHECK-NEXT:    it lt
-; CHECK-NEXT:    asrlt r0, r1, #7
+; CHECK-NEXT:    lsrlt r0, r1, #7
 ; CHECK-NEXT:    bx lr
   %e = sext i16 %a to i32
   %d = mul nsw i32 %e, %e
   %b = ashr i32 %d, 7
   %c = call i32 @llvm.smin.i32(i32 %b, i32 127)
   ret i32 %c
 }