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Differential D126567

[RISCV] Correct load/store alignments in sink-splat-operands.ll. NFC
ClosedPublic

Authored by craig.topper on May 27 2022, 2:24 PM.

Details

Reviewers
reames
frasercrmck
rogfer01
Commits
rG542a83c36222: [RISCV] Correct load/store alignments in sink-splat-operands.ll. NFC
Summary

These should be aligned to the natural alignment of the element.
Probably copy/paste mistake from the i32 tests.

Diff Detail

Event Timeline

craig.topper created this revision.May 27 2022, 2:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 27 2022, 2:24 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 27 others. · View Herald Transcript
craig.topper requested review of this revision.May 27 2022, 2:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 27 2022, 2:24 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
reames added a comment.May 27 2022, 2:27 PM

Did you maybe upload a bad diff? I only see test output changes in this, not changes to input or test commands.

craig.topper updated this revision to Diff 432638.May 27 2022, 2:29 PM

Upload complete diff

reames accepted this revision.May 27 2022, 2:31 PM

LGTM, thanks for catching this!

This revision is now accepted and ready to land.May 27 2022, 2:31 PM
This revision was landed with ongoing or failed builds.May 27 2022, 2:44 PM
Closed by commit rG542a83c36222: [RISCV] Correct load/store alignments in sink-splat-operands.ll. NFC (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG542a83c36222: [RISCV] Correct load/store alignments in sink-splat-operands.ll. NFC.
Harbormaster completed remote builds in B166708: Diff 432638.May 27 2022, 3:05 PM

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
77 lines

Diff 432639

llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

Show First 20 Lines • Show All 3,769 Lines • ▼ Show 20 Linesfor.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @sink_splat_mul_lmul2(i64* nocapture %a, i64 signext %x) { define void @sink_splat_mul_lmul2(i64* nocapture %a, i64 signext %x) {
; CHECK-LABEL: sink_splat_mul_lmul2: ; CHECK-LABEL: sink_splat_mul_lmul2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024 ; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: .LBB67_1: # %vector.body ; CHECK-NEXT: .LBB67_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmul.vx v8, v8, a1 ; CHECK-NEXT: vmul.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 32 ; CHECK-NEXT: addi a0, a0, 32
; CHECK-NEXT: bnez a2, .LBB67_1 ; CHECK-NEXT: bnez a2, .LBB67_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0 %broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0
%broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer %broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer
br label %vector.body br label %vector.body
vector.body: ; preds = %vector.body, %entry vector.body: ; preds = %vector.body, %entry
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%0 = getelementptr inbounds i64, i64* %a, i64 %index %0 = getelementptr inbounds i64, i64* %a, i64 %index
%1 = bitcast i64* %0 to <4 x i64>* %1 = bitcast i64* %0 to <4 x i64>*
%wide.load = load <4 x i64>, <4 x i64>* %1, align 4 %wide.load = load <4 x i64>, <4 x i64>* %1, align 8
%2 = mul <4 x i64> %wide.load, %broadcast.splat %2 = mul <4 x i64> %wide.load, %broadcast.splat
%3 = bitcast i64* %0 to <4 x i64>* %3 = bitcast i64* %0 to <4 x i64>*
store <4 x i64> %2, <4 x i64>* %3, align 4 store <4 x i64> %2, <4 x i64>* %3, align 8
%index.next = add nuw i64 %index, 4 %index.next = add nuw i64 %index, 4
%4 = icmp eq i64 %index.next, 1024 %4 = icmp eq i64 %index.next, 1024
br i1 %4, label %for.cond.cleanup, label %vector.body br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup: ; preds = %vector.body for.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @sink_splat_add_lmul2(i64* nocapture %a, i64 signext %x) { define void @sink_splat_add_lmul2(i64* nocapture %a, i64 signext %x) {
; CHECK-LABEL: sink_splat_add_lmul2: ; CHECK-LABEL: sink_splat_add_lmul2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024 ; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: .LBB68_1: # %vector.body ; CHECK-NEXT: .LBB68_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vadd.vx v8, v8, a1 ; CHECK-NEXT: vadd.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 32 ; CHECK-NEXT: addi a0, a0, 32
; CHECK-NEXT: bnez a2, .LBB68_1 ; CHECK-NEXT: bnez a2, .LBB68_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0 %broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0
%broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer %broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer
br label %vector.body br label %vector.body
vector.body: ; preds = %vector.body, %entry vector.body: ; preds = %vector.body, %entry
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%0 = getelementptr inbounds i64, i64* %a, i64 %index %0 = getelementptr inbounds i64, i64* %a, i64 %index
%1 = bitcast i64* %0 to <4 x i64>* %1 = bitcast i64* %0 to <4 x i64>*
%wide.load = load <4 x i64>, <4 x i64>* %1, align 4 %wide.load = load <4 x i64>, <4 x i64>* %1, align 8
%2 = add <4 x i64> %wide.load, %broadcast.splat %2 = add <4 x i64> %wide.load, %broadcast.splat
%3 = bitcast i64* %0 to <4 x i64>* %3 = bitcast i64* %0 to <4 x i64>*
store <4 x i64> %2, <4 x i64>* %3, align 4 store <4 x i64> %2, <4 x i64>* %3, align 8
%index.next = add nuw i64 %index, 4 %index.next = add nuw i64 %index, 4
%4 = icmp eq i64 %index.next, 1024 %4 = icmp eq i64 %index.next, 1024
br i1 %4, label %for.cond.cleanup, label %vector.body br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup: ; preds = %vector.body for.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @sink_splat_sub_lmul2(i64* nocapture %a, i64 signext %x) { define void @sink_splat_sub_lmul2(i64* nocapture %a, i64 signext %x) {
; CHECK-LABEL: sink_splat_sub_lmul2: ; CHECK-LABEL: sink_splat_sub_lmul2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024 ; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: .LBB69_1: # %vector.body ; CHECK-NEXT: .LBB69_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsub.vx v8, v8, a1 ; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 32 ; CHECK-NEXT: addi a0, a0, 32
; CHECK-NEXT: bnez a2, .LBB69_1 ; CHECK-NEXT: bnez a2, .LBB69_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0 %broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0
%broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer %broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer
br label %vector.body br label %vector.body
vector.body: ; preds = %vector.body, %entry vector.body: ; preds = %vector.body, %entry
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%0 = getelementptr inbounds i64, i64* %a, i64 %index %0 = getelementptr inbounds i64, i64* %a, i64 %index
%1 = bitcast i64* %0 to <4 x i64>* %1 = bitcast i64* %0 to <4 x i64>*
%wide.load = load <4 x i64>, <4 x i64>* %1, align 4 %wide.load = load <4 x i64>, <4 x i64>* %1, align 8
%2 = sub <4 x i64> %wide.load, %broadcast.splat %2 = sub <4 x i64> %wide.load, %broadcast.splat
%3 = bitcast i64* %0 to <4 x i64>* %3 = bitcast i64* %0 to <4 x i64>*
store <4 x i64> %2, <4 x i64>* %3, align 4 store <4 x i64> %2, <4 x i64>* %3, align 8
%index.next = add nuw i64 %index, 4 %index.next = add nuw i64 %index, 4
%4 = icmp eq i64 %index.next, 1024 %4 = icmp eq i64 %index.next, 1024
br i1 %4, label %for.cond.cleanup, label %vector.body br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup: ; preds = %vector.body for.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @sink_splat_rsub_lmul2(i64* nocapture %a, i64 signext %x) { define void @sink_splat_rsub_lmul2(i64* nocapture %a, i64 signext %x) {
; CHECK-LABEL: sink_splat_rsub_lmul2: ; CHECK-LABEL: sink_splat_rsub_lmul2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024 ; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: .LBB70_1: # %vector.body ; CHECK-NEXT: .LBB70_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vrsub.vx v8, v8, a1 ; CHECK-NEXT: vrsub.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 32 ; CHECK-NEXT: addi a0, a0, 32
; CHECK-NEXT: bnez a2, .LBB70_1 ; CHECK-NEXT: bnez a2, .LBB70_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0 %broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0
%broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer %broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer
br label %vector.body br label %vector.body
vector.body: ; preds = %vector.body, %entry vector.body: ; preds = %vector.body, %entry
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%0 = getelementptr inbounds i64, i64* %a, i64 %index %0 = getelementptr inbounds i64, i64* %a, i64 %index
%1 = bitcast i64* %0 to <4 x i64>* %1 = bitcast i64* %0 to <4 x i64>*
%wide.load = load <4 x i64>, <4 x i64>* %1, align 4 %wide.load = load <4 x i64>, <4 x i64>* %1, align 8
%2 = sub <4 x i64> %broadcast.splat, %wide.load %2 = sub <4 x i64> %broadcast.splat, %wide.load
%3 = bitcast i64* %0 to <4 x i64>* %3 = bitcast i64* %0 to <4 x i64>*
store <4 x i64> %2, <4 x i64>* %3, align 4 store <4 x i64> %2, <4 x i64>* %3, align 8
%index.next = add nuw i64 %index, 4 %index.next = add nuw i64 %index, 4
%4 = icmp eq i64 %index.next, 1024 %4 = icmp eq i64 %index.next, 1024
br i1 %4, label %for.cond.cleanup, label %vector.body br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup: ; preds = %vector.body for.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @sink_splat_and_lmul2(i64* nocapture %a, i64 signext %x) { define void @sink_splat_and_lmul2(i64* nocapture %a, i64 signext %x) {
; CHECK-LABEL: sink_splat_and_lmul2: ; CHECK-LABEL: sink_splat_and_lmul2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024 ; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: .LBB71_1: # %vector.body ; CHECK-NEXT: .LBB71_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vand.vx v8, v8, a1 ; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 32 ; CHECK-NEXT: addi a0, a0, 32
; CHECK-NEXT: bnez a2, .LBB71_1 ; CHECK-NEXT: bnez a2, .LBB71_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0 %broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0
%broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer %broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer
br label %vector.body br label %vector.body
vector.body: ; preds = %vector.body, %entry vector.body: ; preds = %vector.body, %entry
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%0 = getelementptr inbounds i64, i64* %a, i64 %index %0 = getelementptr inbounds i64, i64* %a, i64 %index
%1 = bitcast i64* %0 to <4 x i64>* %1 = bitcast i64* %0 to <4 x i64>*
%wide.load = load <4 x i64>, <4 x i64>* %1, align 4 %wide.load = load <4 x i64>, <4 x i64>* %1, align 8
%2 = and <4 x i64> %wide.load, %broadcast.splat %2 = and <4 x i64> %wide.load, %broadcast.splat
%3 = bitcast i64* %0 to <4 x i64>* %3 = bitcast i64* %0 to <4 x i64>*
store <4 x i64> %2, <4 x i64>* %3, align 4 store <4 x i64> %2, <4 x i64>* %3, align 8
%index.next = add nuw i64 %index, 4 %index.next = add nuw i64 %index, 4
%4 = icmp eq i64 %index.next, 1024 %4 = icmp eq i64 %index.next, 1024
br i1 %4, label %for.cond.cleanup, label %vector.body br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup: ; preds = %vector.body for.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @sink_splat_or_lmul2(i64* nocapture %a, i64 signext %x) { define void @sink_splat_or_lmul2(i64* nocapture %a, i64 signext %x) {
; CHECK-LABEL: sink_splat_or_lmul2: ; CHECK-LABEL: sink_splat_or_lmul2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024 ; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: .LBB72_1: # %vector.body ; CHECK-NEXT: .LBB72_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vor.vx v8, v8, a1 ; CHECK-NEXT: vor.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 32 ; CHECK-NEXT: addi a0, a0, 32
; CHECK-NEXT: bnez a2, .LBB72_1 ; CHECK-NEXT: bnez a2, .LBB72_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0 %broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0
%broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer %broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer
br label %vector.body br label %vector.body
vector.body: ; preds = %vector.body, %entry vector.body: ; preds = %vector.body, %entry
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%0 = getelementptr inbounds i64, i64* %a, i64 %index %0 = getelementptr inbounds i64, i64* %a, i64 %index
%1 = bitcast i64* %0 to <4 x i64>* %1 = bitcast i64* %0 to <4 x i64>*
%wide.load = load <4 x i64>, <4 x i64>* %1, align 4 %wide.load = load <4 x i64>, <4 x i64>* %1, align 8
%2 = or <4 x i64> %wide.load, %broadcast.splat %2 = or <4 x i64> %wide.load, %broadcast.splat
%3 = bitcast i64* %0 to <4 x i64>* %3 = bitcast i64* %0 to <4 x i64>*
store <4 x i64> %2, <4 x i64>* %3, align 4 store <4 x i64> %2, <4 x i64>* %3, align 8
%index.next = add nuw i64 %index, 4 %index.next = add nuw i64 %index, 4
%4 = icmp eq i64 %index.next, 1024 %4 = icmp eq i64 %index.next, 1024
br i1 %4, label %for.cond.cleanup, label %vector.body br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup: ; preds = %vector.body for.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @sink_splat_xor_lmul2(i64* nocapture %a, i64 signext %x) { define void @sink_splat_xor_lmul2(i64* nocapture %a, i64 signext %x) {
; CHECK-LABEL: sink_splat_xor_lmul2: ; CHECK-LABEL: sink_splat_xor_lmul2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024 ; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: .LBB73_1: # %vector.body ; CHECK-NEXT: .LBB73_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vxor.vx v8, v8, a1 ; CHECK-NEXT: vxor.vx v8, v8, a1
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -4 ; CHECK-NEXT: addi a2, a2, -4
; CHECK-NEXT: addi a0, a0, 32 ; CHECK-NEXT: addi a0, a0, 32
; CHECK-NEXT: bnez a2, .LBB73_1 ; CHECK-NEXT: bnez a2, .LBB73_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0 %broadcast.splatinsert = insertelement <4 x i64> poison, i64 %x, i64 0
%broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer %broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> poison, <4 x i32> zeroinitializer
br label %vector.body br label %vector.body
vector.body: ; preds = %vector.body, %entry vector.body: ; preds = %vector.body, %entry
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%0 = getelementptr inbounds i64, i64* %a, i64 %index %0 = getelementptr inbounds i64, i64* %a, i64 %index
%1 = bitcast i64* %0 to <4 x i64>* %1 = bitcast i64* %0 to <4 x i64>*
%wide.load = load <4 x i64>, <4 x i64>* %1, align 4 %wide.load = load <4 x i64>, <4 x i64>* %1, align 8
%2 = xor <4 x i64> %wide.load, %broadcast.splat %2 = xor <4 x i64> %wide.load, %broadcast.splat
%3 = bitcast i64* %0 to <4 x i64>* %3 = bitcast i64* %0 to <4 x i64>*
store <4 x i64> %2, <4 x i64>* %3, align 4 store <4 x i64> %2, <4 x i64>* %3, align 8
%index.next = add nuw i64 %index, 4 %index.next = add nuw i64 %index, 4
%4 = icmp eq i64 %index.next, 1024 %4 = icmp eq i64 %index.next, 1024
br i1 %4, label %for.cond.cleanup, label %vector.body br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup: ; preds = %vector.body for.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
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