[TableGen] Remove code beads

[0x59616e]

Summary

Code beads is useless since the only user, M68k, has moved on to
a new encoding/decoding infrastructure.

[0x59616e]

I've done a clean build and everything goes well. So I think it's ready for review.

[myhsu]

Please implement M68kInstrInfo::isPCRelRegisterOperandLegal as suggested by the inline comment. Otherwise rest of the patch looks good :-)

llvm/lib/Target/M68k/M68kInstrInfo.cpp

606–624

We can't mark this function as unimplemented. I added this isPCRelRegisterOperandLegal hook when we were upstreaming the m68k backend. The story behind this was that, as the comments suggested, a logical operand that has addressing mode 'k' is consisting of 3 MachineOperand, for example:

(87, %pc, %a1)

And we mark all three MachineOperand as pc-rel due to the nature of addressing mode 'k'. But MachineVerifier was not happy about this b/c it was not expecting a register operand (i.e. %a1 in the snippet above) to be marked as pc-rel. So this hook was added for MachineVerifier to check this very scenario. (The reason we didn't see this problem after the transition is because the new MC tests don't even get translated into MachineInstr).

One way to implement this function will be (manually) pattern matching against the opcode and the MachineOperand.

Here is a MachineInstr to test:

name: test_move32jk
body: |
  bb.0:
    MOV32jk $a1,  0, $a2, implicit-def $ccr

llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp

235

we can remove this debug print

llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn

15 ↗

(On Diff #431864)

Thanks for taking care GN as well!

[0x59616e]

Implement isPCRelRegisterOperandLegal

[0x59616e]

llvm/lib/Target/M68k/M68kInstrInfo.cpp

606–624

I use the operand number to distinguish between source and destination. And then use regular expression to check whether the instruction has 'k' addressing mode.

llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn

15 ↗

(On Diff #431864)

I did some google, and realize that gn is a build system that can generate ninja build files.

Why do we have this, given that cmake can do the same thing ?

[RKSimon]

llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn

15 ↗

(On Diff #431864)

Its used by some teams - the agreement was that it could be in the repo as long as everyone else doesn't have to worry about it :) Often you'll see auto? updates to the gn files after the equivalent cmakelists.txt file has been updated.

[myhsu]

llvm/lib/Target/M68k/M68kInstrInfo.cpp

622

You might want to handle tail call suffix ("_TC") as well (we're handling MachineInstr here, where tail call operators are still spelled out explicitly)

llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn

15 ↗

(On Diff #431864)

I did some google, and realize that gn is a build system that can generate ninja build files.

Why do we have this, given that cmake can do the same thing ?

GN has some advantages over cmake in terms of generating Ninja. For instance, the reconfiguration speed after a GN file modification is much faster than that of a cmake file modification. But as Simon mentioned, currently in LLVM it's just an optional Ninja generation method for some teams to use for easier integration with their existing build environment.

[aeubanks]

llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn

15 ↗

(On Diff #431864)

GN is an unsupported build system for LLVM, no need to update it if you aren't actively using it. better to let the bot update these files anyway if you aren't going to test it

[0x59616e]

llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn

15 ↗

(On Diff #431864)

Thanks for explanation ;)

As aeubanks suggested, I'll revert it in the next diff.

[0x59616e]

Consider tail call instruction when doing regex.

[myhsu]

LGTM

[myhsu]

Please add a MIR test (you can put it under test/CodeGen/M68k) for the new M68kInstrInfo::isPCRelRegisterOperandLegal to make sure it works well with MachineVerifier.

Sorry I forgot about this before I accepted the patch.

[0x59616e]

Add test

[myhsu]

llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir

1 ↗

(On Diff #432765)

The entire file can be (much) shorter:

# RUN: llc -O0 -mtriple=m68k -start-after=prologepilog -verify-machineinstrs %s -o - | FileCheck %s

name: is-pcrel-register-operand-legal
body:             |
  bb.0.entry:
    # CHECK: ...
    MOV32jk $a1,  0, $a0, implicit-def $ccr
    MOV32kj 0, $a1, $a0, implicit-def $ccr

[0x59616e]

shorten the test case

[myhsu]

llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir

5 ↗

(On Diff #432811)

I think this can be shorter. Could you try the code block I posted in the previous comment? (except the comment style for CHECK, it should be ';'). Note that -start-after=prologepilog is the key. Also please use -mtriple rather than -march for consistency.

[0x59616e]

llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir

5 ↗

(On Diff #432811)

Oh sorry, I didn't notice the -start-after=prologepilog.

[0x59616e]

shorten the test case

[myhsu]

Thank you!

[0x59616e]

Thanks for your help ;)

llvm/lib/Target/M68k/CMakeLists.txt

 add_llvm_component_group(M68k)
 
 set(LLVM_TARGET_DEFINITIONS M68k.td)
 
 tablegen(LLVM M68kGenGlobalISel.inc       -gen-global-isel)
 tablegen(LLVM M68kGenRegisterInfo.inc     -gen-register-info)
 tablegen(LLVM M68kGenRegisterBank.inc     -gen-register-bank)
 tablegen(LLVM M68kGenInstrInfo.inc        -gen-instr-info)
 tablegen(LLVM M68kGenSubtargetInfo.inc    -gen-subtarget)
-tablegen(LLVM M68kGenMCCodeBeads.inc      -gen-code-beads)
 tablegen(LLVM M68kGenMCCodeEmitter.inc    -gen-emitter)
 tablegen(LLVM M68kGenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM M68kGenDAGISel.inc          -gen-dag-isel)
 tablegen(LLVM M68kGenCallingConv.inc      -gen-callingconv)
 tablegen(LLVM M68kGenAsmWriter.inc        -gen-asm-writer)
 tablegen(LLVM M68kGenAsmMatcher.inc       -gen-asm-matcher)
 tablegen(LLVM M68kGenDisassemblerTable.inc -gen-disassembler)
 

llvm/lib/Target/M68k/M68kInstrInfo.cpp

 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/ScopeExit.h"
 #include "llvm/CodeGen/LivePhysRegs.h"
 #include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/Regex.h"
 
 #include <functional>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "M68k-instr-info"
 
 #define GET_INSTRINFO_CTOR_DTOR
case M68k::SETCS_C32d:
     return Expand2AddrUndef(MIB, get(M68k::SUBX32dd));
   }
   return false;
 }
 
 bool M68kInstrInfo::isPCRelRegisterOperandLegal(
     const MachineOperand &MO) const {
   assert(MO.isReg());
-  const auto *MI = MO.getParent();
-  const uint8_t *Beads = M68k::getMCInstrBeads(MI->getOpcode());
-  assert(*Beads);
-
-  // Only addressing mode k has (non-pc) register with PCRel
-  // So we're looking for EA Beads equal to
-  // `3Bits<011>_1Bit<1>_2Bits<11>`
-  // FIXME: There is an important caveat and two assumptions
-  // here: The caveat is that EA encoding always sit on the LSB.
-  // Where the assumptions are that if there are more than one
-  // operands, the EA encoding for the source operand always sit
-  // on the LSB. At the same time, k addressing mode can not be used
-  // on destination operand.
-  // The last assumption is kinda dirty so we need to find a way around
-  // it
-  const uint8_t EncEAk[3] = {0b011, 0b1, 0b11};
-  for (const uint8_t Pat : EncEAk) {
-    uint8_t Bead = *(Beads++);
-    if (!Bead)
-      return false;
 
-    switch (Bead & 0xF) {
-    default:
-      return false;
-    case M68kBeads::Bits1:
-    case M68kBeads::Bits2:
-    case M68kBeads::Bits3: {
-      uint8_t Val = (Bead & 0xF0) >> 4;
-      if (Val != Pat)
-        return false;
-    }
-    }
-  }
-  return true;
-}
+  // Check whether this MO belongs to an instruction with addressing mode 'k',
+  // Refer to TargetInstrInfo.h for more information about this function.
+
+  const MachineInstr *MI = MO.getParent();
+  const unsigned NameIndices = M68kInstrNameIndices[MI->getOpcode()];
+  StringRef InstrName(&M68kInstrNameData[NameIndices]);
+  const unsigned OperandNo = MI->getOperandNo(&MO);
+
+  // If this machine operand is the 2nd operand, then check
+  // whether the instruction has destination addressing mode 'k'.
+  if (OperandNo == 1)
+    return Regex("[A-Z]+(8|16|32)k[a-z](_TC)?$").match(InstrName);
+
+  // If this machine operand is the last one, then check
+  // whether the instruction has source addressing mode 'k'.
+  if (OperandNo == MI->getNumExplicitOperands() - 1)
+    return Regex("[A-Z]+(8|16|32)[a-z]k(_TC)?$").match(InstrName);
+
 
 void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI,
                                 const DebugLoc &DL, MCRegister DstReg,
                                 MCRegister SrcReg, bool KillSrc) const {
   unsigned Opc = 0;
 
   // First deal with the normal symmetric copies.

llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp

void encodePCRelImm(const MCInst &MI, unsigned OpIdx, unsigned InsertPos,
                       const MCSubtargetInfo &STI) const;
 
 public:
   M68kMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
       : MCII(mcii), Ctx(ctx) {}
 
   ~M68kMCCodeEmitter() override {}
 
-  // TableGen'erated function
-  const uint8_t *getGenInstrBeads(const MCInst &MI) const {
-    return M68k::getMCInstrBeads(MI.getOpcode());
-  }
-
-  unsigned encodeBits(unsigned ThisByte, uint8_t Bead, const MCInst &MI,
-                      const MCInstrDesc &Desc, uint64_t &Buffer,
-                      unsigned Offset, SmallVectorImpl<MCFixup> &Fixups,
-                      const MCSubtargetInfo &STI) const;
-
-  unsigned encodeReg(unsigned ThisByte, uint8_t Bead, const MCInst &MI,
-                     const MCInstrDesc &Desc, uint64_t &Buffer, unsigned Offset,
-                     SmallVectorImpl<MCFixup> &Fixups,
-                     const MCSubtargetInfo &STI) const;
-
-  unsigned encodeImm(unsigned ThisByte, uint8_t Bead, const MCInst &MI,
-                     const MCInstrDesc &Desc, uint64_t &Buffer, unsigned Offset,
-                     SmallVectorImpl<MCFixup> &Fixups,
-                     const MCSubtargetInfo &STI) const;
-
   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override;
 };
 
 } // end anonymous namespace
 
 #include "M68kGenMCCodeEmitter.inc"
if (!Op.getExpr()->evaluateAsAbsolute(Addr))
       report_fatal_error("Unsupported asm expression. Only absolute address "
                          "can be placed here.");
     Value |= static_cast<uint64_t>(Addr);
   } else {
     llvm_unreachable("Unsupported operand type");
   }
 }
 
-unsigned M68kMCCodeEmitter::encodeBits(unsigned ThisByte, uint8_t Bead,
-                                       const MCInst &MI,
-                                       const MCInstrDesc &Desc,
-                                       uint64_t &Buffer, unsigned Offset,
-                                       SmallVectorImpl<MCFixup> &Fixups,
-                                       const MCSubtargetInfo &STI) const {
-  unsigned Num = 0;
-  switch (Bead & 0xF) {
-  case M68kBeads::Bits1:
-    Num = 1;
-    break;
-  case M68kBeads::Bits2:
-    Num = 2;
-    break;
-  case M68kBeads::Bits3:
-    Num = 3;
-    break;
-  case M68kBeads::Bits4:
-    Num = 4;
-    break;
-  }
-  unsigned char Val = (Bead & 0xF0) >> 4;
-
-  LLVM_DEBUG(dbgs() << "\tEncodeBits"
-                    << " Num: " << Num << " Val: 0x");
-  LLVM_DEBUG(dbgs().write_hex(Val) << "\n");
-
-  Buffer |= (Val << Offset);
-
-  return Num;
-}
-
-unsigned M68kMCCodeEmitter::encodeReg(unsigned ThisByte, uint8_t Bead,
-                                      const MCInst &MI, const MCInstrDesc &Desc,
-                                      uint64_t &Buffer, unsigned Offset,
-                                      SmallVectorImpl<MCFixup> &Fixups,
-                                      const MCSubtargetInfo &STI) const {
-  bool DA, Reg;
-  switch (Bead & 0xF) {
-  default:
-    llvm_unreachable("Unrecognized Bead code for register type");
-  case M68kBeads::DAReg:
-    Reg = true;
-    DA = true;
-    break;
-  case M68kBeads::DA:
-    Reg = false;
-    DA = true;
-    break;
-  case M68kBeads::DReg:
-  case M68kBeads::Reg:
-    Reg = true;
-    DA = false;
-    break;
-  }
-
-  unsigned Op = (Bead & 0x70) >> 4;
-  bool Alt = (Bead & 0x80);
-  LLVM_DEBUG(dbgs() << "\tEncodeReg"
-                    << " Op: " << Op << ", DA: " << DA << ", Reg: " << Reg
-                    << ", Alt: " << Alt << "\n");
-
-  auto MIOpIdx = M68k::getLogicalOperandIdx(MI.getOpcode(), Op);
-  bool IsPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL;
-
-  MCOperand MCO;
-  if (M68kII::hasMultiMIOperands(MI.getOpcode(), Op)) {
-    if (IsPCRel) {
-      assert(Alt &&
-             "PCRel addresses use Alt bead register encoding by default");
-      MCO = MI.getOperand(MIOpIdx + M68k::PCRelIndex);
-    } else {
-      MCO = MI.getOperand(MIOpIdx + (Alt ? M68k::MemIndex : M68k::MemBase));
-    }
-  } else {
-    assert(!Alt && "You cannot use Alt register with a simple operand");
-    MCO = MI.getOperand(MIOpIdx);
-  }
-
-  unsigned RegNum = MCO.getReg();
-  auto RI = Ctx.getRegisterInfo();
-
-  unsigned Written = 0;
-  if (Reg) {
-    uint32_t Val = RI->getEncodingValue(RegNum);
-    Buffer |= (Val & 7) << Offset;
-    Offset += 3;
-    Written += 3;
-  }
-
-  if (DA) {
-    Buffer |= (uint64_t)M68kII::isAddressRegister(RegNum) << Offset;
-    Written++;
-  }
-
-  return Written;
-}
-
-static unsigned EmitConstant(uint64_t Val, unsigned Size, unsigned Pad,
-                             uint64_t &Buffer, unsigned Offset) {
-  assert(Size + Offset <= 64 && isUIntN(Size, Val) && "Value does not fit");
-
-  // Writing Value in host's endianness
-  Buffer |= (Val & ((1ULL << Size) - 1)) << Offset;
-  return Size + Pad;
-}
-
-unsigned M68kMCCodeEmitter::encodeImm(unsigned ThisByte, uint8_t Bead,
-                                      const MCInst &MI, const MCInstrDesc &Desc,
-                                      uint64_t &Buffer, unsigned Offset,
-                                      SmallVectorImpl<MCFixup> &Fixups,
-                                      const MCSubtargetInfo &STI) const {
-  unsigned ThisWord = ThisByte / 2;
-  unsigned Size = 0;
-  unsigned Pad = 0;
-  unsigned FixOffset = 0;
-  int64_t Addendum = 0;
-  bool NoExpr = false;
-
-  unsigned Type = Bead & 0xF;
-  unsigned Op = (Bead & 0x70) >> 4;
-  bool Alt = (Bead & 0x80);
-
-  auto MIOpIdx = M68k::getLogicalOperandIdx(MI.getOpcode(), Op);
-  bool IsPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL;
-
-  // The PC value upon instruction reading of a short jump will point to the
-  // next instruction, thus we need to compensate 2 bytes, which is the diff
-  // between the patch point and the PC.
-  if (IsPCRel && ThisWord == 0)
-    Addendum -= 2;
-
-  switch (Type) {
-  // ??? what happens if it is not byte aligned
-  // ??? is it even possible
-  case M68kBeads::Disp8:
-    Size = 8;
-    Pad = 0;
-    FixOffset = ThisByte + 1;
-    Addendum += 1;
-    break;
-  case M68kBeads::Imm8:
-    Size = 8;
-    Pad = 8;
-    FixOffset = ThisByte;
-    break;
-  case M68kBeads::Imm16:
-    Size = 16;
-    Pad = 0;
-    FixOffset = ThisByte;
-    break;
-  case M68kBeads::Imm32:
-    Size = 32;
-    Pad = 0;
-    FixOffset = ThisByte;
-    break;
-  case M68kBeads::Imm3:
-    Size = 3;
-    Pad = 0;
-    NoExpr = true;
-    break;
-  }
-
-  LLVM_DEBUG(dbgs() << "\tEncodeImm"
-                    << " Op: " << Op << ", Size: " << Size << ", Alt: " << Alt
-                    << "\n");
-
-  MCOperand MCO;
-  if (M68kII::hasMultiMIOperands(MI.getOpcode(), Op)) {
-
-    if (IsPCRel) {
-      assert(!Alt && "You cannot use ALT operand with PCRel");
-      MCO = MI.getOperand(MIOpIdx + M68k::PCRelDisp);
-    } else {
-      MCO = MI.getOperand(MIOpIdx + (Alt ? M68k::MemOuter : M68k::MemDisp));
-    }
-
-    if (MCO.isExpr()) {
-      assert(!NoExpr && "Cannot use expression here");
-      const MCExpr *Expr = MCO.getExpr();
-
-      // This only makes sense for PCRel instructions since PC points to the
-      // extension word and Disp8 for example is right justified and requires
-      // correction. E.g. R_68K_PC32 is calculated as S + A - P, P for Disp8
-      // will be EXTENSION_WORD + 1 thus we need to have A equal to 1 to
-      // compensate.
-      // TODO count extension words
-      if (IsPCRel && Addendum != 0) {
-        Expr = MCBinaryExpr::createAdd(
-            Expr, MCConstantExpr::create(Addendum, Ctx), Ctx);
-      }
-
-      Fixups.push_back(MCFixup::create(
-          FixOffset, Expr, getFixupForSize(Size, IsPCRel), MI.getLoc()));
-      // Write zeros
-      return EmitConstant(0, Size, Pad, Buffer, Offset);
-    }
-
-  } else {
-    MCO = MI.getOperand(MIOpIdx);
-    if (MCO.isExpr()) {
-      assert(!NoExpr && "Cannot use expression here");
-      const MCExpr *Expr = MCO.getExpr();
-
-      if (Addendum != 0) {
-        Expr = MCBinaryExpr::createAdd(
-            Expr, MCConstantExpr::create(Addendum, Ctx), Ctx);
-      }
-
-      Fixups.push_back(MCFixup::create(
-          FixOffset, Expr, getFixupForSize(Size, IsPCRel), MI.getLoc()));
-      // Write zeros
-      return EmitConstant(0, Size, Pad, Buffer, Offset);
-    }
-  }
-
-  int64_t I = MCO.getImm();
-
-  // Store 8 as 0, thus making range 1-8
-  if (Type == M68kBeads::Imm3 && Alt) {
-    assert(I && "Cannot encode Alt Imm3 zero value");
-    I %= 8;
-  } else {
-    assert(isIntN(Size, I));
-  }
-
-  uint64_t Imm = I;
-
-  // 32 bit Imm requires HI16 first then LO16
-  if (Size == 32) {
-    Offset += EmitConstant((Imm >> 16) & 0xFFFF, 16, Pad, Buffer, Offset);
-    EmitConstant(Imm & 0xFFFF, 16, Pad, Buffer, Offset);
-    return Size;
-  }
-
-  return EmitConstant(Imm & ((1ULL << Size) - 1), Size, Pad, Buffer, Offset);
-}
-
-#include "M68kGenMCCodeBeads.inc"
-
 void M68kMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                           SmallVectorImpl<MCFixup> &Fixups,
                                           const MCSubtargetInfo &STI) const {
   unsigned Opcode = MI.getOpcode();
   const MCInstrDesc &Desc = MCII.get(Opcode);
 
   LLVM_DEBUG(dbgs() << "EncodeInstruction: " << MCII.getName(Opcode) << "("
                     << Opcode << ")\n");
 
   // Try using the new method first.
   APInt EncodedInst(16, 0U);
   APInt Scratch(16, 0U);
   getBinaryCodeForInstr(MI, Fixups, EncodedInst, Scratch, STI);
-  if (EncodedInst.getBitWidth()) {
-    LLVM_DEBUG(dbgs() << "Instruction " << MCII.getName(Opcode) << "(" << Opcode
-                      << ") is using the new code emitter\n");
-    ArrayRef<uint64_t> Data(EncodedInst.getRawData(),
-                            EncodedInst.getNumWords());
-    int64_t InstSize = EncodedInst.getBitWidth();
-    for (uint64_t Word : Data) {
-      for (int i = 0; i < 4 && InstSize > 0; ++i, InstSize -= 16) {
-        support::endian::write<uint16_t>(OS, static_cast<uint16_t>(Word),
-                                         support::big);
-        Word >>= 16;
-      }
-    }
-    return;
-  }
-
-  const uint8_t *Beads = getGenInstrBeads(MI);
-  if (!Beads || !*Beads) {
-    llvm_unreachable("*** Instruction does not have Beads defined");
-  }
-
-  uint64_t Buffer = 0;
-  unsigned Offset = 0;
-  unsigned ThisByte = 0;
-
-  for (uint8_t Bead = *Beads; Bead; Bead = *++Beads) {
-    // Check for control beads
-    if (!(Bead & 0xF)) {
-      switch (Bead >> 4) {
-      case M68kBeads::Ignore:
-        continue;
-      }
-    }
-
-    switch (Bead & 0xF) {
-    default:
-      llvm_unreachable("Unknown Bead code");
-      break;
-    case M68kBeads::Bits1:
-    case M68kBeads::Bits2:
-    case M68kBeads::Bits3:
-    case M68kBeads::Bits4:
-      Offset +=
-          encodeBits(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI);
-      break;
-    case M68kBeads::DAReg:
-    case M68kBeads::DA:
-    case M68kBeads::DReg:
-    case M68kBeads::Reg:
-      Offset +=
-          encodeReg(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI);
-      break;
-    case M68kBeads::Disp8:
-    case M68kBeads::Imm8:
-    case M68kBeads::Imm16:
-    case M68kBeads::Imm32:
-    case M68kBeads::Imm3:
-      Offset +=
-          encodeImm(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI);
-      break;
-    }
-
-    // Since M68k is Big Endian we need to rotate each instruction word
-    while (Offset / 16) {
-      support::endian::write<uint16_t>(OS, Buffer, support::big);
-      Buffer >>= 16;
-      Offset -= 16;
-      ThisByte += 2;
-    }
-  }
-
-  assert(Offset == 0 && "M68k Instructions are % 2 bytes");
-  assert((ThisByte && !(ThisByte % 2)) && "M68k Instructions are % 2 bytes");
+
+  ArrayRef<uint64_t> Data(EncodedInst.getRawData(), EncodedInst.getNumWords());
 }
 
 MCCodeEmitter *llvm::createM68kMCCodeEmitter(const MCInstrInfo &MCII,
                                              MCContext &Ctx) {
   return new M68kMCCodeEmitter(MCII, Ctx);
 }

llvm/utils/TableGen/CMakeLists.txt

 add_subdirectory(GlobalISel)
 
 set(LLVM_LINK_COMPONENTS Support)
 
 add_tablegen(llvm-tblgen LLVM
   AsmMatcherEmitter.cpp
   AsmWriterEmitter.cpp
   AsmWriterInst.cpp
   Attributes.cpp
   CallingConvEmitter.cpp
-  CodeBeadsGen.cpp
   CodeEmitterGen.cpp
   CodeGenDAGPatterns.cpp
   CodeGenHwModes.cpp
   CodeGenInstruction.cpp
   CodeGenMapTable.cpp
   CodeGenRegisters.cpp
   CodeGenSchedule.cpp
   CodeGenTarget.cpp

llvm/utils/TableGen/CodeBeadsGen.cpp

-//===---------- CodeBeadsGen.cpp - Code Beads Generator -------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-// CodeBeads are data fields carrying auxiliary information for instructions.
-//
-// Under the hood it's simply implemented by a `bits` field (with arbitrary
-// length) in each TG instruction description, where this TG backend will
-// generate a helper function to access it.
-//
-// This is especially useful for expressing variable length encoding
-// instructions and complex addressing modes. Since in those cases each
-// instruction is usually associated with large amount of information like
-// addressing mode details used on a specific operand. Instead of retreating to
-// ad-hoc methods to figure out these information when encoding an instruction,
-// CodeBeads provide a clean table for the instruction encoder to lookup.
-//===----------------------------------------------------------------------===//
-
-#include "CodeGenInstruction.h"
-#include "CodeGenTarget.h"
-#include "llvm/ADT/StringExtras.h"
-#include "llvm/TableGen/Error.h"
-#include "llvm/TableGen/Record.h"
-#include "llvm/TableGen/TableGenBackend.h"
-#include <vector>
-using namespace llvm;
-
-namespace {
-
-class CodeBeadsGen {
-  RecordKeeper &Records;
-
-public:
-  CodeBeadsGen(RecordKeeper &R) : Records(R) {}
-  void run(raw_ostream &OS);
-};
-
-void CodeBeadsGen::run(raw_ostream &OS) {
-  CodeGenTarget Target(Records);
-  std::vector<Record *> Insts = Records.getAllDerivedDefinitions("Instruction");
-
-  // For little-endian instruction bit encodings, reverse the bit order
-  Target.reverseBitsForLittleEndianEncoding();
-
-  ArrayRef<const CodeGenInstruction *> NumberedInstructions =
-      Target.getInstructionsByEnumValue();
-
-  // Emit function declaration
-  OS << "const uint8_t *llvm::" << Target.getInstNamespace();
-  OS << "::getMCInstrBeads(unsigned Opcode) {\n";
-
-  // First, get the maximum bit length among all beads. And do some
-  // simple validation
-  unsigned MaxBitLength = 0;
-
-  for (const CodeGenInstruction *CGI : NumberedInstructions) {
-    Record *R = CGI->TheDef;
-    if (!R->getValue("Beads"))
-      continue;
-
-    BitsInit *BI = R->getValueAsBitsInit("Beads");
-    if (!BI->isComplete()) {
-      PrintFatalError(R->getLoc(), "Record `" + R->getName() +
-                                       "', bit field 'Beads' is not complete");
-    }
-
-    MaxBitLength = std::max(MaxBitLength, BI->getNumBits());
-  }
-
-  // Number of bytes
-  unsigned Parts = MaxBitLength / 8;
-
-  // Emit instruction base values
-  OS << "  static const uint8_t InstBits[][" << Parts << "] = {\n";
-  for (const CodeGenInstruction *CGI : NumberedInstructions) {
-    Record *R = CGI->TheDef;
-
-    if (R->getValueAsString("Namespace") == "TargetOpcode" ||
-        !R->getValue("Beads")) {
-      OS << "\t{ 0x0 },\t// ";
-      if (R->getValueAsBit("isPseudo"))
-        OS << "(Pseudo) ";
-      OS << R->getName() << "\n";
-      continue;
-    }
-
-    BitsInit *BI = R->getValueAsBitsInit("Beads");
-
-    // Convert to byte array:
-    // [dcba] -> [a][b][c][d]
-    OS << "\t{";
-    for (unsigned p = 0; p < Parts; ++p) {
-      unsigned Right = 8 * p;
-      unsigned Left = Right + 8;
-
-      uint8_t Value = 0;
-      for (unsigned i = Right; i != Left; ++i) {
-        unsigned Shift = i % 8;
-        if (auto *B = dyn_cast<BitInit>(BI->getBit(i))) {
-          Value |= (static_cast<uint8_t>(B->getValue()) << Shift);
-        } else {
-          PrintFatalError(R->getLoc(), "Record `" + R->getName() +
-                                           "', bit 'Beads[" + Twine(i) +
-                                           "]' is not defined");
-        }
-      }
-
-      if (p)
-        OS << ',';
-      OS << " 0x";
-      OS.write_hex(Value);
-      OS << "";
-    }
-    OS << " }," << '\t' << "// " << R->getName() << "\n";
-  }
-  OS << "\t{ 0x0 }\n  };\n";
-
-  // Emit initial function code
-  OS << "  return InstBits[Opcode];\n"
-     << "}\n\n";
-}
-
-} // End anonymous namespace
-
-namespace llvm {
-
-void EmitCodeBeads(RecordKeeper &RK, raw_ostream &OS) {
-  emitSourceFileHeader("Machine Code Beads", OS);
-  CodeBeadsGen(RK).run(OS);
-}
-
-} // namespace llvm

llvm/utils/TableGen/TableGen.cpp

 using namespace llvm;
 
 enum ActionType {
   PrintRecords,
   PrintDetailedRecords,
   NullBackend,
   DumpJSON,
   GenEmitter,
-  GenCodeBeads,
   GenRegisterInfo,
   GenInstrInfo,
   GenInstrDocs,
   GenAsmWriter,
   GenAsmMatcher,
   GenDisassembler,
   GenPseudoLowering,
   GenCompressInst,
cl::values(
                    "Print all records to stdout (default)"),
         clEnumValN(PrintDetailedRecords, "print-detailed-records",
                    "Print full details of all records to stdout"),
         clEnumValN(NullBackend, "null-backend",
                    "Do nothing after parsing (useful for timing)"),
         clEnumValN(DumpJSON, "dump-json",
                    "Dump all records as machine-readable JSON"),
         clEnumValN(GenEmitter, "gen-emitter", "Generate machine code emitter"),
-        clEnumValN(GenCodeBeads, "gen-code-beads",
-                   "Generate machine code beads"),
         clEnumValN(GenRegisterInfo, "gen-register-info",
                    "Generate registers and register classes info"),
         clEnumValN(GenInstrInfo, "gen-instr-info",
                    "Generate instruction descriptions"),
         clEnumValN(GenInstrDocs, "gen-instr-docs",
                    "Generate instruction documentation"),
         clEnumValN(GenCallingConv, "gen-callingconv",
                    "Generate calling convention descriptions"),
bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
   case NullBackend:             // No backend at all.
     break;
   case DumpJSON:
     EmitJSON(Records, OS);
     break;
   case GenEmitter:
     EmitCodeEmitter(Records, OS);
     break;
-  case GenCodeBeads:
-    EmitCodeBeads(Records, OS);
-    break;
   case GenRegisterInfo:
     EmitRegisterInfo(Records, OS);
     break;
   case GenInstrInfo:
     EmitInstrInfo(Records, OS);
     break;
   case GenInstrDocs:
     EmitInstrDocs(Records, OS);

llvm/utils/TableGen/TableGenBackends.h

 class RecordKeeper;
 
 void EmitIntrinsicEnums(RecordKeeper &RK, raw_ostream &OS);
 void EmitIntrinsicImpl(RecordKeeper &RK, raw_ostream &OS);
 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS);
 void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS);
 void EmitCallingConv(RecordKeeper &RK, raw_ostream &OS);
 void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS);
-void EmitCodeBeads(RecordKeeper &RK, raw_ostream &OS);
 void EmitDAGISel(RecordKeeper &RK, raw_ostream &OS);
 void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS);
 void EmitDisassembler(RecordKeeper &RK, raw_ostream &OS);
 void EmitFastISel(RecordKeeper &RK, raw_ostream &OS);
 void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS);
 void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS);
 void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS);
 void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS);