[BOLT] Increase coverage of shrink wrapping [2/5]

[rafauler]

Summary

Increase coverage of isStackAccess(), making frame opt able
to analyze more functions.

While this has been empirically determined to be one of the most
frequent instructions that need to be analyzed by shrink wrapping in
our use cases, it would be great to have a way of deriving this
information automatically, based on TableGen. I'm not sure this can be
done at the moment, so we rely expanding our logic here.

[Amir]

LGTM but didn't check every new line.

bolt/lib/Target/X86/X86MCPlusBuilder.cpp

1100

There might be a way to fetch memory access size: D126116 (WIP).
Regarding the rest of the fields: IsLoad/IsStore are straightforward. StoreFromReg and IsSimple are somewhat difficult. Let's address them later.

I think it's best to pull this diff in, and remove it later with D126116 after NFC testing.

[rafauler]

Rebase

bolt/lib/Target/X86/X86MCPlusBuilder.cpp

default: {
       bool IsStore = MCII.mayStore();
       // Is it LEA? (deals with memory but is not loading nor storing)
       if (!IsLoad && !IsStore)
         return false;
       uint8_t Sz = getMemDataSize(Inst, MemOpNo);
       I = {Sz, IsLoad, IsStore, false, false};
       break;
     }
+    // Report simple stack accesses
+    case X86::MOV8rm: I = {1, true, false, false, true}; break;
     case X86::MOV16rm: I = {2, true, false, false, true}; break;
     case X86::MOV32rm: I = {4, true, false, false, true}; break;
     case X86::MOV64rm: I = {8, true, false, false, true}; break;
+    case X86::MOV8mr: I = {1, false, true, true, true};  break;
     case X86::MOV16mr: I = {2, false, true, true, true};  break;
     case X86::MOV32mr: I = {4, false, true, true, true};  break;
     case X86::MOV64mr: I = {8, false, true, true, true};  break;
+    case X86::MOV8mi: I = {1, false, true, false, true}; break;
     case X86::MOV16mi: I = {2, false, true, false, true}; break;
     case X86::MOV32mi: I = {4, false, true, false, true}; break;
     } // end switch (Inst.getOpcode())
 
     unsigned BaseRegNum;
     int64_t ScaleValue;
     unsigned IndexRegNum;
     int64_t DispValue;