[GISel] Combine G_FMULs into G_FABS/G_FNEG(G_FABS)

[mkitzan]

Summary

Patch adds new GICombineRules for G_FMUL:

• G_FMUL(x, G_SELECT(G_FCMP(x > 0.0), -1.0, 1.0) -> G_FNEG(G_FABS(x))
• G_FMUL(x, G_SELECT(G_FCMP(x > 0.0), 1.0, -1.0)) -> G_FABS(x)

Patch additionally adds new combine tests for AArch64 target for these new rules.
(Split off from https://reviews.llvm.org/D87870)

[arsenm]

Should try new combiner pattern support

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

 //===--------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
 #define LLVM_CODEGEN_GLOBALISEL_COMBINERHELPER_H
 
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/Register.h"
+#include "llvm/IR/InstrTypes.h"
 #include "llvm/Support/LowLevelTypeImpl.h"
 #include <functional>
 
 namespace llvm {
 
 class GISelChangeObserver;
 class APFloat;
 class APInt;
public:
   bool matchCombineFSubFpExtFNegFMulToFMadOrFMA(MachineInstr &MI,
                                                 BuildFnTy &MatchInfo);
 
   /// Fold boolean selects to logical operations.
   bool matchSelectToLogical(MachineInstr &MI, BuildFnTy &MatchInfo);
 
   bool matchCombineFMinMaxNaN(MachineInstr &MI, unsigned &Info);
 
+  /// Transform G_FMUL(x, G_SELECT(G_FCMP(x > 0.0), -1.0, 1.0)) or
+  ///           G_FMUL(G_SELECT(G_FCMP(x > 0.0), -1.0, 1.0), x) or
+  ///           G_FMUL(x, G_SELECT(G_FCMP(x <= 0.0), 1.0, -1.0)) or
+  ///           G_FMUL(G_SELECT(G_FCMP(x <= 0.0), 1.0, -1.0), x) to
+  /// G_FNEG(G_FABS(x)).
+  /// Transform G_FMUL(x, G_SELECT(G_FCMP(x > 0.0), 1.0, -1.0)) or
+  ///           G_FMUL(G_SELECT(G_FCMP(x > 0.0), 1.0, -1.0), x) or
+  ///           G_FMUL(x, G_SELECT(G_FCMP(x <= 0.0), -1.0, 1.0)) or
+  ///           G_FMUL(G_SELECT(G_FCMP(x <= 0.0), -1.0, 1.0), x) to
+  /// G_FABS(x).
+  bool matchForceFPNegOrPos(MachineInstr &MI,
+                            std::pair<Register, bool> &MatchInfo);
+  bool applyForceFPNegOrPos(MachineInstr &MI,
+                            std::pair<Register, bool> &MatchInfo);
+
 private:
   /// Given a non-indexed load or store instruction \p MI, find an offset that
   /// can be usefully and legally folded into it as a post-indexing operation.
   ///
   /// \returns true if a candidate is found.
   bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
                               Register &Offset);
 

llvm/include/llvm/Target/GlobalISel/Combine.td

 
 def combine_minmax_nan_matchinfo: GIDefMatchData<"unsigned">;
 def combine_minmax_nan: GICombineRule<
   (defs root:$root, combine_minmax_nan_matchinfo:$info),
   (match (wip_match_opcode G_FMINNUM, G_FMAXNUM, G_FMINIMUM, G_FMAXIMUM):$root,
          [{ return Helper.matchCombineFMinMaxNaN(*${root}, ${info}); }]),
   (apply [{ Helper.replaceSingleDefInstWithOperand(*${root}, ${info}); }])>;
 
+// Transform (fmul x, (select (fcmp x > 0.0), -1.0, 1.0))  -> (fneg (fabs X))
+//           (fmul (select (fcmp x > 0.0), -1.0, 1.0), x)  -> (fneg (fabs X))
+//           (fmul x, (select (fcmp x <= 0.0), 1.0, -1.0)) -> (fneg (fabs X))
+//           (fmul (select (fcmp x <= 0.0), 1.0, -1.0), x) -> (fneg (fabs X))
+// Transform (fmul x, (select (fcmp x > 0.0), 1.0, -1.0))  -> (fabs X)
+//           (fmul (select (fcmp x > 0.0), 1.0, -1.0), x)  -> (fabs X)
+//           (fmul x, (select (fcmp x <= 0.0), -1.0, 1.0)) -> (fabs X)
+//           (fmul (select (fcmp x <= 0.0), -1.0, 1.0), x) -> (fabs X)
+def fp_neg_or_pos_matchinfo : GIDefMatchData<"std::pair<Register, bool>">;
+def fp_neg_or_pos: GICombineRule<
+  (defs root:$root, fp_neg_or_pos_matchinfo:$matchinfo),
+  (match (wip_match_opcode G_FMUL):$root,
+         [{ return Helper.matchForceFPNegOrPos(*${root}, ${matchinfo}); }]),
+  (apply [{ return Helper.applyForceFPNegOrPos(*${root}, ${matchinfo}); }])>;
+
 // FIXME: These should use the custom predicate feature once it lands.
 def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
                                      undef_to_negative_one,
                                      binop_left_undef_to_zero,
                                      binop_right_undef_to_undef,
                                      propagate_undef_any_op,
                                      propagate_undef_all_ops,
                                      propagate_undef_shuffle_mask,
def trivial_combines : GICombineGroup<[copy_prop, mul_to_shl, add_p2i_to_ptradd,
                                        mul_by_neg_one]>;
 
 def fma_combines : GICombineGroup<[combine_fadd_fmul_to_fmad_or_fma,
   combine_fadd_fpext_fmul_to_fmad_or_fma, combine_fadd_fma_fmul_to_fmad_or_fma,
   combine_fadd_fpext_fma_fmul_to_fmad_or_fma, combine_fsub_fmul_to_fmad_or_fma,
   combine_fsub_fneg_fmul_to_fmad_or_fma, combine_fsub_fpext_fmul_to_fmad_or_fma,
   combine_fsub_fpext_fneg_fmul_to_fmad_or_fma]>;
 
+def fp_combines : GICombineGroup<[fma_combines, fp_neg_or_pos]>;
+
 def all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines,
     extract_vec_elt_combines, combines_for_extload,
     combine_indexed_load_store, undef_combines, identity_combines, phi_combines,
     simplify_add_to_sub, hoist_logic_op_with_same_opcode_hands,
     reassocs, ptr_add_immed_chain,
     shl_ashr_to_sext_inreg, sext_inreg_of_load,
     width_reduction_combines, select_combines,
     known_bits_simplifications, ext_ext_fold,
     not_cmp_fold, opt_brcond_by_inverting_cond,
     unmerge_merge, fabs_fabs_fold, unmerge_cst, unmerge_dead_to_trunc,
     unmerge_zext_to_zext, merge_unmerge, trunc_ext_fold, trunc_shl,
     const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
     shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine,
     truncstore_merge, div_rem_to_divrem, funnel_shift_combines,
     form_bitfield_extract, constant_fold, fabs_fneg_fold,
     intdiv_combines, mulh_combines, redundant_neg_operands,
-    and_or_disjoint_mask, fma_combines, fold_binop_into_select]>;
+    and_or_disjoint_mask, fp_combines, fold_binop_into_select]>;
 
 // A combine group used to for prelegalizer combiners at -O0. The combines in
 // this group have been selected based on experiments to balance code size and
 // compile time performance.
 def optnone_combines : GICombineGroup<[trivial_combines,
     ptr_add_immed_chain, combines_for_extload,
     not_cmp_fold, opt_brcond_by_inverting_cond]>;

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

if (!MaybeCst || !MaybeCst->getValueAPF().isNaN())
       return false;
     IdxToPropagate = PropagateNaN ? Idx : (Idx == 1 ? 2 : 1);
     return true;
   };
 
   return MatchNaN(1) || MatchNaN(2);
 }
 
+bool CombinerHelper::matchForceFPNegOrPos(
+    MachineInstr &MI, std::pair<Register, bool> &MatchInfo) {
+  assert(MI.getOpcode() == TargetOpcode::G_FMUL && "Expected a G_FMUL");
+  // `G_FMUL`s which allow NaNs or consider signed-zero aren't candidates for
+  // this optimization.
+  if (!MI.getFlag(MachineInstr::MIFlag::FmNoNans) ||
+      !MI.getFlag(MachineInstr::MIFlag::FmNsz))
+    return false;
+
+  Register Src;
+  CmpInst::Predicate Pred;
+  const ConstantFP *SelecteeLHS{};
+  const ConstantFP *SelecteeRHS{};
+  auto MatchFPNegOrPos = [&](Register SelectSrc, Register SameSrc) {
+    Register CompareeLHS;
+    const ConstantFP *CompareeRHS{};
+    if (!mi_match(SelectSrc, MRI,
+                  m_GISelect(m_GFCmp(m_Pred(Pred), m_Reg(CompareeLHS),
+                                     m_GFCst(CompareeRHS)),
+                             m_GFCst(SelecteeLHS), m_GFCst(SelecteeRHS))))
+      return false;
+    if (CompareeLHS != SameSrc ||
+        !CompareeRHS->getValueAPF().isExactlyValue(0.0))
+      return false;
+    Src = SameSrc;
+    return true;
+  };
+
+  Register SrcLHS = MI.getOperand(1).getReg();
+  Register SrcRHS = MI.getOperand(2).getReg();
+  if (!MatchFPNegOrPos(SrcLHS, SrcRHS) && !MatchFPNegOrPos(SrcRHS, SrcLHS))
+    return false;
+
+  APFloat TrueValue = SelecteeLHS->getValueAPF();
+  APFloat FalseValue = SelecteeRHS->getValueAPF();
+  switch (Pred) {
+  default:
+    return false;
+  case CmpInst::FCMP_OLE:
+  case CmpInst::FCMP_ULE:
+    std::swap(TrueValue, FalseValue);
+    break;
+  case CmpInst::FCMP_OGT:
+  case CmpInst::FCMP_UGT:
+    break;
+  }
+
+  if (TrueValue.isExactlyValue(-1.0) && FalseValue.isExactlyValue(1.0)) {
+    MatchInfo = std::make_pair(Src, /*ForceNegate*/ true);
+    return true;
+  }
+  if (TrueValue.isExactlyValue(1.0) && FalseValue.isExactlyValue(-1.0)) {
+    MatchInfo = std::make_pair(Src, /*ForceNegate*/ false);
+    return true;
+  }
+
+  return false;
+}
+
+bool CombinerHelper::applyForceFPNegOrPos(
+    MachineInstr &MI, std::pair<Register, bool> &MatchInfo) {
+  assert(MI.getOpcode() == TargetOpcode::G_FMUL && "Expected a G_FMUL");
+  Register Dst = MI.getOperand(0).getReg();
+  LLT DstTy = MRI.getType(Dst);
+  Register Src = MatchInfo.first;
+  bool ForceNegate = MatchInfo.second;
+
+  Builder.setInstrAndDebugLoc(MI);
+  if (ForceNegate) {
+    auto FAbsMIB = Builder.buildFAbs({DstTy}, {Src});
+    Builder.buildFNeg({Dst}, {FAbsMIB}, MI.getFlags());
+  } else {
+    Builder.buildFAbs({Dst}, {Src});
+  }
+  MI.eraseFromParent();
+  return true;
+}
+
 bool CombinerHelper::tryCombine(MachineInstr &MI) {
   if (tryCombineCopy(MI))
     return true;
   if (tryCombineExtendingLoads(MI))
     return true;
   if (tryCombineIndexedLoadStore(MI))
     return true;
   return false;
 }

llvm/test/CodeGen/AArch64/GlobalISel/combine-fmul.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+
+---
+name:            make_fp_negative_rhs_select_gt
+body:             |
+  bb.1:
+    liveins: $w0
+    ; CHECK-LABEL: name: make_fp_negative_rhs_select_gt
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan nsz G_FNEG [[FABS]]
+    ; CHECK-NEXT: $w0 = COPY [[FNEG]](s32)
+    %0:_(s32) = COPY $w0
+    %1:_(s32) = G_FCONSTANT float 0.0
+    %2:_(s1) = G_FCMP floatpred(ogt), %0, %1
+    %3:_(s32) = G_FCONSTANT float -1.0
+    %4:_(s32) = G_FCONSTANT float 1.0
+    %5:_(s32) = G_SELECT %2(s1), %3, %4
+    %6:_(s32) = nnan nsz G_FMUL %0, %5
+    $w0 = COPY %6(s32)
+...
+---
+name:            make_fp_positive_rhs_select_gt
+body:             |
+  bb.1:
+    liveins: $w0
+    ; CHECK-LABEL: name: make_fp_positive_rhs_select_gt
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+    ; CHECK-NEXT: $w0 = COPY [[FABS]](s32)
+    %0:_(s32) = COPY $w0
+    %1:_(s32) = G_FCONSTANT float 0.0
+    %2:_(s1) = G_FCMP floatpred(ogt), %0, %1
+    %3:_(s32) = G_FCONSTANT float 1.0
+    %4:_(s32) = G_FCONSTANT float -1.0
+    %5:_(s32) = G_SELECT %2(s1), %3, %4
+    %6:_(s32) = nnan nsz G_FMUL %0, %5
+    $w0 = COPY %6(s32)
+...
+---
+name:            make_fp_negative_rhs_select_le
+body:             |
+  bb.1:
+    liveins: $w0
+    ; CHECK-LABEL: name: make_fp_negative_rhs_select_le
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan nsz G_FNEG [[FABS]]
+    ; CHECK-NEXT: $w0 = COPY [[FNEG]](s32)
+    %0:_(s32) = COPY $w0
+    %1:_(s32) = G_FCONSTANT float 0.0
+    %2:_(s1) = G_FCMP floatpred(ole), %0, %1
+    %3:_(s32) = G_FCONSTANT float 1.0
+    %4:_(s32) = G_FCONSTANT float -1.0
+    %5:_(s32) = G_SELECT %2(s1), %3, %4
+    %6:_(s32) = nnan nsz G_FMUL %0, %5
+    $w0 = COPY %6(s32)
+...
+---
+name:            make_fp_positive_rhs_select_le
+body:             |
+  bb.1:
+    liveins: $w0
+    ; CHECK-LABEL: name: make_fp_positive_rhs_select_le
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+    ; CHECK-NEXT: $w0 = COPY [[FABS]](s32)
+    %0:_(s32) = COPY $w0
+    %1:_(s32) = G_FCONSTANT float 0.0
+    %2:_(s1) = G_FCMP floatpred(ole), %0, %1
+    %3:_(s32) = G_FCONSTANT float -1.0
+    %4:_(s32) = G_FCONSTANT float 1.0
+    %5:_(s32) = G_SELECT %2(s1), %3, %4
+    %6:_(s32) = nnan nsz G_FMUL %0, %5
+    $w0 = COPY %6(s32)
+...
+---
+name:            make_fp_negative_lhs_select_gt
+body:             |
+  bb.1:
+    liveins: $w0
+    ; CHECK-LABEL: name: make_fp_negative_lhs_select_gt
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan nsz G_FNEG [[FABS]]
+    ; CHECK-NEXT: $w0 = COPY [[FNEG]](s32)
+    %0:_(s32) = COPY $w0
+    %1:_(s32) = G_FCONSTANT float 0.0
+    %2:_(s1) = G_FCMP floatpred(ogt), %0, %1
+    %3:_(s32) = G_FCONSTANT float -1.0
+    %4:_(s32) = G_FCONSTANT float 1.0
+    %5:_(s32) = G_SELECT %2(s1), %3, %4
+    %6:_(s32) = nnan nsz G_FMUL %5, %0
+    $w0 = COPY %6(s32)
+...
+---
+name:            make_fp_positive_lhs_select_gt
+body:             |
+  bb.1:
+    liveins: $w0
+    ; CHECK-LABEL: name: make_fp_positive_lhs_select_gt
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+    ; CHECK-NEXT: $w0 = COPY [[FABS]](s32)
+    %0:_(s32) = COPY $w0
+    %1:_(s32) = G_FCONSTANT float 0.0
+    %2:_(s1) = G_FCMP floatpred(ogt), %0, %1
+    %3:_(s32) = G_FCONSTANT float 1.0
+    %4:_(s32) = G_FCONSTANT float -1.0
+    %5:_(s32) = G_SELECT %2(s1), %3, %4
+    %6:_(s32) = nnan nsz G_FMUL %5, %0
+    $w0 = COPY %6(s32)
+...
+---
+name:            make_fp_negative_lhs_select_le
+body:             |
+  bb.1:
+    liveins: $w0
+    ; CHECK-LABEL: name: make_fp_negative_lhs_select_le
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+    ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = nnan nsz G_FNEG [[FABS]]
+    ; CHECK-NEXT: $w0 = COPY [[FNEG]](s32)
+    %0:_(s32) = COPY $w0
+    %1:_(s32) = G_FCONSTANT float 0.0
+    %2:_(s1) = G_FCMP floatpred(ole), %0, %1
+    %3:_(s32) = G_FCONSTANT float 1.0
+    %4:_(s32) = G_FCONSTANT float -1.0
+    %5:_(s32) = G_SELECT %2(s1), %3, %4
+    %6:_(s32) = nnan nsz G_FMUL %5, %0
+    $w0 = COPY %6(s32)
+...
+---
+name:            make_fp_positive_lhs_select_le
+body:             |
+  bb.1:
+    liveins: $w0
+    ; CHECK-LABEL: name: make_fp_positive_lhs_select_le
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+    ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+    ; CHECK-NEXT: $w0 = COPY [[FABS]](s32)
+    %0:_(s32) = COPY $w0
+    %1:_(s32) = G_FCONSTANT float 0.0
+    %2:_(s1) = G_FCMP floatpred(ole), %0, %1
+    %3:_(s32) = G_FCONSTANT float -1.0
+    %4:_(s32) = G_FCONSTANT float 1.0
+    %5:_(s32) = G_SELECT %2(s1), %3, %4
+    %6:_(s32) = nnan nsz G_FMUL %5, %0
+    $w0 = COPY %6(s32)
+...