[AMDGPU][GFX9] Support base+soffset+offset SMEM loads.

[kosarev]

Summary

Resolves part of
https://github.com/llvm/llvm-project/issues/38652

[rampitec]

llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

10083

Is there a decoding conflict which requires to use brackets here? Something from the TODO list?

[arsenm]

llvm/test/MC/AMDGPU/gfx9_asm_smem.s

126

An unaligned offset is suspicious looking but technically not wrong

llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

10083

I'm not sure what this question means. The encoding is always printed in brackets?

[arsenm]

I thought we codegened these already? Is this missing a codegen change to use the offsets?

[rampitec]

llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

10083

Printed yes. But disasm tests do not use brackets. These are needed in a stream of bytes when dis cannot find out a boundaries of an instruction itself, and that is usually an indication of disam conflict between subtargets.

[kosarev]

llvm/test/MC/AMDGPU/gfx9_asm_smem.s

126

I assume we are only interested in how instructions are getting encoded here, so no need for them to look very realistic?

llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

10083

I too see no bracketed input bytes here, only printed ones. May this be the case that you just see them on a separate line because of the larger length of the instruction?

[kosarev]

In D125700#3517167, @arsenm wrote:

I thought we codegened these already? Is this missing a codegen change to use the offsets?

This intentionally misses any codegen changes, yes.

llvm/lib/Target/AMDGPU/SMInstructions.td

544

Would love some opinions on how important we think it would be to support that. If I don't miss anything, addressing this would mean either further customising AMDGPUDisassembler::getInstruction() or split the TableGen definitions for GFX8 and GFX9 -- and not just the SMEM ones. Which seems to be a significant amount of changes.

[rampitec]

llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

10083

Oh, yes. This is formatting, not really brackets on input.

[rampitec]

llvm/test/MC/AMDGPU/gfx9_asm_smem.s

126

Isn't the final address has to be aligned, not partial offsets? I.e. this shall be fine even if we wanted to enforce something in the asm.

[kosarev]

llvm/test/MC/AMDGPU/gfx9_asm_smem.s

126

Yes, my understanding is that it's only the resulting address that has to be aligned.

[dp]

Overall looks good.

llvm/lib/Target/AMDGPU/SMInstructions.td

544

// TODO: Ignore soffset_en when disassembling GFX8 instructions.

Are there cases when an illegal GFX8 code may be decoded with soffset_en=1? The _SGPR_IMM_vi case should not work for GFX8, should it?

560

This addressing mode is semantically equivalent to the one where soffset is encoded in the offset field. I'm not sure we really need it. Note that sp3 has no syntactic sugar to enforce this encoding. It may be useful for decoder, but I doubt it worth the trouble.

561

Ditto.

llvm/test/MC/AMDGPU/gfx9_asm_smem.s

63

It is a minor issue, but I noted that all your new tests use soffset=s0. It may be a good idea to avoid operands which are encoded as 0 (or add tests with other operands as well).

[arsenm]

llvm/test/MC/AMDGPU/gfx9_asm_smem.s

126

Yes, the final address is all that matters. But practically speaking that always means a well aligned offset (still not sure why they switched this to a byte offset)

[kosarev]

llvm/lib/Target/AMDGPU/SMInstructions.td

544

Not sure I read the question right, but I understand, e.g., 0xc0024141 0x00012345 (with imm=1 and soffset_en=1) should decode to s_load_dword s5, s[2:3], s0 offset:0x12345 in GFX9 and to s_load_dword s5, s[2:3], 0x12345 in GFX8. With this patch in place we fail to do the latter because our GFX8 and GFX9 definitions share the same decoding namespace; the isGFX9Only predicate for the _SGPR_IMM case below makes it non-instruction in GFX8.

560

Yes, these are not needed for codegen needs and may only be useful for disassembling. Should we leave the TODOs be until we know for sure what to do with this?

llvm/test/MC/AMDGPU/gfx9_asm_smem.s

63

Agree, and so seem to do the other tests here. I don't mind to update them all, if that's the suggestion?

[dp]

llvm/lib/Target/AMDGPU/SMInstructions.td

544

So after this change disassembler will be unable to decode some legal GFX8 code, correct? I think this should be avoided. Would it be difficult to amend this patch with disassembler changes to avoid this breakage?

560

Let us see what other people here think. I'd have replaced TODOs with a description of limitations of the current design. But this is a matter of taste.

llvm/test/MC/AMDGPU/gfx9_asm_smem.s

63

The file has tests with s101, m0, etc for soffset so the coverage is sufficient. I suggest to correct one new test to use e.g. s1 instead of s0.

[kosarev]

llvm/lib/Target/AMDGPU/SMInstructions.td

544

As there is no soffset_en in GFX8, all codes with that bit raised are not what I guess you call legal GFX8 codes. I think we would never normally produce such codes for GFX8 from codegen or assembly, but as of the moment I'm not aware of any reasons to think that such codes are actually illegal or invalid. That is basically a disassembling issue again.

[kosarev]

Updated a test case to use a register that doesn't encode to 0.

[kosarev]

llvm/lib/Target/AMDGPU/SMInstructions.td

560

Tagging @foad @arsenm @rampitec for visibility.

Re replacing TODOs with descriptions: my only concern here would be to avoid masking what might be considered a real problem.

llvm/test/MC/AMDGPU/gfx9_asm_smem.s

63

Done.

Note that there are still lots of other MC tests and test cases where only s0 is used at a register position. And then on a more general note, I admit I struggle a bit to see the point in testing all possible combinations of what encoding-, diagnostics- and implementation-wise seems to be completely unrelated, such as immediate/register operands and glc modifiers, if that's the right example. Feels like removing unnecessary repetitions would make uncovered cases more visible, allow more combinations that we are truly interested in and maybe somewhat reduce testing times.

[dp]

llvm/lib/Target/AMDGPU/SMInstructions.td

544

You are right, this is a corner case which does not look that important. However there are third-party tools which may produce such codes, you never know. We should be able to disassemble such codes unless this requires a lot of additional work.

llvm/test/MC/AMDGPU/gfx9_asm_smem.s

63

The tests in this file have been generated by a script with the purpose of black box testing. The script did not generate all combinations of operands and modifiers, it attempted to provide at least one test for each operand kind and each modifier value. And yes, these tests are not perfect.

When working on a feature you do not have to mimic generated tests. Add a minimal set of tests which you feel would be sufficient for good coverage.

[kosarev]

llvm/lib/Target/AMDGPU/SMInstructions.td

544

Do we want to see it done as part of this patch? AFAIS, all the other notes are addressed.

[dp]

llvm/lib/Target/AMDGPU/SMInstructions.td

544

Probably a disassembler patch may be committed separately though I'd have preferred it as a part of this change.

[dp]

LGTM.

[foad]

llvm/lib/Target/AMDGPU/SMInstructions.td

560

I don't understand why these cases are not supported by the disassembler with the current patch. What happens if you try to disassemble them?

[kosarev]

llvm/lib/Target/AMDGPU/SMInstructions.td

560

It's being treated as non-instruction. Here's what I get for the example above:

; llvm-mc -filetype=obj -triple=amdgcn--amdpal -mcpu=tonga -show-encoding x.s | llvm-objdump -d --mcpu=tonga -
.text
  .long 0xc0024141, 0x00012345

0000000000000000 <.text>:
    .long 0xc0024141                                           // 000000000000: C0024141
    v_cndmask_b32_e32 v0, v69, v145, vcc                       // 000000000004: 00012345

I'm going to look into how subtarget predicates work for decoding facilities first and then as plan B maybe try something like opcode canonicalisation.

[kosarev]

Updated to support decoding GFX8 loads matching GFX9 encodings.

[kosarev]

llvm/lib/Target/AMDGPU/SMInstructions.td

544

From what I see in how the TableGen's decoder backend works, it's fine to have predicated patterns that are special cases of other more generic patterns, even if the latter are themselves differently predicated. So as long as we keep our isGFX9Only instructions to be special cases of isGFX8GFX9 ones, which I think we can expect being possible, disassembling should work for GFX8 as expected. For example, replacing the soffset_en expression with let Inst{14} = !if(!and(ps.has_offset, ps.has_soffset), 1, ?); resolves the decoding issue for the GFX8 instruction mentioned above.

Will update to support the GFX9 encodings for the _SGPR loads and add tests.

[kosarev]

Updated to support the alternative GFX9 encodings for the SGPR variants.

[kosarev]

llvm/lib/Target/AMDGPU/SMInstructions.td

544

Done. Please take a look.

llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

10086–10089

...which means SP3 sees what was previously mentioned as the second alternative SGPR encoding as the usual SGPR_IMM case, so no special handling is needed here.

[kosarev]

Clearing the approval as this needs another look.

[dp]

llvm/lib/Target/AMDGPU/SMInstructions.td

570

Now that we have IsGFX9Specific, could not this expression be replaced with '?'

587

Ingenious!

[kosarev]

Cleaned up the soffset field expression.

[kosarev]

llvm/lib/Target/AMDGPU/SMInstructions.td

570

Nice catch. Done.

587

The NonParsable bit, that's been borrowed from the Hexagon backend, so all the credit goes there!

[dp]

LGTM, thanks!

llvm/lib/Target/AMDGPU/SMInstructions.td

 defm S_BUFFER_LOAD_DWORDX8  : SM_Real_Loads_si <0x0b, "S_BUFFER_LOAD_DWORDX8">;
 defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_si <0x0c, "S_BUFFER_LOAD_DWORDX16">;
 
 def S_MEMTIME_si    : SMRD_Real_si <0x1e, S_MEMTIME>;
 def S_DCACHE_INV_si : SMRD_Real_si <0x1f, S_DCACHE_INV>;
 
 
 //===----------------------------------------------------------------------===//
-// VI
+// VI and GFX9.
 //===----------------------------------------------------------------------===//
 
 class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
   : SM_Real<ps>
   , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
   , Enc64 {
-  let AssemblerPredicate = isGFX8GFX9;
+  field bit IsGFX9Specific = false;
+  let AssemblerPredicate = !if(IsGFX9Specific, isGFX9Only, isGFX8GFX9);
   let DecoderNamespace = "GFX8";
 
   let Inst{5-0}   = !if(ps.has_sbase, sbase{6-1}, ?);
   let Inst{12-6}  = !if(ps.has_sdst, sdst{6-0}, ?);
 
+  // Note that for GFX9 instructions with immediate offsets, soffset_en
+  // must be defined, whereas in GFX8 it's undefined in all cases,
+  // meaning GFX9 is not perfectly backward-compatible with GFX8, despite
+  // documentation suggesting otherwise.
+  field bit SOffsetEn = !if(IsGFX9Specific,
+    !if(ps.has_offset, ps.has_soffset, !if(ps.has_soffset, 0, ?)),
+    ?);
+  let Inst{14} = SOffsetEn;
+
   let Inst{16} = !if(ps.has_glc, cpol{CPolBit.GLC}, ?);
+
+  // imm
+  // TODO: Shall not be defined if the instruction has no offset nor
+  // soffset.
   let Inst{17} = ps.has_offset;
+
   let Inst{25-18} = op;
   let Inst{31-26} = 0x30; //encoding
 
   // VI supports 20-bit unsigned offsets while GFX9+ supports 21-bit signed.
   // Offset value is corrected accordingly when offset is encoded/decoded.
-  let Inst{38-32} = !if(ps.has_offset, offset{6-0}, !if(ps.has_soffset, soffset{6-0}, ?));
-  let Inst{52-39} = !if(ps.has_offset, offset{20-7}, ?);
-}
-
-multiclass SM_Real_Loads_vi<bits<8> op, string ps,
-                            SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
-                            SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
-  def _IMM_vi : SMEM_Real_vi <op, immPs> {
-    let InOperandList = (ins immPs.BaseClass:$sbase, smem_offset:$offset, CPol:$cpol);
-  }
-  def _SGPR_vi : SMEM_Real_vi <op, sgprPs> {
-    let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$soffset, CPol:$cpol);
+  // TODO: Forbid non-M0 register offsets for GFX8 stores and atomics.
+  field bits<21> Offset;
+  let Offset{6-0} = !if(ps.has_offset, offset{6-0},
+                                       !if(ps.has_soffset, soffset{6-0}, ?));
+  let Offset{20-7} = !if(ps.has_offset, offset{20-7}, ?);
+  let Inst{52-32} = Offset;
+
+  // soffset
+  let Inst{63-57} = !if(IsGFX9Specific,
+    !if(ps.has_soffset, soffset{6-0}, ?),
+    !if(!and(ps.has_offset, ps.has_soffset), soffset{6-0}, ?));
+}
+
+class SMEM_Real_Load_vi<bits<8> op, string ps, dag offsets>
+    : SMEM_Real_vi<op, !cast<SM_Pseudo>(ps)> {
+  RegisterClass BaseClass = !cast<SM_Load_Pseudo>(ps).BaseClass;
+  let InOperandList = !con((ins BaseClass:$sbase), offsets, (ins CPol:$cpol));
+}
+
+multiclass SM_Real_Loads_vi<bits<8> op, string ps> {
+  def _IMM_vi : SMEM_Real_Load_vi <op, ps#"_IMM", (ins smem_offset:$offset)>;
+  def _SGPR_vi : SMEM_Real_Load_vi <op, ps#"_SGPR", (ins SReg_32:$soffset)>;
+  let IsGFX9Specific = true in {
+    // The alternative GFX9 SGPR encoding using soffset to encode the
+    // offset register. Not available in assembler and goes to the GFX9
+    // encoding family to avoid conflicts with the primary SGPR variant.
+    let SOffsetEn = 1, Offset = ?, Subtarget = SIEncodingFamily.GFX9,
+        AsmVariantName = "NonParsable" in
+    def _SGPR_alt_gfx9 : SMEM_Real_Load_vi <op, ps#"_SGPR",
+                                            (ins SReg_32:$soffset)>;
+    def _SGPR_IMM_gfx9 : SMEM_Real_Load_vi <
+      op, ps#"_SGPR_IMM", (ins SReg_32:$soffset, smem_offset_mod:$offset)>;
   }
 }
 
 class SMEM_Real_Store_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
   // encoding
   bits<7> sdata;
 
   let sdst = ?;

llvm/test/MC/AMDGPU/gfx9_asm_smem.s

 // CHECK: [0x41,0x01,0x00,0xc0,0x7b,0x00,0x00,0x00]
 
 s_load_dword s5, s[2:3], m0
 // CHECK: [0x41,0x01,0x00,0xc0,0x7c,0x00,0x00,0x00]
 
 s_load_dword s5, s[2:3], 0x0
 // CHECK: [0x41,0x01,0x02,0xc0,0x00,0x00,0x00,0x00]
 
+s_load_dword s5, s[2:3], s7 offset:0x12345
+// CHECK: [0x41,0x41,0x02,0xc0,0x45,0x23,0x01,0x0e]
+
 s_load_dword s5, s[2:3], s0 glc
 // CHECK: [0x41,0x01,0x01,0xc0,0x00,0x00,0x00,0x00]
 
 s_load_dwordx2 s[10:11], s[2:3], s0
 // CHECK: [0x81,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
 
 s_load_dwordx2 s[12:13], s[2:3], s0
 // CHECK: [0x01,0x03,0x04,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x81,0x02,0x04,0xc0,0x7b,0x00,0x00,0x00]
 
 s_load_dwordx2 s[10:11], s[2:3], m0
 // CHECK: [0x81,0x02,0x04,0xc0,0x7c,0x00,0x00,0x00]
 
 s_load_dwordx2 s[10:11], s[2:3], 0x0
 // CHECK: [0x81,0x02,0x06,0xc0,0x00,0x00,0x00,0x00]
 
+s_load_dwordx2 s[10:11], s[2:3], s0 offset:0x12345
+// CHECK: [0x81,0x42,0x06,0xc0,0x45,0x23,0x01,0x00]
+
 s_load_dwordx2 s[10:11], s[2:3], s0 glc
 // CHECK: [0x81,0x02,0x05,0xc0,0x00,0x00,0x00,0x00]
 
 s_load_dwordx4 s[20:23], s[2:3], s0
 // CHECK: [0x01,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
 
 s_load_dwordx4 s[24:27], s[2:3], s0
 // CHECK: [0x01,0x06,0x08,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x01,0x05,0x08,0xc0,0x7b,0x00,0x00,0x00]
 
 s_load_dwordx4 s[20:23], s[2:3], m0
 // CHECK: [0x01,0x05,0x08,0xc0,0x7c,0x00,0x00,0x00]
 
 s_load_dwordx4 s[20:23], s[2:3], 0x0
 // CHECK: [0x01,0x05,0x0a,0xc0,0x00,0x00,0x00,0x00]
 
+s_load_dwordx4 s[20:23], s[2:3], s0 offset:0x12345
+// CHECK: [0x01,0x45,0x0a,0xc0,0x45,0x23,0x01,0x00]
+
 s_load_dwordx4 s[20:23], s[2:3], s0 glc
 // CHECK: [0x01,0x05,0x09,0xc0,0x00,0x00,0x00,0x00]
 
 s_load_dwordx8 s[20:27], s[2:3], s0
 // CHECK: [0x01,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
 
 s_load_dwordx8 s[24:31], s[2:3], s0
 // CHECK: [0x01,0x06,0x0c,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x01,0x05,0x0c,0xc0,0x7b,0x00,0x00,0x00]
 
 s_load_dwordx8 s[20:27], s[2:3], m0
 // CHECK: [0x01,0x05,0x0c,0xc0,0x7c,0x00,0x00,0x00]
 
 s_load_dwordx8 s[20:27], s[2:3], 0x0
 // CHECK: [0x01,0x05,0x0e,0xc0,0x00,0x00,0x00,0x00]
 
+s_load_dwordx8 s[20:27], s[2:3], s0 offset:0x12345
+// CHECK: [0x01,0x45,0x0e,0xc0,0x45,0x23,0x01,0x00]
+
 s_load_dwordx8 s[20:27], s[2:3], s0 glc
 // CHECK: [0x01,0x05,0x0d,0xc0,0x00,0x00,0x00,0x00]
 
 s_load_dwordx16 s[20:35], s[2:3], s0
 // CHECK: [0x01,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
 
 s_load_dwordx16 s[24:39], s[2:3], s0
 // CHECK: [0x01,0x06,0x10,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x01,0x05,0x10,0xc0,0x7b,0x00,0x00,0x00]
 
 s_load_dwordx16 s[20:35], s[2:3], m0
 // CHECK: [0x01,0x05,0x10,0xc0,0x7c,0x00,0x00,0x00]
 
 s_load_dwordx16 s[20:35], s[2:3], 0x0
 // CHECK: [0x01,0x05,0x12,0xc0,0x00,0x00,0x00,0x00]
 
+s_load_dwordx16 s[20:35], s[2:3], s0 offset:0x12345
+// CHECK: [0x01,0x45,0x12,0xc0,0x45,0x23,0x01,0x00]
+
 s_load_dwordx16 s[20:35], s[2:3], s0 glc
 // CHECK: [0x01,0x05,0x11,0xc0,0x00,0x00,0x00,0x00]
 
 s_scratch_load_dword s5, s[2:3], s0
 // CHECK: [0x41,0x01,0x14,0xc0,0x00,0x00,0x00,0x00]
 
 s_scratch_load_dword s101, s[2:3], s0
 // CHECK: [0x41,0x19,0x14,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x41,0x01,0x14,0xc0,0x7b,0x00,0x00,0x00]
 
 s_scratch_load_dword s5, s[2:3], m0
 // CHECK: [0x41,0x01,0x14,0xc0,0x7c,0x00,0x00,0x00]
 
 s_scratch_load_dword s5, s[2:3], 0x0
 // CHECK: [0x41,0x01,0x16,0xc0,0x00,0x00,0x00,0x00]
 
+s_scratch_load_dword s5, s[2:3], s0 offset:0x12345
+// CHECK: [0x41,0x41,0x16,0xc0,0x45,0x23,0x01,0x00]
+
 s_scratch_load_dword s5, s[2:3], s0 glc
 // CHECK: [0x41,0x01,0x15,0xc0,0x00,0x00,0x00,0x00]
 
 s_scratch_load_dwordx2 s[10:11], s[2:3], s0
 // CHECK: [0x81,0x02,0x18,0xc0,0x00,0x00,0x00,0x00]
 
 s_scratch_load_dwordx2 s[12:13], s[2:3], s0
 // CHECK: [0x01,0x03,0x18,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x81,0x02,0x18,0xc0,0x7b,0x00,0x00,0x00]
 
 s_scratch_load_dwordx2 s[10:11], s[2:3], m0
 // CHECK: [0x81,0x02,0x18,0xc0,0x7c,0x00,0x00,0x00]
 
 s_scratch_load_dwordx2 s[10:11], s[2:3], 0x0
 // CHECK: [0x81,0x02,0x1a,0xc0,0x00,0x00,0x00,0x00]
 
+s_scratch_load_dwordx2 s[10:11], s[2:3], s0 offset:0x12345
+// CHECK: [0x81,0x42,0x1a,0xc0,0x45,0x23,0x01,0x00]
+
 s_scratch_load_dwordx2 s[10:11], s[2:3], s0 glc
 // CHECK: [0x81,0x02,0x19,0xc0,0x00,0x00,0x00,0x00]
 
 s_scratch_load_dwordx4 s[20:23], s[2:3], s0
 // CHECK: [0x01,0x05,0x1c,0xc0,0x00,0x00,0x00,0x00]
 
 s_scratch_load_dwordx4 s[24:27], s[2:3], s0
 // CHECK: [0x01,0x06,0x1c,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x01,0x05,0x1c,0xc0,0x7b,0x00,0x00,0x00]
 
 s_scratch_load_dwordx4 s[20:23], s[2:3], m0
 // CHECK: [0x01,0x05,0x1c,0xc0,0x7c,0x00,0x00,0x00]
 
 s_scratch_load_dwordx4 s[20:23], s[2:3], 0x0
 // CHECK: [0x01,0x05,0x1e,0xc0,0x00,0x00,0x00,0x00]
 
+s_scratch_load_dwordx4 s[20:23], s[2:3], s0 offset:0x12345
+// CHECK: [0x01,0x45,0x1e,0xc0,0x45,0x23,0x01,0x00]
+
 s_scratch_load_dwordx4 s[20:23], s[2:3], s0 glc
 // CHECK: [0x01,0x05,0x1d,0xc0,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dword s5, s[4:7], s0
 // CHECK: [0x42,0x01,0x20,0xc0,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dword s101, s[4:7], s0
 // CHECK: [0x42,0x19,0x20,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x42,0x01,0x20,0xc0,0x7b,0x00,0x00,0x00]
 
 s_buffer_load_dword s5, s[4:7], m0
 // CHECK: [0x42,0x01,0x20,0xc0,0x7c,0x00,0x00,0x00]
 
 s_buffer_load_dword s5, s[4:7], 0x0
 // CHECK: [0x42,0x01,0x22,0xc0,0x00,0x00,0x00,0x00]
 
+s_buffer_load_dword s5, s[4:7], s0 offset:0x12345
+// CHECK: [0x42,0x41,0x22,0xc0,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dword s5, s[4:7], s0 glc
 // CHECK: [0x42,0x01,0x21,0xc0,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx2 s[10:11], s[4:7], s0
 // CHECK: [0x82,0x02,0x24,0xc0,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx2 s[12:13], s[4:7], s0
 // CHECK: [0x02,0x03,0x24,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x82,0x02,0x24,0xc0,0x7b,0x00,0x00,0x00]
 
 s_buffer_load_dwordx2 s[10:11], s[4:7], m0
 // CHECK: [0x82,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
 
 s_buffer_load_dwordx2 s[10:11], s[4:7], 0x0
 // CHECK: [0x82,0x02,0x26,0xc0,0x00,0x00,0x00,0x00]
 
+s_buffer_load_dwordx2 s[10:11], s[4:7], s0 offset:0x12345
+// CHECK: [0x82,0x42,0x26,0xc0,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dwordx2 s[10:11], s[4:7], s0 glc
 // CHECK: [0x82,0x02,0x25,0xc0,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx4 s[20:23], s[4:7], s0
 // CHECK: [0x02,0x05,0x28,0xc0,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx4 s[24:27], s[4:7], s0
 // CHECK: [0x02,0x06,0x28,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x02,0x05,0x28,0xc0,0x7b,0x00,0x00,0x00]
 
 s_buffer_load_dwordx4 s[20:23], s[4:7], m0
 // CHECK: [0x02,0x05,0x28,0xc0,0x7c,0x00,0x00,0x00]
 
 s_buffer_load_dwordx4 s[20:23], s[4:7], 0x0
 // CHECK: [0x02,0x05,0x2a,0xc0,0x00,0x00,0x00,0x00]
 
+s_buffer_load_dwordx4 s[20:23], s[4:7], s0 offset:0x12345
+// CHECK: [0x02,0x45,0x2a,0xc0,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dwordx4 s[20:23], s[4:7], s0 glc
 // CHECK: [0x02,0x05,0x29,0xc0,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx8 s[20:27], s[4:7], s0
 // CHECK: [0x02,0x05,0x2c,0xc0,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx8 s[24:31], s[4:7], s0
 // CHECK: [0x02,0x06,0x2c,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x02,0x05,0x2c,0xc0,0x7b,0x00,0x00,0x00]
 
 s_buffer_load_dwordx8 s[20:27], s[4:7], m0
 // CHECK: [0x02,0x05,0x2c,0xc0,0x7c,0x00,0x00,0x00]
 
 s_buffer_load_dwordx8 s[20:27], s[4:7], 0x0
 // CHECK: [0x02,0x05,0x2e,0xc0,0x00,0x00,0x00,0x00]
 
+s_buffer_load_dwordx8 s[20:27], s[4:7], s0 offset:0x12345
+// CHECK: [0x02,0x45,0x2e,0xc0,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dwordx8 s[20:27], s[4:7], s0 glc
 // CHECK: [0x02,0x05,0x2d,0xc0,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx16 s[20:35], s[4:7], s0
 // CHECK: [0x02,0x05,0x30,0xc0,0x00,0x00,0x00,0x00]
 
 s_buffer_load_dwordx16 s[24:39], s[4:7], s0
 // CHECK: [0x02,0x06,0x30,0xc0,0x00,0x00,0x00,0x00]

 // CHECK: [0x02,0x05,0x30,0xc0,0x7b,0x00,0x00,0x00]
 
 s_buffer_load_dwordx16 s[20:35], s[4:7], m0
 // CHECK: [0x02,0x05,0x30,0xc0,0x7c,0x00,0x00,0x00]
 
 s_buffer_load_dwordx16 s[20:35], s[4:7], 0x0
 // CHECK: [0x02,0x05,0x32,0xc0,0x00,0x00,0x00,0x00]
 
+s_buffer_load_dwordx16 s[20:35], s[4:7], s0 offset:0x12345
+// CHECK: [0x02,0x45,0x32,0xc0,0x45,0x23,0x01,0x00]
+
 s_buffer_load_dwordx16 s[20:35], s[4:7], s0 glc
 // CHECK: [0x02,0x05,0x31,0xc0,0x00,0x00,0x00,0x00]
 
 s_store_dword s1, s[4:5], s0
 // CHECK: [0x42,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
 
 s_store_dword s101, s[4:5], s0
 // CHECK: [0x42,0x19,0x40,0xc0,0x00,0x00,0x00,0x00]

llvm/test/MC/AMDGPU/smem.s

 s_atc_probe_buffer 0x1, s[8:11], 0x1FFFFF
 // NOSICI: error: instruction not supported on this GPU
 // NOGFX9GFX10: error: expected a 20-bit unsigned offset
 // NOVI: error: expected a 20-bit unsigned offset
 
 s_load_dword s1, s[2:3], s0 offset:0x1FFFFF
 // NOSICI: error: operands are not valid for this GPU or mode
 // NOVI: error: operands are not valid for this GPU or mode
-// NOGFX9: error: operands are not valid for this GPU or mode
+// NOGFX9: error: expected a 21-bit signed offset
 // NOGFX10: error: expected a 21-bit signed offset
 
 s_store_dword s1, s[2:3], 0x1FFFFF
 // NOSICIGFX1030: error: instruction not supported on this GPU
 // NOGFX9GFX1012: error: expected a 21-bit signed offset
 // NOVI: error: expected a 20-bit unsigned offset
 
 s_buffer_load_dword s10, s[92:95], s0 offset:-1
 // NOSICI: error: operands are not valid for this GPU or mode
 // NOVI: error: operands are not valid for this GPU or mode
-// NOGFX9: error: operands are not valid for this GPU or mode
+// NOGFX9: error: expected a 20-bit unsigned offset
 // NOGFX10: error: expected a 20-bit unsigned offset
 
 s_buffer_store_dword s10, s[92:95], 0x1FFFFF
 // NOSICIGFX1030: error: instruction not supported on this GPU
 // NOGFX9GFX1012: error: expected a 20-bit unsigned offset
 // NOVI: error: expected a 20-bit unsigned offset
 
 s_atomic_swap s5, s[2:3], 0x1FFFFF

llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt

 0x77,0x01,0x00,0xc0,0x02,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, ttmp[10:11], s2        ; encoding: [0x7d,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
 0x7d,0x01,0x00,0xc0,0x02,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, s[2:3], s101           ; encoding: [0x41,0x01,0x00,0xc0,0x65,0x00,0x00,0x00]
 0x41,0x01,0x00,0xc0,0x65,0x00,0x00,0x00
 
+# Make sure that raising the GFX9 soffset_en bit doesn't affect GFX8
+# decoding.
+# CHECK: s_load_dword s5, s[2:3], s101           ; encoding: [0x41,0x01,0x00,0xc0,0x65,0x00,0x00,0x00]
+0x41,0x41,0x00,0xc0,0x65,0x00,0x00,0x00
+
 # CHECK: s_load_dword s5, s[2:3], flat_scratch_lo ; encoding: [0x41,0x01,0x00,0xc0,0x66,0x00,0x00,0x00]
 0x41,0x01,0x00,0xc0,0x66,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, s[2:3], flat_scratch_hi ; encoding: [0x41,0x01,0x00,0xc0,0x67,0x00,0x00,0x00]
 0x41,0x01,0x00,0xc0,0x67,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, s[2:3], vcc_lo         ; encoding: [0x41,0x01,0x00,0xc0,0x6a,0x00,0x00,0x00]
 0x41,0x01,0x00,0xc0,0x6a,0x00,0x00,0x00

 0x41,0x01,0x00,0xc0,0x7b,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, s[2:3], m0             ; encoding: [0x41,0x01,0x00,0xc0,0x7c,0x00,0x00,0x00]
 0x41,0x01,0x00,0xc0,0x7c,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, s[2:3], 0x7ffff        ; encoding: [0x41,0x01,0x02,0xc0,0xff,0xff,0x07,0x00]
 0x41,0x01,0x02,0xc0,0xff,0xff,0x07,0x00
 
+# Make sure that raising the GFX9 soffset_en bit doesn't affect GFX8
+# decoding.
+# CHECK: s_load_dword s5, s[2:3], 0x7ffff        ; encoding: [0x41,0x01,0x02,0xc0,0xff,0xff,0x07,0x00]
+0x41,0x41,0x02,0xc0,0xff,0xff,0x07,0x00
+
 # CHECK: s_load_dword s5, s[2:3], s2 glc         ; encoding: [0x41,0x01,0x01,0xc0,0x02,0x00,0x00,0x00]
 0x41,0x01,0x01,0xc0,0x02,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx2 s[10:11], s[2:3], s2     ; encoding: [0x81,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
 0x81,0x02,0x04,0xc0,0x02,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx2 s[12:13], s[2:3], s2     ; encoding: [0x01,0x03,0x04,0xc0,0x02,0x00,0x00,0x00]
 0x01,0x03,0x04,0xc0,0x02,0x00,0x00,0x00

llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

 0x73,0x01,0x00,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, vcc, s0                ; encoding: [0x75,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
 0x75,0x01,0x00,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, s[2:3], s101           ; encoding: [0x41,0x01,0x00,0xc0,0x65,0x00,0x00,0x00]
 0x41,0x01,0x00,0xc0,0x65,0x00,0x00,0x00
 
+# The SGRP variants can alternatively be encoded with imm=0, soffset_en=1
+# and the offset register encoded in the soffset field with the offset
+# field being disregarded.
+# CHECK: s_load_dword s5, s[2:3], s64            ; encoding: [0x41,0x41,0x00,0xc0,0x00,0x00,0x00,0x80]
+0x41,0x41,0x00,0xc0,0x65,0x00,0x00,0x80
+
 # CHECK: s_load_dword s5, s[2:3], flat_scratch_lo ; encoding: [0x41,0x01,0x00,0xc0,0x66,0x00,0x00,0x00]
 0x41,0x01,0x00,0xc0,0x66,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, s[2:3], flat_scratch_hi ; encoding: [0x41,0x01,0x00,0xc0,0x67,0x00,0x00,0x00]
 0x41,0x01,0x00,0xc0,0x67,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, s[2:3], vcc_lo         ; encoding: [0x41,0x01,0x00,0xc0,0x6a,0x00,0x00,0x00]
 0x41,0x01,0x00,0xc0,0x6a,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, s[2:3], vcc_hi         ; encoding: [0x41,0x01,0x00,0xc0,0x6b,0x00,0x00,0x00]
 0x41,0x01,0x00,0xc0,0x6b,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, s[2:3], m0             ; encoding: [0x41,0x01,0x00,0xc0,0x7c,0x00,0x00,0x00]
 0x41,0x01,0x00,0xc0,0x7c,0x00,0x00,0x00
 
 # CHECK: s_load_dword s5, s[2:3], 0x0            ; encoding: [0x41,0x01,0x02,0xc0,0x00,0x00,0x00,0x00]
 0x41,0x01,0x02,0xc0,0x00,0x00,0x00,0x00
 
+# CHECK: s_load_dword s5, s[2:3], s0 offset:0x12345 ; encoding: [0x41,0x41,0x02,0xc0,0x45,0x23,0x01,0x00]
+0x41,0x41,0x02,0xc0,0x45,0x23,0x01,0x00
+
+# SP3 prefers to decode instructions with imm=1 and soffset_en=1 to the
+# form with the 'offset:' modifier, even if the offset is 0.
+# CHECK: s_load_dword s5, s[2:3], s0 offset:0x0  ; encoding: [0x41,0x41,0x02,0xc0,0x00,0x00,0x00,0x00]
+0x41,0x41,0x02,0xc0,0x00,0x00,0x00,0x00
+
 # CHECK: s_load_dword s5, s[2:3], s0 glc         ; encoding: [0x41,0x01,0x01,0xc0,0x00,0x00,0x00,0x00]
 0x41,0x01,0x01,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx2 s[10:11], s[2:3], s0     ; encoding: [0x81,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
 0x81,0x02,0x04,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx2 s[12:13], s[2:3], s0     ; encoding: [0x01,0x03,0x04,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x03,0x04,0xc0,0x00,0x00,0x00,0x00

 0x81,0x02,0x04,0xc0,0x6b,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx2 s[10:11], s[2:3], m0     ; encoding: [0x81,0x02,0x04,0xc0,0x7c,0x00,0x00,0x00]
 0x81,0x02,0x04,0xc0,0x7c,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx2 s[10:11], s[2:3], 0x0    ; encoding: [0x81,0x02,0x06,0xc0,0x00,0x00,0x00,0x00]
 0x81,0x02,0x06,0xc0,0x00,0x00,0x00,0x00
 
+# CHECK: s_load_dwordx2 s[10:11], s[2:3], s0 offset:0x12345 ; encoding: [0x81,0x42,0x06,0xc0,0x45,0x23,0x01,0x00]
+0x81,0x42,0x06,0xc0,0x45,0x23,0x01,0x00
+
 # CHECK: s_load_dwordx2 s[10:11], s[2:3], s0 glc ; encoding: [0x81,0x02,0x05,0xc0,0x00,0x00,0x00,0x00]
 0x81,0x02,0x05,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx4 s[20:23], s[2:3], s0     ; encoding: [0x01,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x05,0x08,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx4 s[24:27], s[2:3], s0     ; encoding: [0x01,0x06,0x08,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x06,0x08,0xc0,0x00,0x00,0x00,0x00

 0x01,0x05,0x08,0xc0,0x6b,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx4 s[20:23], s[2:3], m0     ; encoding: [0x01,0x05,0x08,0xc0,0x7c,0x00,0x00,0x00]
 0x01,0x05,0x08,0xc0,0x7c,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx4 s[20:23], s[2:3], 0x0    ; encoding: [0x01,0x05,0x0a,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x05,0x0a,0xc0,0x00,0x00,0x00,0x00
 
+# CHECK: s_load_dwordx4 s[20:23], s[2:3], s0 offset:0x12345 ; encoding: [0x01,0x45,0x0a,0xc0,0x45,0x23,0x01,0x00]
+0x01,0x45,0x0a,0xc0,0x45,0x23,0x01,0x00
+
 # CHECK: s_load_dwordx4 s[20:23], s[2:3], s0 glc ; encoding: [0x01,0x05,0x09,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x05,0x09,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx8 s[20:27], s[2:3], s0     ; encoding: [0x01,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx8 s[24:31], s[2:3], s0     ; encoding: [0x01,0x06,0x0c,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x06,0x0c,0xc0,0x00,0x00,0x00,0x00

 0x01,0x05,0x0c,0xc0,0x6b,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx8 s[20:27], s[2:3], m0     ; encoding: [0x01,0x05,0x0c,0xc0,0x7c,0x00,0x00,0x00]
 0x01,0x05,0x0c,0xc0,0x7c,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx8 s[20:27], s[2:3], 0x0    ; encoding: [0x01,0x05,0x0e,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x05,0x0e,0xc0,0x00,0x00,0x00,0x00
 
+# CHECK: s_load_dwordx8 s[20:27], s[2:3], s0 offset:0x12345 ; encoding: [0x01,0x45,0x0e,0xc0,0x45,0x23,0x01,0x00]
+0x01,0x45,0x0e,0xc0,0x45,0x23,0x01,0x00
+
 # CHECK: s_load_dwordx8 s[20:27], s[2:3], s0 glc ; encoding: [0x01,0x05,0x0d,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x05,0x0d,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx16 s[20:35], s[2:3], s0    ; encoding: [0x01,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x05,0x10,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx16 s[24:39], s[2:3], s0    ; encoding: [0x01,0x06,0x10,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x06,0x10,0xc0,0x00,0x00,0x00,0x00

 0x01,0x05,0x10,0xc0,0x6b,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx16 s[20:35], s[2:3], m0    ; encoding: [0x01,0x05,0x10,0xc0,0x7c,0x00,0x00,0x00]
 0x01,0x05,0x10,0xc0,0x7c,0x00,0x00,0x00
 
 # CHECK: s_load_dwordx16 s[20:35], s[2:3], 0x0   ; encoding: [0x01,0x05,0x12,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x05,0x12,0xc0,0x00,0x00,0x00,0x00
 
+# CHECK: s_load_dwordx16 s[20:35], s[2:3], s0 offset:0x12345 ; encoding: [0x01,0x45,0x12,0xc0,0x45,0x23,0x01,0x00]
+0x01,0x45,0x12,0xc0,0x45,0x23,0x01,0x00
+
 # CHECK: s_load_dwordx16 s[20:35], s[2:3], s0 glc ; encoding: [0x01,0x05,0x11,0xc0,0x00,0x00,0x00,0x00]
 0x01,0x05,0x11,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dword s5, s[4:7], s0      ; encoding: [0x42,0x01,0x20,0xc0,0x00,0x00,0x00,0x00]
 0x42,0x01,0x20,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dword s101, s[4:7], s0    ; encoding: [0x42,0x19,0x20,0xc0,0x00,0x00,0x00,0x00]
 0x42,0x19,0x20,0xc0,0x00,0x00,0x00,0x00

 0x42,0x01,0x20,0xc0,0x6b,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dword s5, s[4:7], m0      ; encoding: [0x42,0x01,0x20,0xc0,0x7c,0x00,0x00,0x00]
 0x42,0x01,0x20,0xc0,0x7c,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dword s5, s[4:7], 0x0     ; encoding: [0x42,0x01,0x22,0xc0,0x00,0x00,0x00,0x00]
 0x42,0x01,0x22,0xc0,0x00,0x00,0x00,0x00
 
+# CHECK: s_buffer_load_dword s5, s[4:7], s0 offset:0x12345 ; encoding: [0x42,0x41,0x22,0xc0,0x45,0x23,0x01,0x00]
+0x42,0x41,0x22,0xc0,0x45,0x23,0x01,0x00
+
 # CHECK: s_buffer_load_dword s5, s[4:7], s0 glc  ; encoding: [0x42,0x01,0x21,0xc0,0x00,0x00,0x00,0x00]
 0x42,0x01,0x21,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx2 s[10:11], s[4:7], s0 ; encoding: [0x82,0x02,0x24,0xc0,0x00,0x00,0x00,0x00]
 0x82,0x02,0x24,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx2 s[12:13], s[4:7], s0 ; encoding: [0x02,0x03,0x24,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x03,0x24,0xc0,0x00,0x00,0x00,0x00

 0x82,0x02,0x24,0xc0,0x6b,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx2 s[10:11], s[4:7], m0 ; encoding: [0x82,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
 0x82,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx2 s[10:11], s[4:7], 0x0 ; encoding: [0x82,0x02,0x26,0xc0,0x00,0x00,0x00,0x00]
 0x82,0x02,0x26,0xc0,0x00,0x00,0x00,0x00
 
+# CHECK: s_buffer_load_dwordx2 s[10:11], s[4:7], s0 offset:0x12345 ; encoding: [0x82,0x42,0x26,0xc0,0x45,0x23,0x01,0x00]
+0x82,0x42,0x26,0xc0,0x45,0x23,0x01,0x00
+
 # CHECK: s_buffer_load_dwordx2 s[10:11], s[4:7], s0 glc ; encoding: [0x82,0x02,0x25,0xc0,0x00,0x00,0x00,0x00]
 0x82,0x02,0x25,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx4 s[20:23], s[4:7], s0 ; encoding: [0x02,0x05,0x28,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x05,0x28,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx4 s[24:27], s[4:7], s0 ; encoding: [0x02,0x06,0x28,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x06,0x28,0xc0,0x00,0x00,0x00,0x00

 0x02,0x05,0x28,0xc0,0x6b,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx4 s[20:23], s[4:7], m0 ; encoding: [0x02,0x05,0x28,0xc0,0x7c,0x00,0x00,0x00]
 0x02,0x05,0x28,0xc0,0x7c,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx4 s[20:23], s[4:7], 0x0 ; encoding: [0x02,0x05,0x2a,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x05,0x2a,0xc0,0x00,0x00,0x00,0x00
 
+# CHECK: s_buffer_load_dwordx4 s[20:23], s[4:7], s0 offset:0x12345 ; encoding: [0x02,0x45,0x2a,0xc0,0x45,0x23,0x01,0x00]
+0x02,0x45,0x2a,0xc0,0x45,0x23,0x01,0x00
+
 # CHECK: s_buffer_load_dwordx4 s[20:23], s[4:7], s0 glc ; encoding: [0x02,0x05,0x29,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x05,0x29,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx8 s[20:27], s[4:7], s0 ; encoding: [0x02,0x05,0x2c,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x05,0x2c,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx8 s[24:31], s[4:7], s0 ; encoding: [0x02,0x06,0x2c,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x06,0x2c,0xc0,0x00,0x00,0x00,0x00

 0x02,0x05,0x2c,0xc0,0x6b,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx8 s[20:27], s[4:7], m0 ; encoding: [0x02,0x05,0x2c,0xc0,0x7c,0x00,0x00,0x00]
 0x02,0x05,0x2c,0xc0,0x7c,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx8 s[20:27], s[4:7], 0x0 ; encoding: [0x02,0x05,0x2e,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x05,0x2e,0xc0,0x00,0x00,0x00,0x00
 
+# CHECK: s_buffer_load_dwordx8 s[20:27], s[4:7], s0 offset:0x12345 ; encoding: [0x02,0x45,0x2e,0xc0,0x45,0x23,0x01,0x00]
+0x02,0x45,0x2e,0xc0,0x45,0x23,0x01,0x00
+
 # CHECK: s_buffer_load_dwordx8 s[20:27], s[4:7], s0 glc ; encoding: [0x02,0x05,0x2d,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x05,0x2d,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx16 s[20:35], s[4:7], s0 ; encoding: [0x02,0x05,0x30,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x05,0x30,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx16 s[24:39], s[4:7], s0 ; encoding: [0x02,0x06,0x30,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x06,0x30,0xc0,0x00,0x00,0x00,0x00

 0x02,0x05,0x30,0xc0,0x6b,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx16 s[20:35], s[4:7], m0 ; encoding: [0x02,0x05,0x30,0xc0,0x7c,0x00,0x00,0x00]
 0x02,0x05,0x30,0xc0,0x7c,0x00,0x00,0x00
 
 # CHECK: s_buffer_load_dwordx16 s[20:35], s[4:7], 0x0 ; encoding: [0x02,0x05,0x32,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x05,0x32,0xc0,0x00,0x00,0x00,0x00
 
+# CHECK: s_buffer_load_dwordx16 s[20:35], s[4:7], s0 offset:0x12345 ; encoding: [0x02,0x45,0x32,0xc0,0x45,0x23,0x01,0x00]
+0x02,0x45,0x32,0xc0,0x45,0x23,0x01,0x00
+
 # CHECK: s_buffer_load_dwordx16 s[20:35], s[4:7], s0 glc ; encoding: [0x02,0x05,0x31,0xc0,0x00,0x00,0x00,0x00]
 0x02,0x05,0x31,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_store_dword s1, s[4:5], s0            ; encoding: [0x42,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
 0x42,0x00,0x40,0xc0,0x00,0x00,0x00,0x00
 
 # CHECK: s_store_dword s101, s[4:5], s0          ; encoding: [0x42,0x19,0x40,0xc0,0x00,0x00,0x00,0x00]
 0x42,0x19,0x40,0xc0,0x00,0x00,0x00,0x00