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Differential D125539

[AMDGPU][GlobalISel] Pre-commit tests for D125516
ClosedPublic

Authored by abinavpp on May 13 2022, 4:27 AM.

Details

Reviewers
aemerson
arsenm
foad
paquette
Commits
rGf96d20450c00: [AMDGPU][GlobalISel] Pre-commit tests for D125516

Diff Detail

Unit TestsFailed

TimeTest
60,290 msx64 debian > Clang.Driver::fsanitize.c
60,120 msx64 debian > Clang.OpenMP::target_teams_distribute_parallel_for_simd_codegen_registration.cpp

Event Timeline

abinavpp created this revision.May 13 2022, 4:27 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 13 2022, 4:28 AM
Herald added subscribers: kosarev, kerbowa, t-tye and 6 others. · View Herald Transcript
abinavpp requested review of this revision.May 13 2022, 4:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 13 2022, 4:28 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
abinavpp added a child revision: D125516: [GlobalISel] Handle constant splat in funnel shift combine.May 13 2022, 4:30 AM
foad accepted this revision.May 13 2022, 5:14 AM
This revision is now accepted and ready to land.May 13 2022, 5:14 AM
Harbormaster completed remote builds in B164286: Diff 429199.May 13 2022, 6:09 AM
This revision was landed with ongoing or failed builds.May 16 2022, 3:37 AM
Closed by commit rGf96d20450c00: [AMDGPU][GlobalISel] Pre-commit tests for D125516 (authored by abinavpp). · Explain Why
This revision was automatically updated to reflect the committed changes.
abinavpp added a commit: rGf96d20450c00: [AMDGPU][GlobalISel] Pre-commit tests for D125516.

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
GlobalISel/
32 lines
30 lines

Diff 429199

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines bb.0:
%amt1:_(s32) = G_CONSTANT i32 12 %amt1:_(s32) = G_CONSTANT i32 12
%shl:_(s32) = G_SHL %a, %amt0 %shl:_(s32) = G_SHL %a, %amt0
%lshr:_(s32) = G_LSHR %b, %amt1 %lshr:_(s32) = G_LSHR %b, %amt1
%or:_(s32) = G_OR %shl, %lshr %or:_(s32) = G_OR %shl, %lshr
$vgpr2 = COPY %or $vgpr2 = COPY %or
... ...
--- ---
name: fsh_v2i32_const
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-LABEL: name: fsh_v2i32_const
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %b:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK-NEXT: %scalar_amt0:_(s32) = G_CONSTANT i32 20
; CHECK-NEXT: %amt0:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt0(s32), %scalar_amt0(s32)
; CHECK-NEXT: %scalar_amt1:_(s32) = G_CONSTANT i32 12
; CHECK-NEXT: %amt1:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt1(s32), %scalar_amt1(s32)
; CHECK-NEXT: %shl:_(<2 x s32>) = G_SHL %a, %amt0(<2 x s32>)
; CHECK-NEXT: %lshr:_(<2 x s32>) = G_LSHR %b, %amt1(<2 x s32>)
; CHECK-NEXT: %or:_(<2 x s32>) = G_OR %shl, %lshr
; CHECK-NEXT: $vgpr4_vgpr5 = COPY %or(<2 x s32>)
%a:_(<2 x s32>) = COPY $vgpr0_vgpr1
%b:_(<2 x s32>) = COPY $vgpr2_vgpr3
%scalar_amt0:_(s32) = G_CONSTANT i32 20
%amt0:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt0, %scalar_amt0
%scalar_amt1:_(s32) = G_CONSTANT i32 12
%amt1:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt1, %scalar_amt1
%shl:_(<2 x s32>) = G_SHL %a, %amt0
%lshr:_(<2 x s32>) = G_LSHR %b, %amt1
%or:_(<2 x s32>) = G_OR %shl, %lshr
$vgpr4_vgpr5 = COPY %or
...
---
name: fsh_i32_bad_const name: fsh_i32_bad_const
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2 liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: fsh_i32_bad_const ; CHECK-LABEL: name: fsh_i32_bad_const
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir

Show First 20 Lines • Show All 116 Lines • ▼ Show 20 Lines bb.0:
%amt1:_(s32) = G_CONSTANT i32 12 %amt1:_(s32) = G_CONSTANT i32 12
%shl:_(s32) = G_SHL %a, %amt0 %shl:_(s32) = G_SHL %a, %amt0
%lshr:_(s32) = G_LSHR %a, %amt1 %lshr:_(s32) = G_LSHR %a, %amt1
%or:_(s32) = G_OR %shl, %lshr %or:_(s32) = G_OR %shl, %lshr
$vgpr1 = COPY %or $vgpr1 = COPY %or
... ...
--- ---
name: rot_v2i32_const
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: rot_v2i32_const
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %a:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: %scalar_amt0:_(s32) = G_CONSTANT i32 20
; CHECK-NEXT: %amt0:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt0(s32), %scalar_amt0(s32)
; CHECK-NEXT: %scalar_amt1:_(s32) = G_CONSTANT i32 12
; CHECK-NEXT: %amt1:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt1(s32), %scalar_amt1(s32)
; CHECK-NEXT: %shl:_(<2 x s32>) = G_SHL %a, %amt0(<2 x s32>)
; CHECK-NEXT: %lshr:_(<2 x s32>) = G_LSHR %a, %amt1(<2 x s32>)
; CHECK-NEXT: %or:_(<2 x s32>) = G_OR %shl, %lshr
; CHECK-NEXT: $vgpr2_vgpr3 = COPY %or(<2 x s32>)
%a:_(<2 x s32>) = COPY $vgpr0_vgpr1
%scalar_amt0:_(s32) = G_CONSTANT i32 20
%amt0:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt0, %scalar_amt0
%scalar_amt1:_(s32) = G_CONSTANT i32 12
%amt1:_(<2 x s32>) = G_BUILD_VECTOR %scalar_amt1, %scalar_amt1
%shl:_(<2 x s32>) = G_SHL %a, %amt0
%lshr:_(<2 x s32>) = G_LSHR %a, %amt1
%or:_(<2 x s32>) = G_OR %shl, %lshr
$vgpr2_vgpr3 = COPY %or
...
---
name: rot_i32_bad_const name: rot_i32_bad_const
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: rot_i32_bad_const ; CHECK-LABEL: name: rot_i32_bad_const
; CHECK: liveins: $vgpr0, $vgpr1 ; CHECK: liveins: $vgpr0, $vgpr1
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines