[BOLT][NFC] Suppress unused variable warnings

[Amir]

Summary

Address warnings in Release build without assertions.
Tip @tschuett for reporting the issue #55404.

[rafauler]

LGTM

bolt/lib/Core/BinaryFunction.cpp

 std::string mutateDWARFExpressionTargetReg(const MCCFIInstruction &Instr,
                                            MCPhysReg NewReg) {
   StringRef ExprBytes = Instr.getValues();
   assert(ExprBytes.size() > 1 && "DWARF expression CFI is too short");
   uint8_t Opcode = ExprBytes[0];
   assert((Opcode == dwarf::DW_CFA_expression ||
           Opcode == dwarf::DW_CFA_val_expression) &&
          "invalid DWARF expression CFI");
+  (void)Opcode;
   const uint8_t *const Start =
       reinterpret_cast<const uint8_t *>(ExprBytes.drop_front(1).data());
   const uint8_t *const End =
       reinterpret_cast<const uint8_t *>(Start + ExprBytes.size() - 1);
   unsigned Size = 0;
   decodeULEB128(Start, &Size, End);
   assert(Size > 0 && "Invalid reg encoding for DWARF expression CFI");
   SmallString<8> Tmp;
MIB->replaceImmWithSymbolRef(LoadHiBits, TargetSymbol, Addend, Ctx.get(),
                                  Val, ELF::R_AARCH64_ADR_PREL_PG_HI21);
     MIB->replaceImmWithSymbolRef(LoadLowBits, TargetSymbol, Addend, Ctx.get(),
                                  Val, ELF::R_AARCH64_ADD_ABS_LO12_NC);
   };
 
   auto handleExternalReference = [&](MCInst &Instruction, uint64_t Size,
                                      uint64_t Offset, uint64_t TargetAddress,
                                      bool &IsCall) -> MCSymbol * {
-    const bool IsCondBranch = MIB->isConditionalBranch(Instruction);
     const uint64_t AbsoluteInstrAddr = getAddress() + Offset;
     MCSymbol *TargetSymbol = nullptr;
     InterproceduralReferences.insert(TargetAddress);
     if (opts::Verbosity >= 2 && !IsCall && Size == 2 && !BC.HasRelocations) {
       errs() << "BOLT-WARNING: relaxed tail call detected at 0x"
              << Twine::utohexstr(AbsoluteInstrAddr) << " in function " << *this
              << ". Code size will be increased.\n";
     }
 
     assert(!MIB->isTailCall(Instruction) &&
            "synthetic tail call instruction found");
 
     // This is a call regardless of the opcode.
     // Assign proper opcode for tail calls, so that they could be
     // treated as calls.
     if (!IsCall) {
       if (!MIB->convertJmpToTailCall(Instruction)) {
-        assert(IsCondBranch && "unknown tail call instruction");
+        assert(MIB->isConditionalBranch(Instruction) &&
+               "unknown tail call instruction");
         if (opts::Verbosity >= 2) {
           errs() << "BOLT-WARNING: conditional tail call detected in "
                  << "function " << *this << " at 0x"
                  << Twine::utohexstr(AbsoluteInstrAddr) << ".\n";
         }
       }
       IsCall = true;
     }

bolt/lib/Core/DebugData.cpp

if (Patch.LocList.empty()) {
         DebugInfoPatcher.addLE32Patch(Patch.AttrOffset, EntryOffset);
 
       writeEmptyListDwarf5(*LocBodyStream);
       continue;
     }
 
     assert(Patch.Index == DebugLoclistWriter::InvalidIndex ||
            Patch.Index == Index++ && "Gap in LocList Index Array.");
+    (void)Index;
 
     std::vector<uint64_t> OffsetsArray;
     for (const DebugLocationEntry &Entry : Patch.LocList) {
       support::endian::write(*LocBodyStream,
                              static_cast<uint8_t>(dwarf::DW_LLE_startx_length),
                              support::little);
       const uint32_t Index = AddrWriter->getIndexFromAddress(Entry.LowPC, CU);
       encodeULEB128(Index, *LocBodyStream);

bolt/lib/Passes/RegReAssign.cpp

if (RegScore[Candidate] > (ScoreRBX + 10))
       RBX = I;
   }
 
   if (!RBX)
     return false;
 
   LLVM_DEBUG(dbgs() << "\n ** Swapping " << BC.MRI->getName(RBX) << " with "
                     << BC.MRI->getName(Candidate) << "\n\n");
+  (void)BC;
   swap(Function, RBX, Candidate);
   FuncsChanged.insert(&Function);
   return true;
 }
 
 void RegReAssign::setupAggressivePass(BinaryContext &BC,
                                       std::map<uint64_t, BinaryFunction> &BFs) {
   setupConservativePass(BC, BFs);

bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp

for (InstructionIterator It = Begin; It != End; ++It) {
       AdrpPC += InstSize;
     }
 
     // Get adrp value
     uint64_t Base;
     assert(Adrp->getOperand(1).isImm() && "Unexpected adrp operand");
     bool Ret = evaluateMemOperandTarget(*Adrp, Base, AdrpPC, InstSize);
     assert(Ret && "Failed to evaluate adrp");
+    (void)Ret;
 
     return Base + Offset;
   }
 
   unsigned getInvertedBranchOpcode(unsigned Opcode) const {
     switch (Opcode) {
     default:
       llvm_unreachable("Failed to invert branch opcode");

bolt/lib/Target/X86/X86MCPlusBuilder.cpp

bool convertTailCallToCall(MCInst &Inst) override {
 
     Inst.setOpcode(NewOpcode);
     removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall);
     return true;
   }
 
   bool convertCallToIndirectCall(MCInst &Inst, const MCSymbol *TargetLocation,
                                  MCContext *Ctx) override {
-    bool IsTailCall = isTailCall(Inst);
     assert((Inst.getOpcode() == X86::CALL64pcrel32 ||
-            (Inst.getOpcode() == X86::JMP_4 && IsTailCall)) &&
+            (Inst.getOpcode() == X86::JMP_4 && isTailCall(Inst))) &&
            "64-bit direct (tail) call instruction expected");
     const auto NewOpcode =
         (Inst.getOpcode() == X86::CALL64pcrel32) ? X86::CALL64m : X86::JMP32m;
     Inst.setOpcode(NewOpcode);
 
     // Replace the first operand and preserve auxiliary operands of
     // the instruction.
     Inst.erase(Inst.begin());