[X86] Fix 80 column violation in X86InstrInfo.cpp. NFC

[craig.topper]

That title is misleading. I expected a large patch formatting the whole file and making lots of changes.

Something like "[X86] Fix 80 column violation in X86InstrInfo.cpp. NFC" would be more precise.

llvm/lib/Target/X86/X86InstrInfo.cpp

1051–1052

"directly" is misspelled here

[mingmingl]

Fix a typo

[craig.topper]

LGTM

[mingmingl]

Reopen to update commit message (https://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20220509/1036412.html)

llvm/lib/Target/X86/X86InstrInfo.cpp

if (X86::isAND(VregDefInstr->getOpcode())) {
     //
     // However, the implementation artifically sets `NoSignFlag` to true
     // to poison the SF bit; that is to say, if SF is looked at later, the
     // optimization (to erase TEST64rr) will be disabled.
     //
     // The reason to poison SF bit is that SF bit value could be different
     // in the `AND` and `TEST` operation; signed bit is not known for `AND`,
     // and is known to be 0 as a result of `TEST64rr`.
     //
-    // FIXME: As opposed to poisoning the SF bit direclty, consider peeking into
-    // the AND instruction and using the static information to guide peephole optimization if possible.
-    // For example, it's possible to fold a conditional move into a copy
-    // if the relevant EFLAG bits could be deduced from an immediate operand of and operation.
-    // 
+    // FIXME: As opposed to poisoning the SF bit directly, consider peeking into
+    // the AND instruction and using the static information to guide peephole
+    // optimization if possible. For example, it's possible to fold a
+    // conditional move into a copy if the relevant EFLAG bits could be deduced
+    // from an immediate operand of and operation.
+    //
     NoSignFlag = true;
     // ClearsOverflowFlag is true for AND operation (no surprise).
     ClearsOverflowFlag = true;
     return true;
   }
   return false;
 }