[SelectionDAG] Constant fold (sext_inreg undef, VT) to 0 instead of undef.

[craig.topper]

Summary

The result of sign_extend_inreg needs to have as many sign bits
as requested by the VT argument. The easiest way to guarantee this
is to fold it to 0.

Fixes https://github.com/llvm/llvm-project/issues/55178

Not sure if the SystemZ test is still testing the same thing it
was before.

[RKSimon]

llvm/test/CodeGen/AArch64/pr55178.ll

20

worth pre-commiting with the broken codegen?

[craig.topper]

Rebase on pre-committed test

[RKSimon]

LGTM - but not sure if you want to wait for a SystemZ expert

[uweigand]

Not sure if the SystemZ test is still testing the same thing it was before.

@qcolombet I think you added this test case - any comments?

FYI @jonpa

[craig.topper]

Replace undef with an argument in SystemZ test. Undef operands are a bad idea.

I have verified that reverting the change from https://www.llvm.org/PR46154
hits the original assertion failure on the modified test. That is the patch
that added the test. So I think it is still a valid test with this change.

[uweigand]

SystemZ test change LGTM, thanks!

[RKSimon]

LGTM

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

if (SDValue SV = FoldConstantArithmetic(Opcode, DL, VT, {N1, N2}))
     return SV;
 
   // Canonicalize an UNDEF to the RHS, even over a constant.
   if (N1.isUndef()) {
     if (TLI->isCommutativeBinOp(Opcode)) {
       std::swap(N1, N2);
     } else {
       switch (Opcode) {
-      case ISD::SIGN_EXTEND_INREG:
       case ISD::SUB:
         return getUNDEF(VT);     // fold op(undef, arg2) -> undef
+      case ISD::SIGN_EXTEND_INREG:
       case ISD::UDIV:
       case ISD::SDIV:
       case ISD::UREM:
       case ISD::SREM:
       case ISD::SSUBSAT:
       case ISD::USUBSAT:
         return getConstant(0, DL, VT);    // fold op(undef, arg2) -> 0
       }

llvm/test/CodeGen/AArch64/pr55178.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s
 
 ; This used to generate incorrect code because we sign extended
 ; the undef to undef instead of to 0.
 
 define i1 @test14(i8 %X) {
 ; CHECK-LABEL: test14:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #-113
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
 ; CHECK-NEXT:    lsl w8, w8, w0
-; CHECK-NEXT:    cmp w8, w8, sxtb
-; CHECK-NEXT:    cset w0, lt
+; CHECK-NEXT:    sxtb w8, w8
+; CHECK-NEXT:    cmp w8, #0
+; CHECK-NEXT:    cset w0, gt
 ; CHECK-NEXT:    ret
   %1 = shl i8 -113, %X
   %cmp = icmp slt i8 undef, %1
   ret i1 %cmp
 }

llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -O3 -pre-RA-sched=list-ilp -systemz-subreg-liveness -stress-sched -terminal-rule %s -o - | FileCheck %s
 ; This test used to fail because we were creating empty subranges
 ; instead of subranges with dead defs while rematerializing values
 ; during coalescing.
 ;
 ; PR46154
 ; REQUIRES: asserts
 
 @g_39 = external dso_local unnamed_addr global i64, align 8
 @g_151 = external dso_local global i32, align 4
 @g_222 = external dso_local unnamed_addr global [7 x [10 x i8]], align 2
 
-define void @main() {
+define void @main(i16 %in) {
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lhi %r0, 1
+; CHECK-NEXT:    lhr %r2, %r2
 ; CHECK-NEXT:    larl %r1, g_151
 ; CHECK-NEXT:    lghi %r3, 0
-; CHECK-NEXT:    chi %r0, 0
+; CHECK-NEXT:    chi %r2, 0
+; CHECK-NEXT:    lhi %r0, 1
 ; CHECK-NEXT:    locghile %r3, 1
 ; CHECK-NEXT:    o %r0, 0(%r1)
-; CHECK-NEXT:    dsgfr %r2, %r0
 ; CHECK-NEXT:    larl %r1, g_222
 ; CHECK-NEXT:    lghi %r5, 0
+; CHECK-NEXT:    dsgfr %r2, %r0
 ; CHECK-NEXT:    stgrl %r2, g_39
 ; CHECK-NEXT:    stc %r5, 19(%r1)
 ; CHECK-NEXT:    br %r14
   %tmp = load i32, i32* @g_151, align 4
   %tmp3 = or i32 %tmp, 1
   %tmp4 = sext i32 %tmp3 to i64
   %tmp5 = srem i64 0, %tmp4
   %tmp6 = trunc i64 %tmp5 to i8
   store i8 %tmp6, i8* getelementptr inbounds ([7 x [10 x i8]], [7 x [10 x i8]]* @g_222, i64 0, i64 1, i64 9), align 1
-  %tmp7 = icmp slt i16 undef, 1
+  %tmp7 = icmp slt i16 %in, 1
   %tmp8 = zext i1 %tmp7 to i64
   %tmp9 = srem i64 %tmp8, %tmp4
   store i64 %tmp9, i64* @g_39, align 8
   ret void
 }