[AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0.

[ab]

Summary

This matches the ARM behavior. However, here the lowering isn't guarded
by a "PerfMon" feature: while it is indeed optional on AArch64 as well,
all of the CPUs we support have it, so why pretend.

[jmolloy]

Hi Ahmed,

I'd really prefer this to be predicated on a new feature. I'm happy for the feature to be enabled by default though.

Cheers,

James

lib/Target/AArch64/AArch64ISelLowering.cpp

405

I'd really prefer that this is predicated on a feature.

[ab]

Fair enough; here's an updated patch.

[jmolloy]

Thanks for making that change Ahmed, LGTM.

James

[salvatoredipietro]

Hi @ab,
I was checking this code and I believe that it would be better for the readcyclecounter function to use the CNTVCT_EL0 register (Counter-timer Virtual Count register) instead of the PMCCNTR_EL0 (Performance Monitors Cycle Count Register) because the current one is a PMU register which, depending on PMU configuration, it might always return zeroes and it doesn't guaranteed to always be increased.

lib/Target/AArch64/AArch64ISelLowering.cpp

for (MVT Ty : {MVT::f32, MVT::f64}) {
     setOperationAction(ISD::FMINNUM, Ty, Legal);
     setOperationAction(ISD::FMAXNUM, Ty, Legal);
     setOperationAction(ISD::FMINNAN, Ty, Legal);
     setOperationAction(ISD::FMAXNAN, Ty, Legal);
   }
 
   setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
 
+  // Lower READCYCLECOUNTER using an mrs from PMCCNTR_EL0.
+  // Technically, this requires the Performance Monitors (optional) extension,
+  // but all of the A-class CPUs we support have it.
+  setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
+
   if (Subtarget->isTargetMachO()) {
     // For iOS, we don't want to the normal expansion of a libcall to
     // sincos. We want to issue a libcall to __sincos_stret to avoid memory
     // traffic.
     setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
     setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
   } else {
     setOperationAction(ISD::FSINCOS, MVT::f64, Expand);

lib/Target/AArch64/AArch64InstrInfo.td

 def MRS    : MRSI;
 def MSR    : MSRI;
 def MSRpstate: MSRpstateI;
 
 // The thread pointer (on Linux, at least, where this has been implemented) is
 // TPIDR_EL0.
 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
 
+// The cycle counter PMC register is PMCCNTR_EL0.
+def : Pat<(readcyclecounter), (MRS 0xdce8)>;
+
 // Generic system instructions
 def SYSxt  : SystemXtI<0, "sys">;
 def SYSLxt : SystemLXtI<1, "sysl">;
 
 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
                 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
                  sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
 

test/CodeGen/AArch64/readcyclecounter.ll

+; RUN: llc -mtriple=arm64-unknown-unknown -asm-verbose=false < %s | FileCheck %s
+
+define i64 @test_readcyclecounter() nounwind {
+  ; CHECK-LABEL: test_readcyclecounter:
+  ; CHECK-NEXT: mrs x0, PMCCNTR_EL0
+  ; CHECK-NEXT: ret
+  %tmp0 = call i64 @llvm.readcyclecounter()
+  ret i64 %tmp0
+}
+
+declare i64 @llvm.readcyclecounter()