[AMDGPU][NFC] Organize code around reserving VGPR32 for AGPR copy.

[hsmhsm]

Summary

This is an NFC patch in preparation to fix a bug related to always
reserving VGPR32 for AGPR copy.

[cdevadas]

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

497

No need for the initializer. It takes NoRegister by default.

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

702

I don't think it's the right place to reserve the VGPR by changing the constness of MFI.
May be finalizeLowering?

[hsmhsm]

Fix few review comments by CD.

[hsmhsm]

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

702

Actually, it may not work in case of mir lit tests which may not call finalizeLowering(), but may call getReservedRegs().

Nevertheless it is not a good idea to remove constness and mutate const object. For now, since it an NFC patch, and which actually just refactor the code around reserving VGPR for AGPR copy, let me not add code to mutate const object.

And, in the next subsequent patch, let me think if we can handle it better.

[hsmhsm]

Minor update to member initialization.

[rampitec]

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

1560

There is already assert inside getVGPRForAGPRCopy.

[hsmhsm]

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

1560

The assert inside getVGPRForAGPRCopy() is to assert that some valid VGPR (only in case of gfx908) is identified, which may or may not yet reserved (by calling getReservedRegs()).

On the other hand, the assert here assert that the identified valid VGPR is also reserved.

[hsmhsm]

Fix assert message.

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

static void indirectCopyToAGPR(const SIInstrInfo &TII,
   // Ideally we want to have three registers for a long reg_sequence copy
   // to hide 2 waitstates between v_mov_b32 and accvgpr_write.
   unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
                                              *MBB.getParent());
 
   // Registers in the sequence are allocated contiguously so we can just
   // use register number to pick one of three round-robin temps.
   unsigned RegNo = DestReg % 3;
-  Register Tmp = AMDGPU::VGPR32;
+  Register Tmp =
+      MBB.getParent()->getInfo<SIMachineFunctionInfo>()->getVGPRForAGPRCopy();
   assert(MBB.getParent()->getRegInfo().isReserved(Tmp) &&
          "VGPR used for an intermediate copy should have been reserved.");
 
   // Only loop through if there are any free registers left, otherwise
   // scavenger may report a fatal error without emergency spill slot
   // or spill with the slot.
   while (RegNo-- && RS.FindUnusedReg(&AMDGPU::VGPR_32RegClass)) {
     Register Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

private:
 
   // VGPRs used for AGPR spills.
   SmallVector<MCPhysReg, 32> SpillVGPR;
 
   // Emergency stack slot. Sometimes, we create this before finalizing the stack
   // frame, so save it here and add it to the RegScavenger later.
   Optional<int> ScavengeFI;
 
+private:
+  Register VGPRForAGPRCopy = AMDGPU::NoRegister;
+
+public:
+  Register getVGPRForAGPRCopy() const {
+    assert(VGPRForAGPRCopy &&
+           "Valid VGPR for AGPR copy must have been reserved by now");
+    return VGPRForAGPRCopy;
+  }
+
+  Register reserveVGPRForAGPRCopy(const unsigned HighestAvailableVGPR) {
+    if (VGPRForAGPRCopy)
+      return VGPRForAGPRCopy;
+
+    VGPRForAGPRCopy = AMDGPU::VGPR_32RegClass.getRegister(32);
+
+    return VGPRForAGPRCopy;
+  }
+
 public: // FIXME
   /// If this is set, an SGPR used for save/restore of the register used for the
   /// frame pointer.
   Register SGPRForFPSaveRestoreCopy;
   Optional<int> FramePointerSaveIndex;
 
   /// If this is set, an SGPR used for save/restore of the register used for the
   /// base pointer.

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   for (unsigned i = MaxNumAGPRs; i < TotalNumVGPRs; ++i) {
     unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
     reserveRegisterTuples(Reserved, Reg);
   }
 
   // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
   // VGPR available at all times.
   if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
-    reserveRegisterTuples(Reserved, AMDGPU::VGPR32);
+    auto reservedVGPR =
+        const_cast<SIMachineFunctionInfo *>(MFI)->reserveVGPRForAGPRCopy(
+            MaxNumVGPRs - 1);
+    reserveRegisterTuples(Reserved, reservedVGPR);
   }
 
   for (auto Reg : MFI->WWMReservedRegs) {
     reserveRegisterTuples(Reserved, Reg.first);
   }
 
   // FIXME: Stop using reserved registers for this.
   for (MCPhysReg Reg : MFI->getAGPRSpillVGPRs())
for (unsigned i = 0, e = NumSubRegs + NumRemSubRegs, RegOffset = 0; i != e;
     }
 
     unsigned FinalReg = SubReg;
 
     if (IsAGPR) {
       assert(EltSize == 4);
 
       if (!TmpIntermediateVGPR) {
-        assert(MF->getRegInfo().isReserved(AMDGPU::VGPR32));
-        TmpIntermediateVGPR = AMDGPU::VGPR32;
+        TmpIntermediateVGPR = FuncInfo->getVGPRForAGPRCopy();
+        assert(MF->getRegInfo().isReserved(TmpIntermediateVGPR));
       }
       if (IsStore) {
         auto AccRead = BuildMI(MBB, MI, DL,
                                TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64),
                                TmpIntermediateVGPR)
                            .addReg(SubReg, getKillRegState(IsKill));
         if (NeedSuperRegDef)
           AccRead.addReg(ValueReg, RegState::ImplicitDefine);