[AMDGPU][GFX10] Corrected v_add_nc_u16 and v_sub_nc_u16 to enable op_sel

[dp]

Summary

A fix for bug 54119.

[arsenm]

LGTM. Can you open a new issue to try to codegen to use this?

[dp]

In D123594#3445404, @arsenm wrote:

Can you open a new issue to try to codegen to use this?

Opened a new issue 54869.

llvm/lib/Target/AMDGPU/VOP2Instructions.td

 defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
 defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, any_fmul>;
 
 let mayRaiseFPException = 0 in {
 def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">;
 }
 
 } // End FPDPRounding = 1
-defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;
-defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>;
-defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">;
 defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>;
 defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>;
 defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>;
 defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>;
 defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>;
 defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>;
 defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>;
 
+let SubtargetPredicate = isGFX8GFX9 in {
+  defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;
+  defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>;
+  defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">;
+}
+
 let Constraints = "$vdst = $src2", DisableEncoding="$src2",
     isConvertibleToThreeAddress = 1 in {
 defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
 }
 } // End isCommutable = 1
 
 } // End SubtargetPredicate = Has16BitInsts
 

 >;
 
 def : GCNPat <
   (xor vt:$src0, vt:$src1),
   (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
 >;
 }
 
-let Predicates = [Has16BitInsts] in {
+let Predicates = [Has16BitInsts, isGFX8GFX9] in {
 
 // Undo sub x, c -> add x, -c canonicalization since c is more likely
 // an inline immediate than -c.
 // TODO: Also do for 64-bit.
 def : GCNPat<
   (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),
   (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
 >;
 
-
-let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {
-
 def : GCNPat<
   (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))),
   (V_SUB_U16_e64 VSrc_b16:$src0, NegSubInlineIntConst16:$src1)
 >;
 
 defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>;
 defm : Arithmetic_i16_0Hi_Pats<mul, V_MUL_LO_U16_e64>;
 defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>;
 defm : Arithmetic_i16_0Hi_Pats<smin, V_MIN_I16_e64>;
 defm : Arithmetic_i16_0Hi_Pats<smax, V_MAX_I16_e64>;
 defm : Arithmetic_i16_0Hi_Pats<umin, V_MIN_U16_e64>;
 defm : Arithmetic_i16_0Hi_Pats<umax, V_MAX_U16_e64>;
 defm : Arithmetic_i16_0Hi_Pats<clshl_rev_16, V_LSHLREV_B16_e64>;
 defm : Arithmetic_i16_0Hi_Pats<clshr_rev_16, V_LSHRREV_B16_e64>;
 defm : Arithmetic_i16_0Hi_Pats<cashr_rev_16, V_ASHRREV_I16_e64>;
-}  // End Predicates = [Has16BitInsts, isGFX7GFX8GFX9]
+
+}  // End Predicates = [Has16BitInsts, isGFX8GFX9]
+
+let Predicates = [Has16BitInsts] in {
 
 def : ZExt_i16_i1_Pat<zext>;
 def : ZExt_i16_i1_Pat<anyext>;
 
 def : GCNPat <
   (i16 (sext i1:$src)),
   (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
                      /*src1mod*/(i32 0), /*src1*/(i32 -1), $src)

llvm/lib/Target/AMDGPU/VOP3Instructions.td

let SubtargetPredicate = isGFX10Plus in {
   def : PermlanePat<int_amdgcn_permlanex16, V_PERMLANEX16_B32_e64>;
 
   def : PermlaneDiscardVDstIn<
     BoundControlOrFetchInvalidPermlane<int_amdgcn_permlane16>,
     V_PERMLANE16_B32_e64>;
   def : PermlaneDiscardVDstIn<
     BoundControlOrFetchInvalidPermlane<int_amdgcn_permlanex16>,
     V_PERMLANEX16_B32_e64>;
+
+  defm V_ADD_NC_U16 : VOP3Inst <"v_add_nc_u16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>, add>;
+  defm V_SUB_NC_U16 : VOP3Inst <"v_sub_nc_u16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>, sub>;
+
+  def : OpSelBinOpClampPat<uaddsat, V_ADD_NC_U16_e64>;
+  def : OpSelBinOpClampPat<usubsat, V_SUB_NC_U16_e64>;
+
+  // Undo sub x, c -> add x, -c canonicalization since c is more likely
+  // an inline immediate than -c.
+  def : GCNPat<
+    (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),
+    (V_SUB_NC_U16_e64 0, VSrc_b16:$src0, 0, NegSubInlineIntConst16:$src1, 0, 0)
+  >;
+
 } // End SubtargetPredicate = isGFX10Plus
 
 class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat<
   (AMDGPUdiv_fmas (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
                   (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)),
                   (vt (VOP3Mods vt:$src2, i32:$src2_modifiers)),
                   (i1 CondReg)),
   (inst $src0_modifiers, $src0, $src1_modifiers, $src1, $src2_modifiers, $src2)
defm V_MAD_U16 :
   VOP3OpSel_Real_gfx10_with_name<0x340, "V_MAD_U16_gfx9", "v_mad_u16">;
 defm V_FMA_F16 :
   VOP3OpSel_Real_gfx10_with_name<0x34b, "V_FMA_F16_gfx9", "v_fma_f16">;
 defm V_MAD_I16 :
   VOP3OpSel_Real_gfx10_with_name<0x35e, "V_MAD_I16_gfx9", "v_mad_i16">;
 defm V_DIV_FIXUP_F16 :
   VOP3OpSel_Real_gfx10_with_name<0x35f, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">;
 
+defm V_ADD_NC_U16      : VOP3OpSel_Real_gfx10<0x303>;
+defm V_SUB_NC_U16      : VOP3OpSel_Real_gfx10<0x304>;
+
 // FIXME-GFX10-OPSEL: Need to add "selective" opsel support to some of these
 // (they do not support SDWA or DPP).
-defm V_ADD_NC_U16      : VOP3_Real_gfx10_with_name<0x303, "V_ADD_U16", "v_add_nc_u16">;
-defm V_SUB_NC_U16      : VOP3_Real_gfx10_with_name<0x304, "V_SUB_U16", "v_sub_nc_u16">;
 defm V_MUL_LO_U16      : VOP3_Real_gfx10_with_name<0x305, "V_MUL_LO_U16", "v_mul_lo_u16">;
 defm V_LSHRREV_B16     : VOP3_Real_gfx10_with_name<0x307, "V_LSHRREV_B16", "v_lshrrev_b16">;
 defm V_ASHRREV_I16     : VOP3_Real_gfx10_with_name<0x308, "V_ASHRREV_I16", "v_ashrrev_i16">;
 defm V_MAX_U16         : VOP3_Real_gfx10_with_name<0x309, "V_MAX_U16", "v_max_u16">;
 defm V_MAX_I16         : VOP3_Real_gfx10_with_name<0x30a, "V_MAX_I16", "v_max_i16">;
 defm V_MIN_U16         : VOP3_Real_gfx10_with_name<0x30b, "V_MIN_U16", "v_min_u16">;
 defm V_MIN_I16         : VOP3_Real_gfx10_with_name<0x30c, "V_MIN_I16", "v_min_i16">;
 defm V_LSHLREV_B16     : VOP3_Real_gfx10_with_name<0x314, "V_LSHLREV_B16", "v_lshlrev_b16">;

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir

bb.0:
     ; GFX6-LABEL: name: add_s16
     ; GFX6: liveins: $vgpr0, $vgpr1
     ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
     ; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
     ; GFX10-LABEL: name: add_s16
     ; GFX10: liveins: $vgpr0, $vgpr1
-    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-    ; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
-    ; GFX10: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
+    ; GFX10-NEXT: {{  $}}
+    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; GFX10-NEXT: [[V_ADD_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ADD_NC_U16_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = COPY $vgpr1
     %2:vgpr(s16) = G_TRUNC %0
     %3:vgpr(s16) = G_TRUNC %1
     %4:vgpr(s16) = G_ADD %2, %3
     S_ENDPGM 0, implicit %4
 
 ...
bb.0:
     ; GFX6-LABEL: name: add_s16_zext_to_s32
     ; GFX6: liveins: $vgpr0, $vgpr1
     ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
     ; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
     ; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
     ; GFX10-LABEL: name: add_s16_zext_to_s32
     ; GFX10: liveins: $vgpr0, $vgpr1
-    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
-    ; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
-    ; GFX10: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[V_ADD_U16_e64_]], 0, 16, implicit $exec
-    ; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
+    ; GFX10-NEXT: {{  $}}
+    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; GFX10-NEXT: [[V_ADD_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+    ; GFX10-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[V_ADD_NC_U16_e64_]], 0, 16, implicit $exec
+    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = COPY $vgpr1
     %2:vgpr(s16) = G_TRUNC %0
     %3:vgpr(s16) = G_TRUNC %1
     %4:vgpr(s16) = G_ADD %2, %3
     %5:vgpr(s32) = G_ZEXT %4
     S_ENDPGM 0, implicit %5
 
bb.0:
 
     ; GFX6-LABEL: name: add_s16_neg_inline_const_64
     ; GFX6: liveins: $vgpr0
     ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
     ; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
     ; GFX10-LABEL: name: add_s16_neg_inline_const_64
     ; GFX10: liveins: $vgpr0
-    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
-    ; GFX10: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
+    ; GFX10-NEXT: {{  $}}
+    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX10-NEXT: [[V_SUB_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_NC_U16_e64 0, [[COPY]], 0, 64, 0, 0, implicit $exec
+    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_SUB_NC_U16_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_CONSTANT i16 -64
     %3:vgpr(s16) = G_ADD %1, %2
     S_ENDPGM 0, implicit %3
 
 ...
 
bb.0:
 
     ; GFX6-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
     ; GFX6: liveins: $vgpr0
     ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
     ; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
     ; GFX10-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
     ; GFX10: liveins: $vgpr0
-    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
-    ; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
-    ; GFX10: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[V_SUB_U16_e64_]], 0, 16, implicit $exec
-    ; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
+    ; GFX10-NEXT: {{  $}}
+    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX10-NEXT: [[V_SUB_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_NC_U16_e64 0, [[COPY]], 0, 64, 0, 0, implicit $exec
+    ; GFX10-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[V_SUB_NC_U16_e64_]], 0, 16, implicit $exec
+    ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_CONSTANT i16 -64
     %3:vgpr(s16) = G_ADD %1, %2
     %4:vgpr(s32) = G_ZEXT %3
     S_ENDPGM 0, implicit %4
 
 ...

llvm/test/MC/AMDGPU/gfx10_asm_vop3.s

 // GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
 
 v_add_nc_u16 v5, v1, -4.0
 // GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 
 v_add_nc_u16 v5, v1, -4.0 clamp
 // GFX10: encoding: [0x05,0x80,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 
+v_add_nc_u16 v5, v1, v2 op_sel:[1,1,1]
+// GFX10: [0x05,0x58,0x03,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_u16 v5, v1, v2 op_sel:[0,0,0]
+// GFX10: [0x05,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_u16 v5, v1, v2 op_sel:[1,0,0]
+// GFX10: [0x05,0x08,0x03,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_u16 v5, v1, v2 op_sel:[0,1,0]
+// GFX10: [0x05,0x10,0x03,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_u16 v5, v1, v2 op_sel:[0,0,1]
+// GFX10: [0x05,0x40,0x03,0xd7,0x01,0x05,0x02,0x00]
+
 v_sub_nc_u16 v5, v1, v2
 // GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
 
 v_sub_nc_u16 v255, v1, v2
 // GFX10: encoding: [0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
 
 v_sub_nc_u16 v5, v255, v2
 // GFX10: encoding: [0x05,0x00,0x04,0xd7,0xff,0x05,0x02,0x00]

 // GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
 
 v_sub_nc_u16 v5, v1, -4.0
 // GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 
 v_sub_nc_u16 v5, v1, -4.0 clamp
 // GFX10: encoding: [0x05,0x80,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 
+v_sub_nc_u16 v5, v1, v2 op_sel:[1,1,1]
+// GFX10: [0x05,0x58,0x04,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_u16 v5, v1, v2 op_sel:[0,0,0]
+// GFX10: [0x05,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_u16 v5, v1, v2 op_sel:[1,0,0]
+// GFX10: [0x05,0x08,0x04,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_u16 v5, v1, v2 op_sel:[0,1,0]
+// GFX10: [0x05,0x10,0x04,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_u16 v5, v1, v2 op_sel:[0,0,1]
+// GFX10: [0x05,0x40,0x04,0xd7,0x01,0x05,0x02,0x00]
+
 v_mul_lo_u16 v5, v1, v2
 // GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
 
 v_mul_lo_u16 v255, v1, v2
 // GFX10: encoding: [0xff,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
 
 v_mul_lo_u16 v5, v255, v2
 // GFX10: encoding: [0x05,0x00,0x05,0xd7,0xff,0x05,0x02,0x00]

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

 0x05,0x00,0x03,0xd7,0x6b,0x04,0x02,0x00
 
 # GFX10: v_add_nc_u16 v5, vcc_lo, v2             ; encoding: [0x05,0x00,0x03,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x03,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_add_nc_u16 v5, vcc_lo, v2 clamp       ; encoding: [0x05,0x80,0x03,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x80,0x03,0xd7,0x6a,0x04,0x02,0x00
 
+# GFX10: v_add_nc_u16 v5, v1, v2 op_sel:[1,1,1]  ; encoding: [0x05,0x58,0x03,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x58,0x03,0xd7,0x01,0x05,0x02,0x00
+
+# GFX10: v_add_nc_u16 v5, v1, v2 op_sel:[1,0,0]  ; encoding: [0x05,0x08,0x03,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x08,0x03,0xd7,0x01,0x05,0x02,0x00
+
+# GFX10: v_add_nc_u16 v5, v1, v2 op_sel:[0,1,0]  ; encoding: [0x05,0x10,0x03,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x10,0x03,0xd7,0x01,0x05,0x02,0x00
+
+# GFX10: v_add_nc_u16 v5, v1, v2 op_sel:[0,0,1]  ; encoding: [0x05,0x40,0x03,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x40,0x03,0xd7,0x01,0x05,0x02,0x00
+
 # GFX10: v_add_nc_u32_e32 v255, v1, v2           ; encoding: [0x01,0x05,0xfe,0x4b]
 0x01,0x05,0xfe,0x4b
 
 # GFX10: v_add_nc_u32_e32 v5, -1, v2             ; encoding: [0xc1,0x04,0x0a,0x4a]
 0xc1,0x04,0x0a,0x4a
 
 # GFX10: v_add_nc_u32_e32 v5, -4.0, v2           ; encoding: [0xf7,0x04,0x0a,0x4a]
 0xf7,0x04,0x0a,0x4a

 0x05,0x00,0x04,0xd7,0x6b,0x04,0x02,0x00
 
 # GFX10: v_sub_nc_u16 v5, vcc_lo, v2             ; encoding: [0x05,0x00,0x04,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x04,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_sub_nc_u16 v5, vcc_lo, v2 clamp       ; encoding: [0x05,0x80,0x04,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x80,0x04,0xd7,0x6a,0x04,0x02,0x00
 
+# GFX10: v_sub_nc_u16 v5, v1, v2 op_sel:[1,1,1]  ; encoding: [0x05,0x58,0x04,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x58,0x04,0xd7,0x01,0x05,0x02,0x00
+
+# GFX10: v_sub_nc_u16 v5, v1, v2 op_sel:[1,0,0]  ; encoding: [0x05,0x08,0x04,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x08,0x04,0xd7,0x01,0x05,0x02,0x00
+
+# GFX10: v_sub_nc_u16 v5, v1, v2 op_sel:[0,1,0]  ; encoding: [0x05,0x10,0x04,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x10,0x04,0xd7,0x01,0x05,0x02,0x00
+
+# GFX10: v_sub_nc_u16 v5, v1, v2 op_sel:[0,0,1]  ; encoding: [0x05,0x40,0x04,0xd7,0x01,0x05,0x02,0x00]
+0x05,0x40,0x04,0xd7,0x01,0x05,0x02,0x00
+
 # GFX10: v_sub_nc_u32_e32 v255, v1, v2           ; encoding: [0x01,0x05,0xfe,0x4d]
 0x01,0x05,0xfe,0x4d
 
 # GFX10: v_sub_nc_u32_e32 v5, -1, v2             ; encoding: [0xc1,0x04,0x0a,0x4c]
 0xc1,0x04,0x0a,0x4c
 
 # GFX10: v_sub_nc_u32_e32 v5, -4.0, v2           ; encoding: [0xf7,0x04,0x0a,0x4c]
 0xf7,0x04,0x0a,0x4c