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Differential D123355

[RISCV][NFC] Refactor patterns for Multiply Add instructions
ClosedPublic

Authored by Jimerlife on Apr 7 2022, 8:30 PM.

Details

Reviewers
craig.topper
frasercrmck
benshi001
Commits
rG38706dd94014: [RISCV][NFC] Refactor patterns for Multiply Add instructions
Summary

Refactor patterns for Multiply Add instructions

Diff Detail

Event Timeline

Jimerlife created this revision.Apr 7 2022, 8:30 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 7 2022, 8:30 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 29 others. · View Herald Transcript
Jimerlife requested review of this revision.Apr 7 2022, 8:30 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD and 2 others. · View Herald TranscriptApr 7 2022, 8:30 PM
Harbormaster completed remote builds in B158614: Diff 421397.Apr 7 2022, 9:23 PM
Jimerlife updated this revision to Diff 421849.Apr 11 2022, 1:49 AM

update

Harbormaster completed remote builds in B158957: Diff 421849.Apr 11 2022, 2:33 AM
frasercrmck added inline comments.Apr 12 2022, 9:57 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
1068

We're losing the wti in wti.RegClass:$rd, vti.RegClass:$rs1 here by moving to VPatWidenMultiplyAddVL_VV_VX. I'm not sure why this isn't an error.

craig.topper added inline comments.Apr 12 2022, 10:01 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
1068

Doesn't VPatWidenMultiplyAddVL_VV_VX also use wti.RegClass:$rd, vti.RegClass:$rs1?

frasercrmck added inline comments.Apr 12 2022, 10:03 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
1068

Oh dear, yes of course. I think I was looking at VPatMultiplyAddVL_VV_VX by mistake.

craig.topper added a comment.Apr 12 2022, 10:11 AM

LGTM, but I'll let Fraser also approve.

frasercrmck accepted this revision.Apr 13 2022, 12:04 AM

LGTM too, thanks for the cleanup

This revision is now accepted and ready to land.Apr 13 2022, 12:04 AM
Jimerlife added inline comments.Apr 13 2022, 1:08 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
1068

VPatWidenMultiplyAddVL_VV_VX also used wti.RegClass:$rd, vti.RegClass:$rs1

This revision was landed with ongoing or failed builds.Apr 14 2022, 1:15 AM
Closed by commit rG38706dd94014: [RISCV][NFC] Refactor patterns for Multiply Add instructions (authored by Jimerlife). · Explain Why
This revision was automatically updated to reflect the committed changes.
Jimerlife added a commit: rG38706dd94014: [RISCV][NFC] Refactor patterns for Multiply Add instructions.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
52 lines
158 lines

Diff 422761

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 531 Lines • ▼ Show 20 Lines def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))),
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)), (fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
wti.RegClass:$rd), wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
} }
} }
multiclass VPatMultiplyAddSDNode_VV_VX<SDNode op, string instruction_name> {
foreach vti = AllIntegerVectors in {
defvar suffix = vti.LMul.MX;
// NOTE: We choose VMADD because it has the most commuting freedom. So it
// works best with how TwoAddressInstructionPass tries commuting.
def : Pat<(vti.Vector (op vti.RegClass:$rs2,
(mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))),
(!cast<Instruction>(instruction_name#"_VV_"# suffix)
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
// The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally
// commutable.
def : Pat<(vti.Vector (op vti.RegClass:$rs2,
(mul_oneuse (SplatPat XLenVT:$rs1), vti.RegClass:$rd))),
(!cast<Instruction>(instruction_name#"_VX_" # suffix)
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Patterns. // Patterns.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasVInstructions] in { let Predicates = [HasVInstructions] in {
// 7.4. Vector Unit-Stride Instructions // 7.4. Vector Unit-Stride Instructions
foreach vti = !listconcat(FractionalGroupIntegerVectors, foreach vti = !listconcat(FractionalGroupIntegerVectors,
▲ Show 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
defm : VPatWidenBinarySDNode_VV_VX<mul, zext_oneuse, anyext_oneuse, defm : VPatWidenBinarySDNode_VV_VX<mul, zext_oneuse, anyext_oneuse,
"PseudoVWMULU">; "PseudoVWMULU">;
defm : VPatWidenBinarySDNode_VV_VX<mul, sext_oneuse, zext_oneuse, defm : VPatWidenBinarySDNode_VV_VX<mul, sext_oneuse, zext_oneuse,
"PseudoVWMULSU">; "PseudoVWMULSU">;
defm : VPatWidenBinarySDNode_VV_VX<mul, sext_oneuse, anyext_oneuse, defm : VPatWidenBinarySDNode_VV_VX<mul, sext_oneuse, anyext_oneuse,
"PseudoVWMULSU">; "PseudoVWMULSU">;
// 12.13 Vector Single-Width Integer Multiply-Add Instructions. // 12.13 Vector Single-Width Integer Multiply-Add Instructions.
foreach vti = AllIntegerVectors in { defm : VPatMultiplyAddSDNode_VV_VX<add, "PseudoVMADD">;
// NOTE: We choose VMADD because it has the most commuting freedom. So it defm : VPatMultiplyAddSDNode_VV_VX<sub, "PseudoVNMSUB">;
// works best with how TwoAddressInstructionPass tries commuting.
defvar suffix = vti.LMul.MX;
def : Pat<(vti.Vector (add vti.RegClass:$rs2,
(mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))),
(!cast<Instruction>("PseudoVMADD_VV_"# suffix)
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(vti.Vector (sub vti.RegClass:$rs2,
(mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))),
(!cast<Instruction>("PseudoVNMSUB_VV_"# suffix)
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
// The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally
// commutable.
def : Pat<(vti.Vector (add vti.RegClass:$rs2,
(mul_oneuse (SplatPat XLenVT:$rs1),
vti.RegClass:$rd))),
(!cast<Instruction>("PseudoVMADD_VX_" # suffix)
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(vti.Vector (sub vti.RegClass:$rs2,
(mul_oneuse (SplatPat XLenVT:$rs1),
vti.RegClass:$rd))),
(!cast<Instruction>("PseudoVNMSUB_VX_" # suffix)
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
// 12.14 Vector Widening Integer Multiply-Add Instructions // 12.14 Vector Widening Integer Multiply-Add Instructions
defm : VPatWidenMulAddSDNode_VV<sext_oneuse, sext_oneuse, "PseudoVWMACC">; defm : VPatWidenMulAddSDNode_VV<sext_oneuse, sext_oneuse, "PseudoVWMACC">;
defm : VPatWidenMulAddSDNode_VX<sext_oneuse, sext_oneuse, "PseudoVWMACC">; defm : VPatWidenMulAddSDNode_VX<sext_oneuse, sext_oneuse, "PseudoVWMACC">;
defm : VPatWidenMulAddSDNode_VV<zext_oneuse, zext_oneuse, "PseudoVWMACCU">; defm : VPatWidenMulAddSDNode_VV<zext_oneuse, zext_oneuse, "PseudoVWMACCU">;
defm : VPatWidenMulAddSDNode_VX<zext_oneuse, zext_oneuse, "PseudoVWMACCU">; defm : VPatWidenMulAddSDNode_VX<zext_oneuse, zext_oneuse, "PseudoVWMACCU">;
defm : VPatWidenMulAddSDNode_VV<sext_oneuse, zext_oneuse, "PseudoVWMACCSU">; defm : VPatWidenMulAddSDNode_VV<sext_oneuse, zext_oneuse, "PseudoVWMACCSU">;
defm : VPatWidenMulAddSDNode_VX<sext_oneuse, zext_oneuse, "PseudoVWMACCSU">; defm : VPatWidenMulAddSDNode_VX<sext_oneuse, zext_oneuse, "PseudoVWMACCSU">;
▲ Show 20 Lines • Show All 299 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 823 Lines • ▼ Show 20 Lines def : Pat<
(vti.Wti.Mask true_mask), VLOpFrag), (vti.Wti.Mask true_mask), VLOpFrag),
(vti.Vti.Mask true_mask), VLOpFrag)), (vti.Vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX)
vti.Wti.RegClass:$rs2, GPR:$rs1, vti.Wti.RegClass:$rs2, GPR:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>; vti.Vti.AVL, vti.Vti.Log2SEW)>;
} }
} }
multiclass VPatMultiplyAddVL_VV_VX<SDNode op, string instruction_name> {
foreach vti = AllIntegerVectors in {
defvar suffix = vti.LMul.MX;
// NOTE: We choose VMADD because it has the most commuting freedom. So it
// works best with how TwoAddressInstructionPass tries commuting.
def : Pat<(vti.Vector
(op vti.RegClass:$rs2,
(riscv_mul_vl_oneuse vti.RegClass:$rs1,
vti.RegClass:$rd,
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_VV_"# suffix)
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
// The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally
// commutable.
def : Pat<(vti.Vector
(op vti.RegClass:$rs2,
(riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1),
vti.RegClass:$rd,
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_VX_" # suffix)
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
multiclass VPatWidenMultiplyAddVL_VV_VX<PatFrag op1, string instruction_name> {
foreach vtiTowti = AllWidenableIntVectors in {
defvar vti = vtiTowti.Vti;
defvar wti = vtiTowti.Wti;
def : Pat<(wti.Vector
(riscv_add_vl wti.RegClass:$rd,
(op1 vti.RegClass:$rs1,
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_VV_" # vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(wti.Vector
(riscv_add_vl wti.RegClass:$rd,
(op1 (SplatPat XLenVT:$rs1),
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_VX_" # vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Patterns. // Patterns.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasVInstructions] in { let Predicates = [HasVInstructions] in {
// 12.1. Vector Single-Width Integer Add and Subtract // 12.1. Vector Single-Width Integer Add and Subtract
defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">; defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">;
▲ Show 20 Lines • Show All 163 Lines • ▼ Show 20 Lines
defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">;
// 12.12. Vector Widening Integer Multiply Instructions // 12.12. Vector Widening Integer Multiply Instructions
defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">; defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">;
defm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">; defm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">;
defm : VPatBinaryWVL_VV_VX<riscv_vwmulsu_vl, "PseudoVWMULSU">; defm : VPatBinaryWVL_VV_VX<riscv_vwmulsu_vl, "PseudoVWMULSU">;
// 12.13 Vector Single-Width Integer Multiply-Add Instructions // 12.13 Vector Single-Width Integer Multiply-Add Instructions
foreach vti = AllIntegerVectors in { defm : VPatMultiplyAddVL_VV_VX<riscv_add_vl, "PseudoVMADD">;
// NOTE: We choose VMADD because it has the most commuting freedom. So it defm : VPatMultiplyAddVL_VV_VX<riscv_sub_vl, "PseudoVNMSUB">;
// works best with how TwoAddressInstructionPass tries commuting.
defvar suffix = vti.LMul.MX;
def : Pat<(vti.Vector
(riscv_add_vl vti.RegClass:$rs2,
(riscv_mul_vl_oneuse vti.RegClass:$rs1,
vti.RegClass:$rd,
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>("PseudoVMADD_VV_"# suffix)
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(vti.Vector
(riscv_sub_vl vti.RegClass:$rs2,
(riscv_mul_vl_oneuse vti.RegClass:$rs1,
vti.RegClass:$rd,
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>("PseudoVNMSUB_VV_"# suffix)
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
// The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally
// commutable.
def : Pat<(vti.Vector
(riscv_add_vl vti.RegClass:$rs2,
(riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1),
vti.RegClass:$rd,
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>("PseudoVMADD_VX_" # suffix)
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(vti.Vector
(riscv_sub_vl vti.RegClass:$rs2,
(riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1),
vti.RegClass:$rd,
(vti.Mask true_mask),
VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>("PseudoVNMSUB_VX_" # suffix)
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
// 12.14. Vector Widening Integer Multiply-Add Instructions // 12.14. Vector Widening Integer Multiply-Add Instructions
defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmul_vl_oneuse, "PseudoVWMACC">;
defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmulu_vl_oneuse, "PseudoVWMACCU">;
defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmulsu_vl_oneuse, "PseudoVWMACCSU">;
foreach vtiTowti = AllWidenableIntVectors in { foreach vtiTowti = AllWidenableIntVectors in {
defvar vti = vtiTowti.Vti; defvar vti = vtiTowti.Vti;
defvar wti = vtiTowti.Wti; defvar wti = vtiTowti.Wti;
def : Pat<(wti.Vector def : Pat<(wti.Vector
(riscv_add_vl wti.RegClass:$rd, (riscv_add_vl wti.RegClass:$rd,
(riscv_vwmul_vl_oneuse vti.RegClass:$rs1,
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>("PseudoVWMACC_VV_" # vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
frasercrmckUnsubmitted
Not Done
ReplyInline Actions

We're losing the wti in wti.RegClass:$rd, vti.RegClass:$rs1 here by moving to VPatWidenMultiplyAddVL_VV_VX. I'm not sure why this isn't an error.

frasercrmck: We're losing the `wti` in `wti.RegClass:$rd, vti.RegClass:$rs1` here by moving to…
craig.topperUnsubmitted
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Doesn't VPatWidenMultiplyAddVL_VV_VX also use wti.RegClass:$rd, vti.RegClass:$rs1?

craig.topper: Doesn't VPatWidenMultiplyAddVL_VV_VX also use `wti.RegClass:$rd, vti.RegClass:$rs1`?
frasercrmckUnsubmitted
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Oh dear, yes of course. I think I was looking at VPatMultiplyAddVL_VV_VX by mistake.

frasercrmck: Oh dear, yes of course. I think I was looking at `VPatMultiplyAddVL_VV_VX` by mistake.
JimerlifeAuthorUnsubmitted
Done
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VPatWidenMultiplyAddVL_VV_VX also used wti.RegClass:$rd, vti.RegClass:$rs1

Jimerlife: VPatWidenMultiplyAddVL_VV_VX also used wti.RegClass:$rd, vti.RegClass:$rs1
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(wti.Vector
(riscv_add_vl wti.RegClass:$rd,
(riscv_vwmulu_vl_oneuse vti.RegClass:$rs1,
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>("PseudoVWMACCU_VV_" # vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(wti.Vector
(riscv_add_vl wti.RegClass:$rd,
(riscv_vwmulsu_vl_oneuse vti.RegClass:$rs1,
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>("PseudoVWMACCSU_VV_" # vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(wti.Vector
(riscv_add_vl wti.RegClass:$rd,
(riscv_vwmul_vl_oneuse (SplatPat XLenVT:$rs1),
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>("PseudoVWMACC_VX_" # vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(wti.Vector
(riscv_add_vl wti.RegClass:$rd,
(riscv_vwmulu_vl_oneuse (SplatPat XLenVT:$rs1),
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>("PseudoVWMACCU_VX_" # vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(wti.Vector
(riscv_add_vl wti.RegClass:$rd,
(riscv_vwmulsu_vl_oneuse (SplatPat XLenVT:$rs1),
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>("PseudoVWMACCSU_VX_" # vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(wti.Vector
(riscv_add_vl wti.RegClass:$rd,
(riscv_vwmulsu_vl_oneuse (vti.Vector vti.RegClass:$rs1), (riscv_vwmulsu_vl_oneuse (vti.Vector vti.RegClass:$rs1),
(SplatPat XLenVT:$rs2), (SplatPat XLenVT:$rs2),
(vti.Mask true_mask), VLOpFrag), (vti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)), (vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>("PseudoVWMACCUS_VX_" # vti.LMul.MX) (!cast<Instruction>("PseudoVWMACCUS_VX_" # vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs2, vti.RegClass:$rs1, wti.RegClass:$rd, vti.ScalarRegClass:$rs2, vti.RegClass:$rs1,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
} }
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