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[Hexagon] Enable IAS in the Hexagon backend
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Authored by brad on Apr 4 2022, 4:13 PM.

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Details

Reviewers

bcain
kparzysz
MaskRay
sidneym

Commits

rGa0bc67e555f4: [Hexagon] Enable IAS in the Hexagon backend

Diff Detail

Repository: rG LLVM Github Monorepo

Unit TestsFailed

	Time	Test
	100 ms	x64 debian > LLVM.CodeGen/Hexagon::inline-asm-hexagon.ll
	100 ms	x64 debian > LLVM.CodeGen/Hexagon::inline-asm-i1.ll
	100 ms	x64 debian > LLVM.CodeGen/Hexagon::inline-asm-qv.ll
	160 ms	x64 debian > LLVM.CodeGen/Hexagon::rdf-inline-asm-fixed.ll
	130 ms	x64 debian > LLVM.CodeGen/Hexagon::v6-inlasm1.ll
		View Full Test Results (13 Failed)

Event Timeline

brad created this revision.Apr 4 2022, 4:13 PM

Herald added a project: Restricted Project. · View Herald TranscriptApr 4 2022, 4:13 PM

Herald added a subscriber: hiraditya. · View Herald Transcript

brad requested review of this revision.Apr 4 2022, 4:13 PM

Herald added a subscriber: llvm-commits. · View Herald TranscriptApr 4 2022, 4:13 PM

Harbormaster completed remote builds in B157856: Diff 420338.Apr 4 2022, 5:37 PM

brad added a reviewer: sidneym.Apr 15 2022, 1:43 AM

Updated diff.

Harbormaster completed remote builds in B165983: Diff 431566.May 23 2022, 8:38 PM

brad edited reviewers, added: MaskRay; removed: sidneym.May 28 2022, 8:35 PM

Herald added a subscriber: StephenFan. · View Herald TranscriptMay 28 2022, 8:35 PM

brad added a reviewer: sidneym.May 28 2022, 8:36 PM

kparzysz accepted this revision.Jun 1 2022, 7:36 AM

This revision is now accepted and ready to land.Jun 1 2022, 7:36 AM

This revision was landed with ongoing or failed builds.Jun 3 2022, 3:20 PM

Closed by commit rGa0bc67e555f4: [Hexagon] Enable IAS in the Hexagon backend (authored by brad). · Explain Why

This revision was automatically updated to reflect the committed changes.

brad added a commit: rGa0bc67e555f4: [Hexagon] Enable IAS in the Hexagon backend.

Revision Contents

Path

Size

llvm/

lib/

Target/

Hexagon/

MCTargetDesc/

HexagonMCAsmInfo.cpp

1 line

Diff 420338

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp

Show All 28 Lines	HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) {
InlineAsmEnd = "# InlineAsm End";		InlineAsmEnd = "# InlineAsm End";
ZeroDirective = "\t.space\t";		ZeroDirective = "\t.space\t";
AscizDirective = "\t.string\t";		AscizDirective = "\t.string\t";

MinInstAlignment = 4;		MinInstAlignment = 4;
UsesELFSectionDirectiveForBSS = true;		UsesELFSectionDirectiveForBSS = true;
ExceptionsType = ExceptionHandling::DwarfCFI;		ExceptionsType = ExceptionHandling::DwarfCFI;
UseLogicalShr = false;		UseLogicalShr = false;
UseIntegratedAssembler = false;
}		}