[Hexagon] Enable IAS in the Hexagon backend

[brad]

Updated diff.

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp

HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) {
   InlineAsmEnd = "# InlineAsm End";
   ZeroDirective = "\t.space\t";
   AscizDirective = "\t.string\t";
 
   MinInstAlignment = 4;
   UsesELFSectionDirectiveForBSS  = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
   UseLogicalShr = false;
-  UseIntegratedAssembler = false;
 }

llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll

-; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -no-integrated-as < %s | FileCheck %s
 
 target triple = "hexagon"
 
 ;CHECK: [[REGH:r[0-9]]]:[[REGL:[0-9]]] = memd_locked
 ;CHECK: HIGH([[REGH]])
 ;CHECK: LOW(r[[REGL]])
 define i32 @fred(i64* %free_list_ptr, i32** %item_ptr, i8** %free_item_ptr) nounwind {
 entry:
   %free_list_ptr.addr = alloca i64*, align 4
   store i64* %free_list_ptr, i64** %free_list_ptr.addr, align 4
   %0 = load i32*, i32** %item_ptr, align 4
   %1 = call { i64, i32 } asm sideeffect "1:     $0 = memd_locked($5)\0A\09       $1 = HIGH(${0:H}) \0A\09       $1 = add($1,#1) \0A\09       memw($6) = LOW(${0:L}) \0A\09       $0 = combine($7,$1) \0A\09       memd_locked($5,p0) = $0 \0A\09       if !p0 jump 1b\0A\09", "=&r,=&r,=*m,=*m,r,r,r,r,*m,*m,~{p0}"(i64** elementtype(i64*) %free_list_ptr.addr, i8** elementtype(i8*) %free_item_ptr, i64 0, i64* %free_list_ptr, i8** %free_item_ptr, i32* %0, i64** elementtype(i64*) %free_list_ptr.addr, i8** elementtype(i8*) %free_item_ptr) nounwind
   %asmresult1 = extractvalue { i64, i32 } %1, 1
   ret i32 %asmresult1
 }

llvm/test/CodeGen/Hexagon/inline-asm-i1.ll

 ; RUN: llc -march=hexagon < %s | FileCheck %s
 ; CHECK: r[[REG0:[0-9]+]] = usr
-; CHECK: [[REG0]] = insert(r{{[0-9]+}}, #1, #16)
+; CHECK: [[REG0]] = insert(r{{[0-9]+}},#1,#16)
 
 target triple = "hexagon"
 
 define hidden void @fred() #0 {
 entry:
   %0 = call { i32, i32 } asm sideeffect " $0 = usr\0A $1 = $2\0A $0 = insert($1, #1, #16)\0Ausr = $0 \0A", "=&r,=&r,r"(i1 undef) #1
   ret void
 }
 
 attributes #0 = { nounwind "target-cpu"="hexagonv60" }
 attributes #1 = { nounwind }

llvm/test/CodeGen/Hexagon/inline-asm-qv.ll

-; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -no-integrated-as < %s | FileCheck %s
 
 ; Check that constraints q and v are handled correctly.
 ; CHECK: q{{.}} = vgtw(v{{.}}.w,v{{.}}.w)
 ; CHECK: vand
 ; CHECK: vmem
 
 target triple = "hexagon"
 

llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll

 ; RUN: llc -march=hexagon < %s | FileCheck %s
 ; CHECK: r0 = #24
-; CHECK-NEXT: r1 =
+; CHECK: r1 =
 ; // R2 should be assigned a value from R3+.
-; CHECK-NEXT: r2 = r{{[3-9]}}
-; CHECK-NEXT: trap0
+; CHECK: r2 = r{{[3-9]}}
+; CHECK: trap0
 
 target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
 target triple = "hexagon"
 
 ; Function Attrs: nounwind
 define i32 @foo(i32 %status) #0 {
 entry:
   %arg1 = alloca i32, align 4

llvm/test/CodeGen/Hexagon/v6-inlasm1.ll

 ; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
-; CHECK: vmemu(r{{[0-9]+}}) = v{{[0-9]*}};
+; CHECK: vmemu(r{{[0-9]+}}+#0) = v{{[0-9]*}}
 
 target triple = "hexagon"
 
 ; Function Attrs: nounwind
 define void @f0(i8* %a0, i32 %a1, i8* %a2, i32 %a3, i8* %a4) #0 {
 b0:
   %v0 = alloca i8*, align 4
   %v1 = alloca i32, align 4

llvm/test/CodeGen/Hexagon/v6-inlasm2.ll

 ; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
-; CHECK: vmemu(r{{[0-9]+}}) = v{{[0-9]*}};
+; CHECK: vmemu(r{{[0-9]}}+#0) = v{{[0-9]*}}
 
 target triple = "hexagon"
 
 ; Function Attrs: nounwind
 define void @f0(i8* %a0, i8* %a1) #0 {
 b0:
   %v0 = alloca i8*, align 4
   %v1 = alloca i8*, align 4

llvm/test/CodeGen/Hexagon/v6-inlasm3.ll

 ; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
-; CHECK: vmemu(r{{[0-9]+}}) = v{{[0-9]*}}
+; CHECK: vmemu(r{{[0-9]}}+#0) = v{{[0-9]*}}
 
 target triple = "hexagon"
 
 ; Function Attrs: nounwind
 define void @f0(i8* %a0, i8* %a1) #0 {
 b0:
   %v0 = alloca i8*, align 4
   %v1 = alloca i8*, align 4

llvm/test/CodeGen/Hexagon/v6vec-vprint.ll

-; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s
-; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s
+; RUN: llc -no-integrated-as -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s
+; RUN: llc -no-integrated-as -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s
 ;   generate .long XXXX which is a vector debug print instruction.
 ; CHECK: .long 0x1dffe0
 ; CHECK: .long 0x1dffe0
 ; CHECK: .long 0x1dffe0
 ; VSTPRINT: .long 0x1dffe0
 ; VSTPRINT-NOT: .long 0x1dffe0
 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
 target triple = "hexagon"