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Differential D122664

[AMDGPU] Fix last remaining checks in perfhint.ll
ClosedPublic

Authored by foad on Mar 29 2022, 9:09 AM.

Details

Reviewers
rampitec
yaxunl
Commits
rGfdaf606c8ebb: [AMDGPU] Fix last remaining checks in perfhint.ll
Summary

Unfortunately this just shows that the test case for D47740 never
really tested what it was supposed to test.

Diff Detail

Event Timeline

foad created this revision.Mar 29 2022, 9:09 AM
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Herald added subscribers: kerbowa, t-tye, tpr and 3 others. · View Herald Transcript
foad requested review of this revision.Mar 29 2022, 9:09 AM
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foad added inline comments.Mar 29 2022, 9:12 AM
llvm/test/CodeGen/AMDGPU/perfhint.ll
81

@rampitec do you want to try to come up with a test that really does result in "WaveLimiterHint : 0"? It seems hard because the default value for -amdgpu-indirect-access-weight is so high. (See also D83675.)

rampitec accepted this revision.Mar 29 2022, 11:31 AM
rampitec added inline comments.
llvm/test/CodeGen/AMDGPU/perfhint.ll
81

Do you mind to place FIXME here?

This revision is now accepted and ready to land.Mar 29 2022, 11:31 AM
Harbormaster completed remote builds in B156777: Diff 418900.Mar 30 2022, 3:50 AM
foad updated this revision to Diff 419405.Mar 31 2022, 5:23 AM

Add FIXME.

This revision was landed with ongoing or failed builds.Mar 31 2022, 5:39 AM
Closed by commit rGfdaf606c8ebb: [AMDGPU] Fix last remaining checks in perfhint.ll (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rGfdaf606c8ebb: [AMDGPU] Fix last remaining checks in perfhint.ll.
Harbormaster completed remote builds in B157148: Diff 419405.Mar 31 2022, 11:02 AM

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
5 lines

Diff 419409

llvm/test/CodeGen/AMDGPU/perfhint.ll

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Linesbb:
%tmp17 = extractelement <4 x i32> %tmp4, i32 3 %tmp17 = extractelement <4 x i32> %tmp4, i32 3
%tmp18 = sext i32 %tmp17 to i64 %tmp18 = sext i32 %tmp17 to i64
%tmp19 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp18 %tmp19 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp18
%tmp20 = load i32, i32 addrspace(1)* %tmp19, align 4 %tmp20 = load i32, i32 addrspace(1)* %tmp19, align 4
store i32 %tmp20, i32 addrspace(1)* %tmp2, align 4 store i32 %tmp20, i32 addrspace(1)* %tmp2, align 4
ret void ret void
} }
; FIXME: This test was intended to be WaveLimiterHint : 0
; GCN-LABEL: {{^}}test_indirect_through_phi: ; GCN-LABEL: {{^}}test_indirect_through_phi:
; MemoryBound: 0 ; GCN: MemoryBound: 0
; WaveLimiterHint : 0 ; GCN: WaveLimiterHint : 1
foadAuthorUnsubmitted
Done
ReplyInline Actions

@rampitec do you want to try to come up with a test that really does result in "WaveLimiterHint : 0"? It seems hard because the default value for -amdgpu-indirect-access-weight is so high. (See also D83675.)

foad: @rampitec do you want to try to come up with a test that really does result in "WaveLimiterHint…
rampitecUnsubmitted
Not Done
ReplyInline Actions

Do you mind to place FIXME here?

rampitec: Do you mind to place FIXME here?
define amdgpu_kernel void @test_indirect_through_phi(float addrspace(1)* %arg) { define amdgpu_kernel void @test_indirect_through_phi(float addrspace(1)* %arg) {
bb: bb:
%load = load float, float addrspace(1)* %arg, align 8 %load = load float, float addrspace(1)* %arg, align 8
%load.f = bitcast float %load to i32 %load.f = bitcast float %load to i32
%n = tail call i32 @llvm.amdgcn.workitem.id.x() %n = tail call i32 @llvm.amdgcn.workitem.id.x()
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
Show All 16 Lines