[AVR] Remove AVRRelaxMemOperations

[Patryk27]

Summary

This commit contains a refactoring that merges AVRRelaxMemOperations
into AVRExpandPseudoInsts, so that we have a single place in code that
expands the STDWPtrQRr opcode.

Seizing the day, I've also fixed a couple of potential bugs with our
previous implementation (e.g. when the destination register was killed,
the previous implementation would try to .addDef() that killed
register, crashing LLVM in the process - that's fixed now, as proved by
the test).

In the bigger picture, this commit is the first step of fixing
https://reviews.llvm.org/D114611.

[Patryk27]

avr -> AVR

[Patryk27]

cc @benshi001 (from https://reviews.llvm.org/D114611) 🙂

[benshi001]

I have built (with -DCMAKE_BUILD_TYPE=Debug) and tested your patch, but got the following failure

FAIL: LLVM :: CodeGen/AVR/pseudo/STDWPtrQRr.mir (150 of 152)
******************** TEST 'LLVM :: CodeGen/AVR/pseudo/STDWPtrQRr.mir' FAILED ********************
Script:
--
: 'RUN: at line 1';   /home/shiben/work/llvm-project/build-x/bin/llc -O0 -run-pass=avr-expand-pseudo /home/shiben/work/llvm-project/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir -o - | /home/shiben/work/llvm-project/build-x/bin/FileCheck /home/shiben/work/llvm-project/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
--
Exit Code: 2

Command Output (stderr):
--

# After AVR pseudo instruction expansion pass
# Machine code for function test: IsSSA, NoPHIs, TracksLiveness, NoVRegs

bb.0.entry:
  STDPtrQRr $r29r28, 3, $r0
  STDPtrQRr $r29r28, 4, $r1
  STDPtrQRr $r29r28, 3, $r0
  STDPtrQRr killed $r29r28, 4, $r1
  STDPtrQRr $r29r28, 3, killed $r0
  STDPtrQRr $r29r28, 4, killed $r1
  STDPtrQRr $r29r28, 62, $r0
  STDPtrQRr $r29r28, 63, $r1
  PUSHRr $r28, implicit-def $sp, implicit $sp
  PUSHRr $r29, implicit-def $sp, implicit $sp
  $r28 = SBCIRdK killed $r28(tied-def 0), 193, implicit-def $sreg, implicit killed $sreg
  $r29 = SBCIRdK killed $r29(tied-def 0), 255, implicit-def $sreg, implicit killed $sreg
  STPtrRr $r29r28, $r0
  STDPtrQRr $r29r28, 1, $r1
  $r29 = POPRd implicit-def $sp, implicit $sp
  $r28 = POPRd implicit-def $sp, implicit $sp
  $r28 = SBCIRdK killed $r28(tied-def 0), 193, implicit-def $sreg, implicit killed $sreg
  $r29 = SBCIRdK killed $r29(tied-def 0), 255, implicit-def $sreg, implicit killed $sreg
  STPtrRr $r29r28, $r0
  STDPtrQRr $r29r28, 1, $r1
  PUSHRr $r28, implicit-def $sp, implicit $sp
  PUSHRr $r29, implicit-def $sp, implicit $sp
  $r28 = SBCIRdK killed $r28(tied-def 0), 193, implicit-def $sreg, implicit killed $sreg
  $r29 = SBCIRdK killed $r29(tied-def 0), 255, implicit-def $sreg, implicit killed $sreg
  STPtrRr $r29r28, killed $r0
  STDPtrQRr $r29r28, 1, killed $r1
  $r29 = POPRd implicit-def $sp, implicit $sp
  $r28 = POPRd implicit-def $sp, implicit $sp

# End machine code for function test.

*** Bad machine code: Using an undefined physical register ***
- function:    test
- basic block: %bb.0 entry (0x563a083b79e8)
- instruction: $r28 = SBCIRdK killed $r28(tied-def 0), 193, implicit-def $sreg, implicit killed $sreg
- operand 4:   implicit killed $sreg
LLVM ERROR: Found 1 machine code errors.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: /home/shiben/work/llvm-project/build-x/bin/llc -O0 -run-pass=avr-expand-pseudo /home/shiben/work/llvm-project/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir -o -
1.      Running pass 'Function Pass Manager' on module '/home/shiben/work/llvm-project/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir'.
2.      Running pass 'Verify generated machine code' on function '@test'
 #0 0x0000563a036e61a8 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /home/shiben/work/llvm-project/llvm/lib/Support/Unix/Signals.inc:565:0
 #1 0x0000563a036e625f PrintStackTraceSignalHandler(void*) /home/shiben/work/llvm-project/llvm/lib/Support/Unix/Signals.inc:632:0
 #2 0x0000563a036e3e22 llvm::sys::RunSignalHandlers() /home/shiben/work/llvm-project/llvm/lib/Support/Signals.cpp:103:0
 #3 0x0000563a036e5b29 SignalHandler(int) /home/shiben/work/llvm-project/llvm/lib/Support/Unix/Signals.inc:407:0
 #4 0x00007f1480842980 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x12980)
 #5 0x00007f147f4f2e87 raise /build/glibc-uZu3wS/glibc-2.27/signal/../sysdeps/unix/sysv/linux/raise.c:51:0
 #6 0x00007f147f4f47f1 abort /build/glibc-uZu3wS/glibc-2.27/stdlib/abort.c:81:0
 #7 0x0000563a036202ea llvm::install_bad_alloc_error_handler(void (*)(void*, char const*, bool), void*) /home/shiben/work/llvm-project/llvm/lib/Support/ErrorHandling.cpp:126:0
 #8 0x0000563a026cec3f (anonymous namespace)::MachineVerifierPass::runOnMachineFunction(llvm::MachineFunction&) /home/shiben/work/llvm-project/llvm/lib/CodeGen/MachineVerifier.cpp:307:0
 #9 0x0000563a0259c657 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /home/shiben/work/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:73:0
#10 0x0000563a02c7f2b3 llvm::FPPassManager::runOnFunction(llvm::Function&) /home/shiben/work/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1430:0
#11 0x0000563a02c7f633 llvm::FPPassManager::runOnModule(llvm::Module&) /home/shiben/work/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1476:0
#12 0x0000563a02c7fa7b (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) /home/shiben/work/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1545:0
#13 0x0000563a02c7a95b llvm::legacy::PassManagerImpl::run(llvm::Module&) /home/shiben/work/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:535:0
#14 0x0000563a02c8034f llvm::legacy::PassManager::run(llvm::Module&) /home/shiben/work/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1673:0
#15 0x0000563a018e2ad1 compileModule(char**, llvm::LLVMContext&) /home/shiben/work/llvm-project/llvm/tools/llc/llc.cpp:724:0
#16 0x0000563a018e073f main /home/shiben/work/llvm-project/llvm/tools/llc/llc.cpp:419:0
#17 0x00007f147f4d5c87 __libc_start_main /build/glibc-uZu3wS/glibc-2.27/csu/../csu/libc-start.c:344:0
#18 0x0000563a018df4ca _start (/home/shiben/work/llvm-project/build-x/bin/llc+0x14b54ca)
FileCheck error: '<stdin>' is empty.
FileCheck command line:  /home/shiben/work/llvm-project/build-x/bin/FileCheck /home/shiben/work/llvm-project/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir

--

********************
********************
Failed Tests (1):
  LLVM :: CodeGen/AVR/pseudo/STDWPtrQRr.mir


Testing Time: 33.51s
  Passed           : 148
  Expectedly Failed:   3
  Failed           :   1

[Patryk27]

Hmm, that's weird - I've just re-checked and everything's working correctly on my side; maybe you're testing it on an older LLVM revision? (for reference, my patch is based off of the current LLVM's main branch, which - at the time of writing this comment - is the d9cea8d3a8fff86672174780312674871729578c commit).

[benshi001]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1174–1177

The above built error is caused by this line, this should be a SUBI other than a SBCI.

[benshi001]

In D122533#3410064, @Patryk27 wrote:

Hmm, that's weird - I've just re-checked and everything's working correctly on my side; maybe you're testing it on an older LLVM revision? (for reference, my patch is based off of the current LLVM's main branch, which - at the time of writing this comment - is the d9cea8d3a8fff86672174780312674871729578c commit).

I tested based on https://github.com/llvm/llvm-project/commit/674d52e8ced27bf427b3ea2c763a566ca9b8212a, which is also today's (March 27) revision. Did you build LLVM with -DCMAKE_BUILD_TYPE=Debug , it seems only debug version of llvm will get this issue be triggered.

[Patryk27]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1174–1177

Out of curiosity, why SUBI? (just trying to understand what is the difference between both)

It looks like currently - https://github.com/llvm/llvm-project/blob/d9cea8d3a8fff86672174780312674871729578c/llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp#L101 - we expand to SBCI.

[benshi001]

llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir

1

You can trigger the bug, with -verify-machineinstrs option after the -run-pass=avr-expand-pseudo option.

[Patryk27]

I think I'm using =Release instead of =Debug, that would explain the difference, yeah;

[benshi001]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1174–1177

I thought this should be an old bug which has never been triggered. Actually if C bit in SREG is set before current STWPtrPdRr, then it is sure to run into wrong.

[benshi001]

In D122533#3410072, @Patryk27 wrote:

I think I'm using =Release instead of =Debug, that would explain the difference, yeah;

You need not Debug, just add -verify-machineinstrs option after the -run-pass=avr-expand-pseudo, then the bug will also be triggered.

[Patryk27]

SBCI -> SUBI

[benshi001]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1174–1177

Sorry, I think this should be a SUBIW, neither SBCIW nor SUBI.

[Patryk27]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1174–1177

Right, great catch - fixed!

[Patryk27]

Ah, sorry - I've pushed my changes at the same time you created your comment; one moment, let me change to SUBIW, then.

[Patryk27]

Ah, nevermind - looks like I've already actually used SUBIWRdK.

[benshi001]

llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir

1

I still suggest you add a -verify-machineinstrs option after the -run-pass=avr-expand-pseudo option.

[Patryk27]

Add -verify-machineinstrs

[Patryk27]

Ok, I have added the switch; I think a separate patch that adds that switch to all of the AVR tests could come handy - what do you think?

[benshi001]

@aykevl How about your opinion? I think current form is good!

[benshi001]

In D122533#3410259, @Patryk27 wrote:

Ok, I have added the switch; I think a separate patch that adds that switch to all of the AVR tests could come handy - what do you think?

No. -verify-machineinstrs might be default in the future, which is still under discuss, since it costs longer time. Currently we just make highly risky case with explicit -verify-machineinstrs, such as yours. ^_^

[Patryk27]

In D122533#3410428, @benshi001 wrote:

In D122533#3410259, @Patryk27 wrote:

Ok, I have added the switch; I think a separate patch that adds that switch to all of the AVR tests could come handy - what do you think?

No. -verify-machineinstrs might be default in the future, which is still under discuss, since it costs longer time. Currently we just make highly risky case with explicit -verify-machineinstrs, such as yours. ^_^

Okie, understood - thanks :-)

clang/docs/tools/clang-formatted-files.txt

 llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp
 llvm/lib/Target/AVR/AVRISelLowering.cpp
 llvm/lib/Target/AVR/AVRISelLowering.h
 llvm/lib/Target/AVR/AVRMachineFunctionInfo.h
 llvm/lib/Target/AVR/AVRMCInstLower.cpp
 llvm/lib/Target/AVR/AVRMCInstLower.h
 llvm/lib/Target/AVR/AVRRegisterInfo.cpp
 llvm/lib/Target/AVR/AVRRegisterInfo.h
-llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp
 llvm/lib/Target/AVR/AVRSelectionDAGInfo.h
 llvm/lib/Target/AVR/AVRShiftExpand.cpp
 llvm/lib/Target/AVR/AVRSubtarget.cpp
 llvm/lib/Target/AVR/AVRSubtarget.h
 llvm/lib/Target/AVR/AVRTargetMachine.cpp
 llvm/lib/Target/AVR/AVRTargetMachine.h
 llvm/lib/Target/AVR/AVRTargetObjectFile.cpp
 llvm/lib/Target/AVR/AVRTargetObjectFile.h

llvm/lib/Target/AVR/AVR.h

 class AVRTargetMachine;
 class FunctionPass;
 
 Pass *createAVRShiftExpandPass();
 FunctionPass *createAVRISelDag(AVRTargetMachine &TM,
                                CodeGenOpt::Level OptLevel);
 FunctionPass *createAVRExpandPseudoPass();
 FunctionPass *createAVRFrameAnalyzerPass();
-FunctionPass *createAVRRelaxMemPass();
 FunctionPass *createAVRBranchSelectionPass();
 
 void initializeAVRShiftExpandPass(PassRegistry &);
 void initializeAVRExpandPseudoPass(PassRegistry &);
-void initializeAVRRelaxMemPass(PassRegistry &);
 
 /// Contains the AVR backend.
 namespace AVR {
 
 /// An integer that identifies all of the supported AVR address spaces.
 enum AddressSpace {
   DataMemory,
   ProgramMemory,

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

bool AVRExpandPseudo::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) {
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
-  Register SrcLoReg, SrcHiReg;
+
   Register DstReg = MI.getOperand(0).getReg();
-  Register SrcReg = MI.getOperand(2).getReg();
-  unsigned Imm = MI.getOperand(1).getImm();
   bool DstIsKill = MI.getOperand(0).isKill();
+  unsigned Imm = MI.getOperand(1).getImm();
+  Register SrcReg = MI.getOperand(2).getReg();
   bool SrcIsKill = MI.getOperand(2).isKill();
+
+  // STD's maximum displacement is 63, so larger stores have to be split into a
+  // set of operations
+  if (Imm >= 63) {
+    if (!DstIsKill) {
+      buildMI(MBB, MBBI, AVR::PUSHWRr).addReg(DstReg);
+    }
+
+    buildMI(MBB, MBBI, AVR::SUBIWRdK)
+        .addReg(DstReg, RegState::Define)
+        .addReg(DstReg, RegState::Kill)
+        .addImm(-Imm);
+
+    buildMI(MBB, MBBI, AVR::STWPtrRr)
+        .addReg(DstReg, RegState::Kill)
+        .addReg(SrcReg, getKillRegState(SrcIsKill));
+
+    if (!DstIsKill) {
+      buildMI(MBB, MBBI, AVR::POPWRd).addDef(DstReg, RegState::Define);
+    }
+  } else {
     unsigned OpLo = AVR::STDPtrQRr;
     unsigned OpHi = AVR::STDPtrQRr;
+    Register SrcLoReg, SrcHiReg;
     TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
 
-  // Since we add 1 to the Imm value for the high byte below, and 63 is the
-  // highest Imm value allowed for the instruction, 62 is the limit here.
-  assert(Imm <= 62 && "Offset is out of range");
-
     auto MIBLO = buildMI(MBB, MBBI, OpLo)
                      .addReg(DstReg)
                      .addImm(Imm)
                      .addReg(SrcLoReg, getKillRegState(SrcIsKill));
 
     auto MIBHI = buildMI(MBB, MBBI, OpHi)
                      .addReg(DstReg, getKillRegState(DstIsKill))
                      .addImm(Imm + 1)
                      .addReg(SrcHiReg, getKillRegState(SrcIsKill));
 
     MIBLO.setMemRefs(MI.memoperands());
     MIBHI.setMemRefs(MI.memoperands());
+  }
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;

llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp

-//===-- AVRRelaxMemOperations.cpp - Relax out of range loads/stores -------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains a pass which relaxes out of range memory operations into
-// equivalent operations which handle bigger addresses.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AVR.h"
-#include "AVRInstrInfo.h"
-#include "AVRTargetMachine.h"
-#include "MCTargetDesc/AVRMCTargetDesc.h"
-
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/TargetRegisterInfo.h"
-
-using namespace llvm;
-
-#define AVR_RELAX_MEM_OPS_NAME "AVR memory operation relaxation pass"
-
-namespace {
-
-class AVRRelaxMem : public MachineFunctionPass {
-public:
-  static char ID;
-
-  AVRRelaxMem() : MachineFunctionPass(ID) {
-    initializeAVRRelaxMemPass(*PassRegistry::getPassRegistry());
-  }
-
-  bool runOnMachineFunction(MachineFunction &MF) override;
-
-  StringRef getPassName() const override { return AVR_RELAX_MEM_OPS_NAME; }
-
-private:
-  typedef MachineBasicBlock Block;
-  typedef Block::iterator BlockIt;
-
-  const TargetInstrInfo *TII;
-
-  template <unsigned OP> bool relax(Block &MBB, BlockIt MBBI);
-
-  bool runOnBasicBlock(Block &MBB);
-  bool runOnInstruction(Block &MBB, BlockIt MBBI);
-
-  MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
-    return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
-  }
-};
-
-char AVRRelaxMem::ID = 0;
-
-bool AVRRelaxMem::runOnMachineFunction(MachineFunction &MF) {
-  bool Modified = false;
-
-  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
-  TII = STI.getInstrInfo();
-
-  for (Block &MBB : MF) {
-    bool BlockModified = runOnBasicBlock(MBB);
-    Modified |= BlockModified;
-  }
-
-  return Modified;
-}
-
-bool AVRRelaxMem::runOnBasicBlock(Block &MBB) {
-  bool Modified = false;
-
-  BlockIt MBBI = MBB.begin(), E = MBB.end();
-  while (MBBI != E) {
-    BlockIt NMBBI = std::next(MBBI);
-    Modified |= runOnInstruction(MBB, MBBI);
-    MBBI = NMBBI;
-  }
-
-  return Modified;
-}
-
-template <> bool AVRRelaxMem::relax<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
-  MachineInstr &MI = *MBBI;
-
-  MachineOperand &Ptr = MI.getOperand(0);
-  MachineOperand &Src = MI.getOperand(2);
-  int64_t Imm = MI.getOperand(1).getImm();
-
-  // We can definitely optimise this better.
-  if (Imm > 63) {
-    // Push the previous state of the pointer register.
-    // This instruction must preserve the value.
-    buildMI(MBB, MBBI, AVR::PUSHWRr).addReg(Ptr.getReg());
-
-    // Add the immediate to the pointer register.
-    buildMI(MBB, MBBI, AVR::SBCIWRdK)
-        .addReg(Ptr.getReg(), RegState::Define)
-        .addReg(Ptr.getReg())
-        .addImm(-Imm);
-
-    // Store the value in the source register to the address
-    // pointed to by the pointer register.
-    buildMI(MBB, MBBI, AVR::STWPtrRr)
-        .addReg(Ptr.getReg())
-        .addReg(Src.getReg(), getKillRegState(Src.isKill()));
-
-    // Pop the original state of the pointer register.
-    buildMI(MBB, MBBI, AVR::POPWRd)
-        .addDef(Ptr.getReg(), getKillRegState(Ptr.isKill()));
-
-    MI.removeFromParent();
-  }
-
-  return false;
-}
-
-bool AVRRelaxMem::runOnInstruction(Block &MBB, BlockIt MBBI) {
-  MachineInstr &MI = *MBBI;
-  int Opcode = MBBI->getOpcode();
-
-#define RELAX(Op)                                                              \
-  case Op:                                                                     \
-    return relax<Op>(MBB, MI)
-
-  switch (Opcode) { RELAX(AVR::STDWPtrQRr); }
-#undef RELAX
-  return false;
-}
-
-} // end of anonymous namespace
-
-INITIALIZE_PASS(AVRRelaxMem, "avr-relax-mem", AVR_RELAX_MEM_OPS_NAME, false,
-                false)
-
-namespace llvm {
-
-FunctionPass *createAVRRelaxMemPass() { return new AVRRelaxMem(); }
-
-} // end of namespace llvm

llvm/lib/Target/AVR/AVRTargetMachine.cpp

 }
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTarget() {
   // Register the target.
   RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget());
 
   auto &PR = *PassRegistry::getPassRegistry();
   initializeAVRExpandPseudoPass(PR);
-  initializeAVRRelaxMemPass(PR);
   initializeAVRShiftExpandPass(PR);
 }
 
 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
   return &SubTarget;
 }
 
 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
bool AVRPassConfig::addInstSelector() {
   addPass(createAVRISelDag(getAVRTargetMachine(), getOptLevel()));
   // Create the frame analyzer pass used by the PEI pass.
   addPass(createAVRFrameAnalyzerPass());
 
   return false;
 }
 
 void AVRPassConfig::addPreSched2() {
-  addPass(createAVRRelaxMemPass());
   addPass(createAVRExpandPseudoPass());
 }
 
 void AVRPassConfig::addPreEmitPass() {
   // Must run branch selection immediately preceding the asm printer.
   addPass(&BranchRelaxationPassID);
 }
 
 } // end of namespace llvm

llvm/lib/Target/AVR/CMakeLists.txt

 add_llvm_target(AVRCodeGen
   AVRAsmPrinter.cpp
   AVRExpandPseudoInsts.cpp
   AVRFrameLowering.cpp
   AVRInstrInfo.cpp
   AVRISelDAGToDAG.cpp
   AVRISelLowering.cpp
   AVRMCInstLower.cpp
-  AVRRelaxMemOperations.cpp
   AVRRegisterInfo.cpp
   AVRShiftExpand.cpp
   AVRSubtarget.cpp
   AVRTargetMachine.cpp
   AVRTargetObjectFile.cpp
 
   DEPENDS
   intrinsics_gen

llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir

-# RUN: llc -O0 -run-pass=avr-expand-pseudo  %s -o - | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
   define void @test() {
   entry:
     ret void
   }
 ...
 
 ---
 name:            test
 body: |
   bb.0.entry:
 
     ; CHECK-LABEL: test
 
-    ; CHECK:      STDPtrQRr $r29r28, 10, $r0
-    ; CHECK-NEXT: STDPtrQRr $r29r28, 11, $r1
+    ; Small displacement (<63):
+    ; CHECK:      STDPtrQRr $r29r28, 3, $r0
+    ; CHECK-NEXT: STDPtrQRr $r29r28, 4, $r1
+    STDWPtrQRr $r29r28, 3, $r1r0
 
-    STDWPtrQRr $r29r28, 10, $r1r0
+    ; Small displacement where the destination register is killed:
+    ; CHECK:      STDPtrQRr $r29r28, 3, $r0
+    ; CHECK-NEXT: STDPtrQRr killed $r29r28, 4, $r1
+    STDWPtrQRr killed $r29r28, 3, $r1r0
+
+    ; Small displacement where the source register is killed:
+    ; CHECK:      STDPtrQRr $r29r28, 3, killed $r0
+    ; CHECK-NEXT: STDPtrQRr $r29r28, 4, killed $r1
+    STDWPtrQRr $r29r28, 3, killed $r1r0
+
+    ; Small displacement, near the limit (=62):
+    ; CHECK:      STDPtrQRr $r29r28, 62, $r0
+    ; CHECK-NEXT: STDPtrQRr $r29r28, 63, $r1
+    STDWPtrQRr $r29r28, 62, $r1r0
+
+    ; Large displacement (>=63):
+    ; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
+    ; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
+    ; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
+    ; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+    ; CHECK-NEXT: STPtrRr $r29r28, $r0
+    ; CHECK-NEXT: STDPtrQRr $r29r28, 1, $r1
+    ; CHECK-NEXT: $r29 = POPRd implicit-def $sp, implicit $sp
+    ; CHECK-NEXT: $r28 = POPRd implicit-def $sp, implicit $sp
+    STDWPtrQRr $r29r28, 63, $r1r0
+
+    ; Large displacement where the destination register is killed:
+    ; CHECK: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
+    ; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+    ; CHECK-NEXT: STPtrRr $r29r28, $r0
+    ; CHECK-NEXT: STDPtrQRr $r29r28, 1, $r1
+    STDWPtrQRr killed $r29r28, 63, $r1r0
+
+    ; Large displacement where the source register is killed:
+    ; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
+    ; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
+    ; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
+    ; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+    ; CHECK-NEXT: STPtrRr $r29r28, killed $r0
+    ; CHECK-NEXT: STDPtrQRr $r29r28, 1, killed $r1
+    ; CHECK-NEXT: $r29 = POPRd implicit-def $sp, implicit $sp
+    ; CHECK-NEXT: $r28 = POPRd implicit-def $sp, implicit $sp
+    STDWPtrQRr $r29r28, 63, killed $r1r0
 ...

llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir

-# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - | FileCheck %s
-
---- |
-  target triple = "avr--"
-  define void @test() {
-  entry:
-    ret void
-  }
-...
-
----
-name:            test
-body: |
-  bb.0.entry:
-
-    ; CHECK-LABEL: test
-
-    ; We shouldn't expand things which already have 6-bit imms.
-    ; CHECK: STDWPtrQRr $r29r28, 63, $r1r0
-    STDWPtrQRr $r29r28, 63, $r1r0
-
-    ; We shouldn't expand things which already have 6-bit imms.
-    ; CHECK-NEXT: STDWPtrQRr $r29r28, 0, $r1r0
-    STDWPtrQRr $r29r28, 0, $r1r0
-
-    ; CHECK-NEXT: PUSHWRr $r29r28, implicit-def $sp, implicit $sp
-    ; CHECK-NEXT: $r29r28 = SBCIWRdK $r29r28, -64, implicit-def $sreg, implicit $sreg
-    ; CHECK-NEXT: STWPtrRr $r29r28, $r1r0
-    ; CHECK-NEXT: $r29r28 = POPWRd implicit-def $sp, implicit $sp
-    STDWPtrQRr $r29r28, 64, $r1r0
-...

llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn

sources = [
     "AVRAsmPrinter.cpp",
     "AVRExpandPseudoInsts.cpp",
     "AVRFrameLowering.cpp",
     "AVRISelDAGToDAG.cpp",
     "AVRISelLowering.cpp",
     "AVRInstrInfo.cpp",
     "AVRMCInstLower.cpp",
     "AVRRegisterInfo.cpp",
-    "AVRRelaxMemOperations.cpp",
     "AVRShiftExpand.cpp",
     "AVRSubtarget.cpp",
     "AVRTargetMachine.cpp",
     "AVRTargetObjectFile.cpp",
   ]
 }
 
 # This is a bit different from most build files: Due to this group