[LoongArch] Construct codegen infra and generate first add instruction.

[wangleiat]

Summary

This patch constructs codegen infra and successfully generate the first
'add' instruction. Add integer calling convention for fixed arguments which
are passed with general-purpose registers.

New test added here:

CodeGen/LoongArch/ir-instruction/add.ll

The test file is placed in a subdirectory because we will use
subdirctories to distinguish different categories of tests (e.g.
intrinsic, inline-asm ...)

[wangleiat]

Delete useless comments.
Change 'check-prefixes' to check-prefix, because only one check-prefix is needed in the current test.

[SixWeining]

Hi @MaskRay @xen0n @rengolin @myhsu,

The author (@wangleiat) of this patch is one of the LoongArch port developers from Loongson Inc. This patch has been reviewed internally before being uploaded. We hope you could raise more comments. Without your approval I will not commit it to github especially we are in an early stage.

Thanks,
Weining

[MaskRay]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

51

Consider using X macro here to avoid future boilerplate.

92

llvm_unreachable takes a string literal. Use "" instead of nullptr if you don't have a specific message.

102

Coding standard uses pre-increments.

142

Is 16 necessary?

Suggest SmallVector<CCValAssign> ArgLocs;.

158

return ... <= 2;

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

63

https://llvm.org/docs/CodingStandards.html#doxygen-use-in-documentation-comments
"Don’t duplicate function or class name at the beginning of the comment."

65

Prefer using to typedef.

Does llvm/CodeGen/CallingConvLower.h CCAssignFn work for you or you just want to remove the ISD::ArgFlagsTy argument?

llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp

39

In the majority of cases ! is omitted. https://llvm.org/docs/CodingStandards.html#error-and-warning-messages

40

llvm_unreachable does need a subsequent return.

llvm/test/CodeGen/LoongArch/ir-instruction/add.ll

2

--verify-machineinstrs is not necessary.

LLVM_ENABLE_EXPENSIVE_CHECKS=on builds default to --verify-machineinstrs unless the target sets isMachineVerifierClean to false.

[wangleiat]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

51

Good idea. Thanks, i will change that.

92

Thanks.

102

OK, thanks. It seems that i have to learn coding standards first. :)

142

OK. I will change that.

158

Thanks.

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

63

OK, i will remove it.

65

To define a target-specific function, the main reason is that more information needs to be passed to. For example, the abi information to be added in the future. (loongarch calling convention is very similar to risc-v.)

llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp

39

OK, thanks.

40

Thanks, i will remove it.

llvm/test/CodeGen/LoongArch/ir-instruction/add.ll

2

Thanks. I will remove them.

[wangleiat]

Fix coding style issues.

[SixWeining]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

57

redundant semicolon

[wangleiat]

Remove a useless ;

[wangleiat]

modify the wrong macro name

[SixWeining]

LGTM

[SixWeining]

This patch has been rebased and pushed. Thanks.

llvm/lib/Target/LoongArch/LoongArch.h

 //===-- LoongArch.h - Top-level interface for LoongArch ---------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the entry points for global functions defined in the LLVM
 // LoongArch back-end.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCH_H
 #define LLVM_LIB_TARGET_LOONGARCH_LOONGARCH_H
 
+#include "MCTargetDesc/LoongArchBaseInfo.h"
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
 class LoongArchTargetMachine;
 class AsmPrinter;
 class FunctionPass;
 class MCInst;
 class MCOperand;

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

 namespace llvm {
 class LoongArchSubtarget;
 struct LoongArchRegisterInfo;
 namespace LoongArchISD {
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
 
   // TODO: add more LoongArchISDs
+  RET,
 
 };
 } // namespace LoongArchISD
 
 class LoongArchTargetLowering : public TargetLowering {
   const LoongArchSubtarget &Subtarget;
 
 public:
   explicit LoongArchTargetLowering(const TargetMachine &TM,
                                    const LoongArchSubtarget &STI);
 
   const LoongArchSubtarget &getSubtarget() const { return Subtarget; }
+
+  // This method returns the name of a target specific DAG node.
+  const char *getTargetNodeName(unsigned Opcode) const override;
+
+  // Lower incoming arguments, copy physregs into vregs.
+  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
+                               bool IsVarArg,
+                               const SmallVectorImpl<ISD::InputArg> &Ins,
+                               const SDLoc &DL, SelectionDAG &DAG,
+                               SmallVectorImpl<SDValue> &InVals) const override;
+  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+                      bool IsVarArg,
+                      const SmallVectorImpl<ISD::OutputArg> &Outs,
+                      LLVMContext &Context) const override;
+  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
+                      const SmallVectorImpl<ISD::OutputArg> &Outs,
+                      const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
+                      SelectionDAG &DAG) const override;
+
+private:
+  /// Target-specific function used to lower LoongArch calling conventions.
+  typedef bool LoongArchCCAssignFn(unsigned ValNo, MVT ValVT,
+                                   CCValAssign::LocInfo LocInfo,
+                                   CCState &State);
+
+  void analyzeInputArgs(CCState &CCInfo,
+                        const SmallVectorImpl<ISD::InputArg> &Ins,
+                        LoongArchCCAssignFn Fn) const;
+  void analyzeOutputArgs(CCState &CCInfo,
+                         const SmallVectorImpl<ISD::OutputArg> &Outs,
+                         LoongArchCCAssignFn Fn) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
   computeRegisterProperties(STI.getRegisterInfo());
 
   setStackPointerRegisterToSaveRestore(LoongArch::R3);
 
   // Function alignments.
   const Align FunctionAlignment(4);
   setMinFunctionAlignment(FunctionAlignment);
 }
+
+const char *LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
+  switch ((LoongArchISD::NodeType)Opcode) {
+  case LoongArchISD::FIRST_NUMBER:
+    break;
+
+#define NODE_NAME_CASE(node)                                                   \
+  case LoongArchISD::node:                                                     \
+    return "LoongArchISD::" #node;
+
+    // TODO: Add more target-dependent nodes later.
+    NODE_NAME_CASE(RET)
+  }
+#undef HANDLE_NODE
+  return nullptr;
+}
+
+//===----------------------------------------------------------------------===//
+//                     Calling Convention Implementation
+//===----------------------------------------------------------------------===//
+// FIXME: Now, we only support CallingConv::C with fixed arguments which are
+// passed with integer registers.
+static const MCPhysReg ArgGPRs[] = {
+    LoongArch::R4, LoongArch::R5, LoongArch::R6,  LoongArch::R7,
+    LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11};
+
+// Implements the LoongArch calling convention. Returns true upon failure.
+static bool CC_LoongArch(unsigned ValNo, MVT ValVT,
+                         CCValAssign::LocInfo LocInfo, CCState &State) {
+  // Allocate to a register if possible.
+  Register Reg = State.AllocateReg(ArgGPRs);
+  if (Reg) {
+    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, ValVT, LocInfo));
+    return false;
+  }
+
+  // TODO: Handle arguments passed without register.
+  return true;
+}
+
+void LoongArchTargetLowering::analyzeInputArgs(
+    CCState &CCInfo, const SmallVectorImpl<ISD::InputArg> &Ins,
+    LoongArchCCAssignFn Fn) const {
+  for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
+    MVT ArgVT = Ins[i].VT;
+
+    if (Fn(i, ArgVT, CCValAssign::Full, CCInfo)) {
+      LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "
+                        << EVT(ArgVT).getEVTString() << '\n');
+      llvm_unreachable("");
+    }
+  }
+}
+
+void LoongArchTargetLowering::analyzeOutputArgs(
+    CCState &CCInfo, const SmallVectorImpl<ISD::OutputArg> &Outs,
+    LoongArchCCAssignFn Fn) const {
+  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
+    MVT ArgVT = Outs[i].VT;
+
+    if (Fn(i, ArgVT, CCValAssign::Full, CCInfo)) {
+      LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "
+                        << EVT(ArgVT).getEVTString() << "\n");
+      llvm_unreachable("");
+    }
+  }
+}
+
+static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain,
+                                const CCValAssign &VA, const SDLoc &DL,
+                                const LoongArchTargetLowering &TLI) {
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachineRegisterInfo &RegInfo = MF.getRegInfo();
+  EVT LocVT = VA.getLocVT();
+  const TargetRegisterClass *RC = TLI.getRegClassFor(LocVT.getSimpleVT());
+  Register VReg = RegInfo.createVirtualRegister(RC);
+  RegInfo.addLiveIn(VA.getLocReg(), VReg);
+
+  return DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
+}
+
+// Transform physical registers into virtual registers.
+SDValue LoongArchTargetLowering::LowerFormalArguments(
+    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
+    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
+    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
+
+  MachineFunction &MF = DAG.getMachineFunction();
+
+  switch (CallConv) {
+  default:
+    llvm_unreachable("Unsupported calling convention");
+  case CallingConv::C:
+    break;
+  }
+
+  // Assign locations to all of the incoming arguments.
+  SmallVector<CCValAssign> ArgLocs;
+  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
+
+  analyzeInputArgs(CCInfo, Ins, CC_LoongArch);
+
+  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
+    InVals.push_back(unpackFromRegLoc(DAG, Chain, ArgLocs[i], DL, *this));
+
+  return Chain;
+}
+
+bool LoongArchTargetLowering::CanLowerReturn(
+    CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+  // Any return value split in to more than two values can't be returned
+  // directly.
+  return Outs.size() <= 2;
+}
+
+SDValue LoongArchTargetLowering::LowerReturn(
+    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
+    const SmallVectorImpl<ISD::OutputArg> &Outs,
+    const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
+    SelectionDAG &DAG) const {
+  // Stores the assignment of the return value to a location.
+  SmallVector<CCValAssign> RVLocs;
+
+  // Info about the registers and stack slot.
+  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
+                 *DAG.getContext());
+
+  analyzeOutputArgs(CCInfo, Outs, CC_LoongArch);
+
+  SDValue Glue;
+  SmallVector<SDValue, 4> RetOps(1, Chain);
+
+  // Copy the result values into the output registers.
+  for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
+    CCValAssign &VA = RVLocs[i];
+    assert(VA.isRegLoc() && "Can only return in registers!");
+
+    // Handle a 'normal' return.
+    Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Glue);
+
+    // Guarantee that all emitted copies are stuck together.
+    Glue = Chain.getValue(1);
+    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
+  }
+
+  RetOps[0] = Chain; // Update chain.
+
+  // Add the glue node if we have it.
+  if (Glue.getNode())
+    RetOps.push_back(Glue);
+
+  return DAG.getNode(LoongArchISD::RET, DL, MVT::Other, RetOps);
+}

llvm/lib/Target/LoongArch/LoongArchInstrFormats.td

class LAInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
   let Size = 4;
   let OutOperandList = outs;
   let InOperandList = ins;
   let AsmString = asmstr;
   let Pattern = pattern;
 }
 
 // Pseudo instructions
-class Pseudo<dag outs, dag ins, string asmstr> : LAInst<outs, ins, asmstr> {
+class Pseudo<dag outs, dag ins, list<dag> pattern = [], string asmstr = "">
+    : LAInst<outs, ins, asmstr, pattern> {
   let isPseudo = 1;
+  let isCodeGenOnly = 1;
 }
 
 // 2R-type
 // <opcode | rj | rd>
 class Fmt2R<bits<22> op, dag outs, dag ins, string asmstr,
             list<dag> pattern = []> : LAInst<outs, ins, asmstr, pattern> {
   bits<5> rj;
   bits<5> rd;

llvm/lib/Target/LoongArch/LoongArchInstrInfo.h

 //=- LoongArchInstrInfo.h - LoongArch Instruction Information ---*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the LoongArch implementation of the TargetInstrInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
 #define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H
 
+#include "LoongArchRegisterInfo.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 
 #define GET_INSTRINFO_HEADER
 #include "LoongArchGenInstrInfo.inc"
 
 namespace llvm {
 
 class LoongArchSubtarget;
 
 class LoongArchInstrInfo : public LoongArchGenInstrInfo {
   const LoongArchSubtarget &STI;
 
 public:
   explicit LoongArchInstrInfo(LoongArchSubtarget &STI);
+
+  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+                   const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
+                   bool KillSrc) const override;
 };
 
 } // end namespace llvm
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHINSTRINFO_H

llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp

 //=- LoongArchInstrInfo.cpp - LoongArch Instruction Information -*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the LoongArch implementation of the TargetInstrInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "LoongArchInstrInfo.h"
+#include "LoongArch.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_CTOR_DTOR
 #include "LoongArchGenInstrInfo.inc"
 
 LoongArchInstrInfo::LoongArchInstrInfo(LoongArchSubtarget &STI)
     // FIXME: add CFSetup and CFDestroy Inst when we implement function call.
     : LoongArchGenInstrInfo(),
 
       STI(STI) {}
+
+void LoongArchInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
+                                     MachineBasicBlock::iterator MBBI,
+                                     const DebugLoc &DL, MCRegister DstReg,
+                                     MCRegister SrcReg, bool KillSrc) const {
+  if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
+    BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg)
+        .addReg(SrcReg, getKillRegState(KillSrc))
+        .addReg(LoongArch::R0);
+    return;
+  }
+
+  // TODO: Now, we only support GPR->GPR copies.
+  llvm_unreachable("LoongArch didn't implement copyPhysReg");
+}

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // LoongArch specific DAG Nodes.
 //===----------------------------------------------------------------------===//
 
 // TODO: Add LoongArch specific DAG Nodes
+// Target-dependent nodes.
+def loongarch_ret : SDNode<"LoongArchISD::RET", SDTNone,
+                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//
 class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass {
   let Name = prefix # "Imm" # width # suffix;
   let DiagnosticType = !strconcat("Invalid", Name);
   let RenderMethod = "addImmOperands";

 class PatGprImm_32<SDPatternOperator OpNode, LAInst Inst, Operand ImmOpnd>
     : Pat<(sext_inreg (OpNode GPR:$rj, ImmOpnd:$imm), i32),
           (Inst GPR:$rj, ImmOpnd:$imm)>;
 
 def : PatGprGpr<and, AND>;
 def : PatGprGpr<or, OR>;
 def : PatGprGpr<xor, XOR>;
 
+/// Branches and jumps
+
+let isBarrier = 1, isReturn = 1, isTerminator = 1 in
+def PseudoRET : Pseudo<(outs), (ins), [(loongarch_ret)]>,
+                PseudoInstExpansion<(JIRL R0, R1, 0)>;
+
 /// LA32 patterns
 
 let Predicates = [IsLA32] in {
 def : PatGprGpr<add, ADD_W>;
 def : PatGprImm<add, ADDI_W, simm12>;
 } // Predicates = [IsLA32]
 
 /// LA64 patterns

llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp

 #define DEBUG_TYPE "loongarch"
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchTarget() {
   // Register the target.
   RegisterTargetMachine<LoongArchTargetMachine> X(getTheLoongArch32Target());
   RegisterTargetMachine<LoongArchTargetMachine> Y(getTheLoongArch64Target());
 }
 
-// FIXME: This is just a placeholder to make current commit buildable. Body of
-// this function will be filled in later commits.
 static std::string computeDataLayout(const Triple &TT) {
-  std::string Ret;
-  Ret += "e";
-  return Ret;
+  if (TT.isArch64Bit())
+    return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
+  assert(TT.isArch32Bit() && "only LA32 and LA64 are currently supported");
+  return "e-m:e-p:32:32-i64:64-n32-S128";
 }
 
 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
                                            Optional<Reloc::Model> RM) {
   if (!RM.hasValue())
     return Reloc::Static;
   return *RM;
 }

llvm/test/CodeGen/LoongArch/ir-instruction/add.ll

+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=CHECK32
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=CHECK64
+
+define i32 @addRR(i32 %x, i32 %y) {
+; CHECK32-LABEL: addRR:
+; CHECK32:       # %bb.0: # %entry
+; CHECK32-NEXT:    add.w $a0, $a1, $a0
+; CHECK32-NEXT:    jirl $zero, $ra, 0
+;
+; CHECK64-LABEL: addRR:
+; CHECK64:       # %bb.0: # %entry
+; CHECK64-NEXT:    add.d $a0, $a1, $a0
+; CHECK64-NEXT:    jirl $zero, $ra, 0
+entry:
+  %add = add nsw i32 %y, %x
+  ret i32 %add
+}