[RISCV] Teach VSETVLI insertion that it doesn't need to insert vsetvli for vlm.v and vsm.v in some cases.

[jacquesguan]

Summary

Unit-stride mask load and store instructions also have EEW=8. So add them to the switch case to avoid redundant VSETVLI.

[craig.topper]

Test?

[craig.topper]

vlm and vsm instructions should be created with an SEW of 0 so they should be treated as MaskRegOp by the vsetvli pass.

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

 
 bool canSkipVSETVLIForLoadStore(const MachineInstr &MI,
                                 const VSETVLIInfo &Require,
                                 const VSETVLIInfo &CurInfo) {
   unsigned EEW;
   switch (MI.getOpcode()) {
   default:
     return false;
+  case RISCV::PseudoVSM_V_B1:
+  case RISCV::PseudoVSM_V_B2:
+  case RISCV::PseudoVSM_V_B4:
+  case RISCV::PseudoVSM_V_B8:
+  case RISCV::PseudoVSM_V_B16:
+  case RISCV::PseudoVSM_V_B32:
+  case RISCV::PseudoVSM_V_B64:
+  case RISCV::PseudoVLM_V_B1:
+  case RISCV::PseudoVLM_V_B2:
+  case RISCV::PseudoVLM_V_B4:
+  case RISCV::PseudoVLM_V_B8:
+  case RISCV::PseudoVLM_V_B16:
+  case RISCV::PseudoVLM_V_B32:
+  case RISCV::PseudoVLM_V_B64:
   case RISCV::PseudoVLE8_V_M1:
   case RISCV::PseudoVLE8_V_M1_MASK:
   case RISCV::PseudoVLE8_V_M2:
   case RISCV::PseudoVLE8_V_M2_MASK:
   case RISCV::PseudoVLE8_V_M4:
   case RISCV::PseudoVLE8_V_M4_MASK:
   case RISCV::PseudoVLE8_V_M8:
   case RISCV::PseudoVLE8_V_M8_MASK: