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Differential D121847

[OpaquePtr][ARM] Use elementtype on ldrex/ldaex/stlex/strex
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Authored by aeubanks on Mar 16 2022, 2:02 PM.

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nikic
Group Reviewers
Restricted Project
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rG2371c5a0e06d: [OpaquePtr][ARM] Use elementtype on ldrex/ldaex/stlex/strex
Summary

Includes verifier changes checking the elementtype, clang codegen
changes to emit the elementtype, and ISel changes using the elementtype.

Basically the same as D120527.

Diff Detail

Event Timeline

aeubanks created this revision.Mar 16 2022, 2:02 PM
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Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
aeubanks requested review of this revision.Mar 16 2022, 2:02 PM
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aeubanks added a reviewer: Restricted Project.Mar 16 2022, 2:03 PM
nikic accepted this revision.Mar 16 2022, 2:10 PM
nikic added a subscriber: nikic.

LGTM

This revision is now accepted and ready to land.Mar 16 2022, 2:10 PM
This revision was landed with ongoing or failed builds.Mar 16 2022, 2:13 PM
Closed by commit rG2371c5a0e06d: [OpaquePtr][ARM] Use elementtype on ldrex/ldaex/stlex/strex (authored by aeubanks). · Explain Why
This revision was automatically updated to reflect the committed changes.
aeubanks added a commit: rG2371c5a0e06d: [OpaquePtr][ARM] Use elementtype on ldrex/ldaex/stlex/strex.
Harbormaster completed remote builds in B154696: Diff 415968.Mar 16 2022, 2:56 PM

Revision Contents

PathSize
clang/
lib/
CodeGen/
19 lines
test/
CodeGen/
4 lines
44 lines
CodeGenCXX/
4 lines
llvm/
lib/
Bitcode/
Reader/
23 lines
IR/
9 lines
Target/
ARM/
22 lines
test/
Bitcode/
19 lines
CodeGen/
ARM/
12 lines
4 lines
54 lines
Transforms/
AtomicExpand/
ARM/
60 lines
24 lines
16 lines
Verifier/
19 lines

Diff 415982

clang/lib/CodeGen/CGBuiltin.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,690 Lines • ▼ Show 20 LinesValue *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,
} }
if (BuiltinID == ARM::BI__builtin_arm_ldrex || if (BuiltinID == ARM::BI__builtin_arm_ldrex ||
BuiltinID == ARM::BI__builtin_arm_ldaex) { BuiltinID == ARM::BI__builtin_arm_ldaex) {
Value *LoadAddr = EmitScalarExpr(E->getArg(0)); Value *LoadAddr = EmitScalarExpr(E->getArg(0));
QualType Ty = E->getType(); QualType Ty = E->getType();
llvm::Type *RealResTy = ConvertType(Ty); llvm::Type *RealResTy = ConvertType(Ty);
llvm::Type *PtrTy = llvm::IntegerType::get( llvm::Type *IntTy =
getLLVMContext(), getContext().getTypeSize(Ty))->getPointerTo(); llvm::IntegerType::get(getLLVMContext(), getContext().getTypeSize(Ty));
llvm::Type *PtrTy = IntTy->getPointerTo();
LoadAddr = Builder.CreateBitCast(LoadAddr, PtrTy); LoadAddr = Builder.CreateBitCast(LoadAddr, PtrTy);
Function *F = CGM.getIntrinsic(BuiltinID == ARM::BI__builtin_arm_ldaex Function *F = CGM.getIntrinsic(BuiltinID == ARM::BI__builtin_arm_ldaex
? Intrinsic::arm_ldaex ? Intrinsic::arm_ldaex
: Intrinsic::arm_ldrex, : Intrinsic::arm_ldrex,
PtrTy); PtrTy);
Value *Val = Builder.CreateCall(F, LoadAddr, "ldrex"); CallInst *Val = Builder.CreateCall(F, LoadAddr, "ldrex");
Val->addParamAttr(
0, Attribute::get(getLLVMContext(), Attribute::ElementType, IntTy));
if (RealResTy->isPointerTy()) if (RealResTy->isPointerTy())
return Builder.CreateIntToPtr(Val, RealResTy); return Builder.CreateIntToPtr(Val, RealResTy);
else { else {
llvm::Type *IntResTy = llvm::IntegerType::get( llvm::Type *IntResTy = llvm::IntegerType::get(
getLLVMContext(), CGM.getDataLayout().getTypeSizeInBits(RealResTy)); getLLVMContext(), CGM.getDataLayout().getTypeSizeInBits(RealResTy));
Val = Builder.CreateTruncOrBitCast(Val, IntResTy); return Builder.CreateBitCast(Builder.CreateTruncOrBitCast(Val, IntResTy),
return Builder.CreateBitCast(Val, RealResTy); RealResTy);
} }
} }
if (BuiltinID == ARM::BI__builtin_arm_strexd || if (BuiltinID == ARM::BI__builtin_arm_strexd ||
((BuiltinID == ARM::BI__builtin_arm_stlex || ((BuiltinID == ARM::BI__builtin_arm_stlex ||
BuiltinID == ARM::BI__builtin_arm_strex) && BuiltinID == ARM::BI__builtin_arm_strex) &&
getContext().getTypeSize(E->getArg(0)->getType()) == 64)) { getContext().getTypeSize(E->getArg(0)->getType()) == 64)) {
Function *F = CGM.getIntrinsic(BuiltinID == ARM::BI__builtin_arm_stlex Function *F = CGM.getIntrinsic(BuiltinID == ARM::BI__builtin_arm_stlex
Show All 33 Lines else {
StoreVal = Builder.CreateBitCast(StoreVal, IntTy); StoreVal = Builder.CreateBitCast(StoreVal, IntTy);
StoreVal = Builder.CreateZExtOrBitCast(StoreVal, Int32Ty); StoreVal = Builder.CreateZExtOrBitCast(StoreVal, Int32Ty);
} }
Function *F = CGM.getIntrinsic(BuiltinID == ARM::BI__builtin_arm_stlex Function *F = CGM.getIntrinsic(BuiltinID == ARM::BI__builtin_arm_stlex
? Intrinsic::arm_stlex ? Intrinsic::arm_stlex
: Intrinsic::arm_strex, : Intrinsic::arm_strex,
StoreAddr->getType()); StoreAddr->getType());
return Builder.CreateCall(F, {StoreVal, StoreAddr}, "strex");
CallInst *CI = Builder.CreateCall(F, {StoreVal, StoreAddr}, "strex");
CI->addParamAttr(
1, Attribute::get(getLLVMContext(), Attribute::ElementType, StoreTy));
return CI;
} }
if (BuiltinID == ARM::BI__builtin_arm_clrex) { if (BuiltinID == ARM::BI__builtin_arm_clrex) {
Function *F = CGM.getIntrinsic(Intrinsic::arm_clrex); Function *F = CGM.getIntrinsic(Intrinsic::arm_clrex);
return Builder.CreateCall(F); return Builder.CreateCall(F);
} }
// CRC32 // CRC32
▲ Show 20 Lines • Show All 11,299 Lines • Show Last 20 Lines

clang/test/CodeGen/arm_acle.c

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
#endif #endif
/* 8.5 Swap */ /* 8.5 Swap */
// AArch32-LABEL: @test_swp( // AArch32-LABEL: @test_swp(
// AArch32-NEXT: entry: // AArch32-NEXT: entry:
// AArch32-NEXT: [[TMP0:%.*]] = bitcast i8* [[P:%.*]] to i32* // AArch32-NEXT: [[TMP0:%.*]] = bitcast i8* [[P:%.*]] to i32*
// AArch32-NEXT: br label [[DO_BODY_I:%.*]] // AArch32-NEXT: br label [[DO_BODY_I:%.*]]
// AArch32: do.body.i: // AArch32: do.body.i:
// AArch32-NEXT: [[LDREX_I:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* [[TMP0]]) [[ATTR1]] // AArch32-NEXT: [[LDREX_I:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) [[TMP0]]) [[ATTR1]]
// AArch32-NEXT: [[STREX_I:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[X:%.*]], i32* [[TMP0]]) [[ATTR1]] // AArch32-NEXT: [[STREX_I:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[X:%.*]], i32* elementtype(i32) [[TMP0]]) [[ATTR1]]
// AArch32-NEXT: [[TOBOOL_I:%.*]] = icmp ne i32 [[STREX_I]], 0 // AArch32-NEXT: [[TOBOOL_I:%.*]] = icmp ne i32 [[STREX_I]], 0
// AArch32-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], [[LOOP3:!llvm.loop !.*]] // AArch32-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], [[LOOP3:!llvm.loop !.*]]
// AArch32: __swp.exit: // AArch32: __swp.exit:
// AArch32-NEXT: ret void // AArch32-NEXT: ret void
// //
// AArch64-LABEL: @test_swp( // AArch64-LABEL: @test_swp(
// AArch64-NEXT: entry: // AArch64-NEXT: entry:
// AArch64-NEXT: [[TMP0:%.*]] = bitcast i8* [[P:%.*]] to i32* // AArch64-NEXT: [[TMP0:%.*]] = bitcast i8* [[P:%.*]] to i32*
▲ Show 20 Lines • Show All 1,641 Lines • Show Last 20 Lines

clang/test/CodeGen/builtins-arm-exclusive.c

// RUN: %clang_cc1 -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// RUN: %clang_cc1 -Wall -Werror -triple arm64-apple-ios7.0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK-ARM64 // RUN: %clang_cc1 -Wall -Werror -triple arm64-apple-ios7.0 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK-ARM64
struct Simple { struct Simple {
char a, b; char a, b;
}; };
int test_ldrex(char *addr, long long *addr64, float *addrfloat) { int test_ldrex(char *addr, long long *addr64, float *addrfloat) {
// CHECK-LABEL: @test_ldrex // CHECK-LABEL: @test_ldrex
// CHECK-ARM64-LABEL: @test_ldrex // CHECK-ARM64-LABEL: @test_ldrex
int sum = 0; int sum = 0;
sum += __builtin_arm_ldrex(addr); sum += __builtin_arm_ldrex(addr);
// CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %addr) // CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %addr)
// CHECK: trunc i32 [[INTRES]] to i8 // CHECK: trunc i32 [[INTRES]] to i8
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i8(i8* elementtype(i8) %addr) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i8(i8* elementtype(i8) %addr)
// CHECK-ARM64: trunc i64 [[INTRES]] to i8 // CHECK-ARM64: trunc i64 [[INTRES]] to i8
sum += __builtin_arm_ldrex((short *)addr); sum += __builtin_arm_ldrex((short *)addr);
// CHECK: [[ADDR16:%.*]] = bitcast i8* %addr to i16* // CHECK: [[ADDR16:%.*]] = bitcast i8* %addr to i16*
// CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* [[ADDR16]]) // CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) [[ADDR16]])
// CHECK: trunc i32 [[INTRES]] to i16 // CHECK: trunc i32 [[INTRES]] to i16
// CHECK-ARM64: [[ADDR16:%.*]] = bitcast i8* %addr to i16* // CHECK-ARM64: [[ADDR16:%.*]] = bitcast i8* %addr to i16*
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i16(i16* elementtype(i16) [[ADDR16]]) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i16(i16* elementtype(i16) [[ADDR16]])
// CHECK-ARM64: trunc i64 [[INTRES]] to i16 // CHECK-ARM64: trunc i64 [[INTRES]] to i16
sum += __builtin_arm_ldrex((int *)addr); sum += __builtin_arm_ldrex((int *)addr);
// CHECK: [[ADDR32:%.*]] = bitcast i8* %addr to i32* // CHECK: [[ADDR32:%.*]] = bitcast i8* %addr to i32*
// CHECK: call i32 @llvm.arm.ldrex.p0i32(i32* [[ADDR32]]) // CHECK: call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) [[ADDR32]])
// CHECK-ARM64: [[ADDR32:%.*]] = bitcast i8* %addr to i32* // CHECK-ARM64: [[ADDR32:%.*]] = bitcast i8* %addr to i32*
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i32(i32* elementtype(i32) [[ADDR32]]) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i32(i32* elementtype(i32) [[ADDR32]])
// CHECK-ARM64: trunc i64 [[INTRES]] to i32 // CHECK-ARM64: trunc i64 [[INTRES]] to i32
sum += __builtin_arm_ldrex((long long *)addr); sum += __builtin_arm_ldrex((long long *)addr);
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to i64* // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to i64*
// CHECK: [[TMP5:%.*]] = bitcast i64* [[TMP4]] to i8* // CHECK: [[TMP5:%.*]] = bitcast i64* [[TMP4]] to i8*
// CHECK: call { i32, i32 } @llvm.arm.ldrexd(i8* [[TMP5]]) // CHECK: call { i32, i32 } @llvm.arm.ldrexd(i8* [[TMP5]])
// CHECK-ARM64: [[ADDR64:%.*]] = bitcast i8* %addr to i64* // CHECK-ARM64: [[ADDR64:%.*]] = bitcast i8* %addr to i64*
// CHECK-ARM64: call i64 @llvm.aarch64.ldxr.p0i64(i64* elementtype(i64) [[ADDR64]]) // CHECK-ARM64: call i64 @llvm.aarch64.ldxr.p0i64(i64* elementtype(i64) [[ADDR64]])
sum += __builtin_arm_ldrex(addr64); sum += __builtin_arm_ldrex(addr64);
// CHECK: [[ADDR64_AS8:%.*]] = bitcast i64* %addr64 to i8* // CHECK: [[ADDR64_AS8:%.*]] = bitcast i64* %addr64 to i8*
// CHECK: call { i32, i32 } @llvm.arm.ldrexd(i8* [[ADDR64_AS8]]) // CHECK: call { i32, i32 } @llvm.arm.ldrexd(i8* [[ADDR64_AS8]])
// CHECK-ARM64: call i64 @llvm.aarch64.ldxr.p0i64(i64* elementtype(i64) %addr64) // CHECK-ARM64: call i64 @llvm.aarch64.ldxr.p0i64(i64* elementtype(i64) %addr64)
sum += __builtin_arm_ldrex(addrfloat); sum += __builtin_arm_ldrex(addrfloat);
// CHECK: [[INTADDR:%.*]] = bitcast float* %addrfloat to i32* // CHECK: [[INTADDR:%.*]] = bitcast float* %addrfloat to i32*
// CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* [[INTADDR]]) // CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) [[INTADDR]])
// CHECK: bitcast i32 [[INTRES]] to float // CHECK: bitcast i32 [[INTRES]] to float
// CHECK-ARM64: [[INTADDR:%.*]] = bitcast float* %addrfloat to i32* // CHECK-ARM64: [[INTADDR:%.*]] = bitcast float* %addrfloat to i32*
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i32(i32* elementtype(i32) [[INTADDR]]) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i32(i32* elementtype(i32) [[INTADDR]])
// CHECK-ARM64: [[TRUNCRES:%.*]] = trunc i64 [[INTRES]] to i32 // CHECK-ARM64: [[TRUNCRES:%.*]] = trunc i64 [[INTRES]] to i32
// CHECK-ARM64: bitcast i32 [[TRUNCRES]] to float // CHECK-ARM64: bitcast i32 [[TRUNCRES]] to float
sum += __builtin_arm_ldrex((double *)addr); sum += __builtin_arm_ldrex((double *)addr);
Show All 11 Lines
// CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to double* // CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to double*
// CHECK-ARM64: [[TMP5:%.*]] = bitcast double* [[TMP4]] to i64* // CHECK-ARM64: [[TMP5:%.*]] = bitcast double* [[TMP4]] to i64*
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i64(i64* elementtype(i64) [[TMP5]]) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i64(i64* elementtype(i64) [[TMP5]])
// CHECK-ARM64: bitcast i64 [[INTRES]] to double // CHECK-ARM64: bitcast i64 [[INTRES]] to double
sum += *__builtin_arm_ldrex((int **)addr); sum += *__builtin_arm_ldrex((int **)addr);
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to i32** // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to i32**
// CHECK: [[TMP5:%.*]] = bitcast i32** [[TMP4]] to i32* // CHECK: [[TMP5:%.*]] = bitcast i32** [[TMP4]] to i32*
// CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* [[TMP5]]) // CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) [[TMP5]])
// CHECK: inttoptr i32 [[INTRES]] to i32* // CHECK: inttoptr i32 [[INTRES]] to i32*
// CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to i32** // CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to i32**
// CHECK-ARM64: [[TMP5:%.*]] = bitcast i32** [[TMP4]] to i64* // CHECK-ARM64: [[TMP5:%.*]] = bitcast i32** [[TMP4]] to i64*
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i64(i64* elementtype(i64) [[TMP5]]) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i64(i64* elementtype(i64) [[TMP5]])
// CHECK-ARM64: inttoptr i64 [[INTRES]] to i32* // CHECK-ARM64: inttoptr i64 [[INTRES]] to i32*
sum += __builtin_arm_ldrex((struct Simple **)addr)->a; sum += __builtin_arm_ldrex((struct Simple **)addr)->a;
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple** // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple**
// CHECK: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i32* // CHECK: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i32*
// CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* [[TMP5]]) // CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) [[TMP5]])
// CHECK: inttoptr i32 [[INTRES]] to %struct.Simple* // CHECK: inttoptr i32 [[INTRES]] to %struct.Simple*
// CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple** // CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple**
// CHECK-ARM64: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i64* // CHECK-ARM64: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i64*
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i64(i64* elementtype(i64) [[TMP5]]) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldxr.p0i64(i64* elementtype(i64) [[TMP5]])
// CHECK-ARM64: inttoptr i64 [[INTRES]] to %struct.Simple* // CHECK-ARM64: inttoptr i64 [[INTRES]] to %struct.Simple*
return sum; return sum;
} }
int test_ldaex(char *addr, long long *addr64, float *addrfloat) { int test_ldaex(char *addr, long long *addr64, float *addrfloat) {
// CHECK-LABEL: @test_ldaex // CHECK-LABEL: @test_ldaex
// CHECK-ARM64-LABEL: @test_ldaex // CHECK-ARM64-LABEL: @test_ldaex
int sum = 0; int sum = 0;
sum += __builtin_arm_ldaex(addr); sum += __builtin_arm_ldaex(addr);
// CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldaex.p0i8(i8* %addr) // CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldaex.p0i8(i8* elementtype(i8) %addr)
// CHECK: trunc i32 [[INTRES]] to i8 // CHECK: trunc i32 [[INTRES]] to i8
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i8(i8* elementtype(i8) %addr) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i8(i8* elementtype(i8) %addr)
// CHECK-ARM64: trunc i64 [[INTRES]] to i8 // CHECK-ARM64: trunc i64 [[INTRES]] to i8
sum += __builtin_arm_ldaex((short *)addr); sum += __builtin_arm_ldaex((short *)addr);
// CHECK: [[ADDR16:%.*]] = bitcast i8* %addr to i16* // CHECK: [[ADDR16:%.*]] = bitcast i8* %addr to i16*
// CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* [[ADDR16]]) // CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* elementtype(i16) [[ADDR16]])
// CHECK: trunc i32 [[INTRES]] to i16 // CHECK: trunc i32 [[INTRES]] to i16
// CHECK-ARM64: [[ADDR16:%.*]] = bitcast i8* %addr to i16* // CHECK-ARM64: [[ADDR16:%.*]] = bitcast i8* %addr to i16*
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i16(i16* elementtype(i16) [[ADDR16]]) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i16(i16* elementtype(i16) [[ADDR16]])
// CHECK-ARM64: [[TRUNCRES:%.*]] = trunc i64 [[INTRES]] to i16 // CHECK-ARM64: [[TRUNCRES:%.*]] = trunc i64 [[INTRES]] to i16
sum += __builtin_arm_ldaex((int *)addr); sum += __builtin_arm_ldaex((int *)addr);
// CHECK: [[ADDR32:%.*]] = bitcast i8* %addr to i32* // CHECK: [[ADDR32:%.*]] = bitcast i8* %addr to i32*
// CHECK: call i32 @llvm.arm.ldaex.p0i32(i32* [[ADDR32]]) // CHECK: call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32) [[ADDR32]])
// CHECK-ARM64: [[ADDR32:%.*]] = bitcast i8* %addr to i32* // CHECK-ARM64: [[ADDR32:%.*]] = bitcast i8* %addr to i32*
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i32(i32* elementtype(i32) [[ADDR32]]) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i32(i32* elementtype(i32) [[ADDR32]])
// CHECK-ARM64: trunc i64 [[INTRES]] to i32 // CHECK-ARM64: trunc i64 [[INTRES]] to i32
sum += __builtin_arm_ldaex((long long *)addr); sum += __builtin_arm_ldaex((long long *)addr);
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to i64* // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to i64*
// CHECK: [[TMP5:%.*]] = bitcast i64* [[TMP4]] to i8* // CHECK: [[TMP5:%.*]] = bitcast i64* [[TMP4]] to i8*
// CHECK: call { i32, i32 } @llvm.arm.ldaexd(i8* [[TMP5]]) // CHECK: call { i32, i32 } @llvm.arm.ldaexd(i8* [[TMP5]])
// CHECK-ARM64: [[ADDR64:%.*]] = bitcast i8* %addr to i64* // CHECK-ARM64: [[ADDR64:%.*]] = bitcast i8* %addr to i64*
// CHECK-ARM64: call i64 @llvm.aarch64.ldaxr.p0i64(i64* elementtype(i64) [[ADDR64]]) // CHECK-ARM64: call i64 @llvm.aarch64.ldaxr.p0i64(i64* elementtype(i64) [[ADDR64]])
sum += __builtin_arm_ldaex(addr64); sum += __builtin_arm_ldaex(addr64);
// CHECK: [[ADDR64_AS8:%.*]] = bitcast i64* %addr64 to i8* // CHECK: [[ADDR64_AS8:%.*]] = bitcast i64* %addr64 to i8*
// CHECK: call { i32, i32 } @llvm.arm.ldaexd(i8* [[ADDR64_AS8]]) // CHECK: call { i32, i32 } @llvm.arm.ldaexd(i8* [[ADDR64_AS8]])
// CHECK-ARM64: call i64 @llvm.aarch64.ldaxr.p0i64(i64* elementtype(i64) %addr64) // CHECK-ARM64: call i64 @llvm.aarch64.ldaxr.p0i64(i64* elementtype(i64) %addr64)
sum += __builtin_arm_ldaex(addrfloat); sum += __builtin_arm_ldaex(addrfloat);
// CHECK: [[INTADDR:%.*]] = bitcast float* %addrfloat to i32* // CHECK: [[INTADDR:%.*]] = bitcast float* %addrfloat to i32*
// CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* [[INTADDR]]) // CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32) [[INTADDR]])
// CHECK: bitcast i32 [[INTRES]] to float // CHECK: bitcast i32 [[INTRES]] to float
// CHECK-ARM64: [[INTADDR:%.*]] = bitcast float* %addrfloat to i32* // CHECK-ARM64: [[INTADDR:%.*]] = bitcast float* %addrfloat to i32*
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i32(i32* elementtype(i32) [[INTADDR]]) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i32(i32* elementtype(i32) [[INTADDR]])
// CHECK-ARM64: [[TRUNCRES:%.*]] = trunc i64 [[INTRES]] to i32 // CHECK-ARM64: [[TRUNCRES:%.*]] = trunc i64 [[INTRES]] to i32
// CHECK-ARM64: bitcast i32 [[TRUNCRES]] to float // CHECK-ARM64: bitcast i32 [[TRUNCRES]] to float
sum += __builtin_arm_ldaex((double *)addr); sum += __builtin_arm_ldaex((double *)addr);
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// CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to double* // CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to double*
// CHECK-ARM64: [[TMP5:%.*]] = bitcast double* [[TMP4]] to i64* // CHECK-ARM64: [[TMP5:%.*]] = bitcast double* [[TMP4]] to i64*
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i64(i64* elementtype(i64) [[TMP5]]) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i64(i64* elementtype(i64) [[TMP5]])
// CHECK-ARM64: bitcast i64 [[INTRES]] to double // CHECK-ARM64: bitcast i64 [[INTRES]] to double
sum += *__builtin_arm_ldaex((int **)addr); sum += *__builtin_arm_ldaex((int **)addr);
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to i32** // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to i32**
// CHECK: [[TMP5:%.*]] = bitcast i32** [[TMP4]] to i32* // CHECK: [[TMP5:%.*]] = bitcast i32** [[TMP4]] to i32*
// CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* [[TMP5]]) // CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32) [[TMP5]])
// CHECK: inttoptr i32 [[INTRES]] to i32* // CHECK: inttoptr i32 [[INTRES]] to i32*
// CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to i32** // CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to i32**
// CHECK-ARM64: [[TMP5:%.*]] = bitcast i32** [[TMP4]] to i64* // CHECK-ARM64: [[TMP5:%.*]] = bitcast i32** [[TMP4]] to i64*
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i64(i64* elementtype(i64) [[TMP5]]) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i64(i64* elementtype(i64) [[TMP5]])
// CHECK-ARM64: inttoptr i64 [[INTRES]] to i32* // CHECK-ARM64: inttoptr i64 [[INTRES]] to i32*
sum += __builtin_arm_ldaex((struct Simple **)addr)->a; sum += __builtin_arm_ldaex((struct Simple **)addr)->a;
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple** // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple**
// CHECK: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i32* // CHECK: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i32*
// CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* [[TMP5]]) // CHECK: [[INTRES:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32) [[TMP5]])
// CHECK: inttoptr i32 [[INTRES]] to %struct.Simple* // CHECK: inttoptr i32 [[INTRES]] to %struct.Simple*
// CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple** // CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple**
// CHECK-ARM64: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i64* // CHECK-ARM64: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i64*
// CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i64(i64* elementtype(i64) [[TMP5]]) // CHECK-ARM64: [[INTRES:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i64(i64* elementtype(i64) [[TMP5]])
// CHECK-ARM64: inttoptr i64 [[INTRES]] to %struct.Simple* // CHECK-ARM64: inttoptr i64 [[INTRES]] to %struct.Simple*
return sum; return sum;
} }
int test_strex(char *addr) { int test_strex(char *addr) {
// CHECK-LABEL: @test_strex // CHECK-LABEL: @test_strex
// CHECK-ARM64-LABEL: @test_strex // CHECK-ARM64-LABEL: @test_strex
int res = 0; int res = 0;
struct Simple var = {0}; struct Simple var = {0};
res |= __builtin_arm_strex(4, addr); res |= __builtin_arm_strex(4, addr);
// CHECK: call i32 @llvm.arm.strex.p0i8(i32 4, i8* %addr) // CHECK: call i32 @llvm.arm.strex.p0i8(i32 4, i8* elementtype(i8) %addr)
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i8(i64 4, i8* elementtype(i8) %addr) // CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i8(i64 4, i8* elementtype(i8) %addr)
res |= __builtin_arm_strex(42, (short *)addr); res |= __builtin_arm_strex(42, (short *)addr);
// CHECK: [[ADDR16:%.*]] = bitcast i8* %addr to i16* // CHECK: [[ADDR16:%.*]] = bitcast i8* %addr to i16*
// CHECK: call i32 @llvm.arm.strex.p0i16(i32 42, i16* [[ADDR16]]) // CHECK: call i32 @llvm.arm.strex.p0i16(i32 42, i16* elementtype(i16) [[ADDR16]])
// CHECK-ARM64: [[ADDR16:%.*]] = bitcast i8* %addr to i16* // CHECK-ARM64: [[ADDR16:%.*]] = bitcast i8* %addr to i16*
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i16(i64 42, i16* elementtype(i16) [[ADDR16]]) // CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i16(i64 42, i16* elementtype(i16) [[ADDR16]])
res |= __builtin_arm_strex(42, (int *)addr); res |= __builtin_arm_strex(42, (int *)addr);
// CHECK: [[ADDR32:%.*]] = bitcast i8* %addr to i32* // CHECK: [[ADDR32:%.*]] = bitcast i8* %addr to i32*
// CHECK: call i32 @llvm.arm.strex.p0i32(i32 42, i32* [[ADDR32]]) // CHECK: call i32 @llvm.arm.strex.p0i32(i32 42, i32* elementtype(i32) [[ADDR32]])
// CHECK-ARM64: [[ADDR32:%.*]] = bitcast i8* %addr to i32* // CHECK-ARM64: [[ADDR32:%.*]] = bitcast i8* %addr to i32*
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i32(i64 42, i32* elementtype(i32) [[ADDR32]]) // CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i32(i64 42, i32* elementtype(i32) [[ADDR32]])
res |= __builtin_arm_strex(42, (long long *)addr); res |= __builtin_arm_strex(42, (long long *)addr);
// CHECK: store i64 42, i64* [[TMP:%.*]], align 8 // CHECK: store i64 42, i64* [[TMP:%.*]], align 8
// CHECK: [[LOHI_ADDR:%.*]] = bitcast i64* [[TMP]] to { i32, i32 }* // CHECK: [[LOHI_ADDR:%.*]] = bitcast i64* [[TMP]] to { i32, i32 }*
// CHECK: [[LOHI:%.*]] = load { i32, i32 }, { i32, i32 }* [[LOHI_ADDR]] // CHECK: [[LOHI:%.*]] = load { i32, i32 }, { i32, i32 }* [[LOHI_ADDR]]
// CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 // CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0
// CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 // CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to i64* // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to i64*
// CHECK: [[TMP5:%.*]] = bitcast i64* [[TMP4]] to i8* // CHECK: [[TMP5:%.*]] = bitcast i64* [[TMP4]] to i8*
// CHECK: call i32 @llvm.arm.strexd(i32 [[LO]], i32 [[HI]], i8* [[TMP5]]) // CHECK: call i32 @llvm.arm.strexd(i32 [[LO]], i32 [[HI]], i8* [[TMP5]])
// CHECK-ARM64: [[ADDR64:%.*]] = bitcast i8* %addr to i64* // CHECK-ARM64: [[ADDR64:%.*]] = bitcast i8* %addr to i64*
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i64(i64 42, i64* elementtype(i64) [[ADDR64]]) // CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i64(i64 42, i64* elementtype(i64) [[ADDR64]])
res |= __builtin_arm_strex(2.71828f, (float *)addr); res |= __builtin_arm_strex(2.71828f, (float *)addr);
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to float* // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to float*
// CHECK: [[TMP5:%.*]] = bitcast float* [[TMP4]] to i32* // CHECK: [[TMP5:%.*]] = bitcast float* [[TMP4]] to i32*
// CHECK: call i32 @llvm.arm.strex.p0i32(i32 1076754509, i32* [[TMP5]]) // CHECK: call i32 @llvm.arm.strex.p0i32(i32 1076754509, i32* elementtype(i32) [[TMP5]])
// CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to float* // CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to float*
// CHECK-ARM64: [[TMP5:%.*]] = bitcast float* [[TMP4]] to i32* // CHECK-ARM64: [[TMP5:%.*]] = bitcast float* [[TMP4]] to i32*
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i32(i64 1076754509, i32* elementtype(i32) [[TMP5]]) // CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i32(i64 1076754509, i32* elementtype(i32) [[TMP5]])
res |= __builtin_arm_strex(3.14159, (double *)addr); res |= __builtin_arm_strex(3.14159, (double *)addr);
// CHECK: store double 3.141590e+00, double* [[TMP:%.*]], align 8 // CHECK: store double 3.141590e+00, double* [[TMP:%.*]], align 8
// CHECK: [[LOHI_ADDR:%.*]] = bitcast double* [[TMP]] to { i32, i32 }* // CHECK: [[LOHI_ADDR:%.*]] = bitcast double* [[TMP]] to { i32, i32 }*
// CHECK: [[LOHI:%.*]] = load { i32, i32 }, { i32, i32 }* [[LOHI_ADDR]] // CHECK: [[LOHI:%.*]] = load { i32, i32 }, { i32, i32 }* [[LOHI_ADDR]]
// CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 // CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0
// CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 // CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to double* // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to double*
// CHECK: [[TMP5:%.*]] = bitcast double* [[TMP4]] to i8* // CHECK: [[TMP5:%.*]] = bitcast double* [[TMP4]] to i8*
// CHECK: call i32 @llvm.arm.strexd(i32 [[LO]], i32 [[HI]], i8* [[TMP5]]) // CHECK: call i32 @llvm.arm.strexd(i32 [[LO]], i32 [[HI]], i8* [[TMP5]])
// CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to double* // CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to double*
// CHECK-ARM64: [[TMP5:%.*]] = bitcast double* [[TMP4]] to i64* // CHECK-ARM64: [[TMP5:%.*]] = bitcast double* [[TMP4]] to i64*
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i64(i64 4614256650576692846, i64* elementtype(i64) [[TMP5]]) // CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i64(i64 4614256650576692846, i64* elementtype(i64) [[TMP5]])
res |= __builtin_arm_strex(&var, (struct Simple **)addr); res |= __builtin_arm_strex(&var, (struct Simple **)addr);
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple** // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple**
// CHECK: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i32* // CHECK: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i32*
// CHECK: [[INTVAL:%.*]] = ptrtoint %struct.Simple* %var to i32 // CHECK: [[INTVAL:%.*]] = ptrtoint %struct.Simple* %var to i32
// CHECK: call i32 @llvm.arm.strex.p0i32(i32 [[INTVAL]], i32* [[TMP5]]) // CHECK: call i32 @llvm.arm.strex.p0i32(i32 [[INTVAL]], i32* elementtype(i32) [[TMP5]])
// CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple** // CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple**
// CHECK-ARM64: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i64* // CHECK-ARM64: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i64*
// CHECK-ARM64: [[INTVAL:%.*]] = ptrtoint %struct.Simple* %var to i64 // CHECK-ARM64: [[INTVAL:%.*]] = ptrtoint %struct.Simple* %var to i64
// CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i64(i64 [[INTVAL]], i64* elementtype(i64) [[TMP5]]) // CHECK-ARM64: call i32 @llvm.aarch64.stxr.p0i64(i64 [[INTVAL]], i64* elementtype(i64) [[TMP5]])
return res; return res;
} }
int test_stlex(char *addr) { int test_stlex(char *addr) {
// CHECK-LABEL: @test_stlex // CHECK-LABEL: @test_stlex
// CHECK-ARM64-LABEL: @test_stlex // CHECK-ARM64-LABEL: @test_stlex
int res = 0; int res = 0;
struct Simple var = {0}; struct Simple var = {0};
res |= __builtin_arm_stlex(4, addr); res |= __builtin_arm_stlex(4, addr);
// CHECK: call i32 @llvm.arm.stlex.p0i8(i32 4, i8* %addr) // CHECK: call i32 @llvm.arm.stlex.p0i8(i32 4, i8* elementtype(i8) %addr)
// CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i8(i64 4, i8* elementtype(i8) %addr) // CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i8(i64 4, i8* elementtype(i8) %addr)
res |= __builtin_arm_stlex(42, (short *)addr); res |= __builtin_arm_stlex(42, (short *)addr);
// CHECK: [[ADDR16:%.*]] = bitcast i8* %addr to i16* // CHECK: [[ADDR16:%.*]] = bitcast i8* %addr to i16*
// CHECK: call i32 @llvm.arm.stlex.p0i16(i32 42, i16* [[ADDR16]]) // CHECK: call i32 @llvm.arm.stlex.p0i16(i32 42, i16* elementtype(i16) [[ADDR16]])
// CHECK-ARM64: [[ADDR16:%.*]] = bitcast i8* %addr to i16* // CHECK-ARM64: [[ADDR16:%.*]] = bitcast i8* %addr to i16*
// CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i16(i64 42, i16* elementtype(i16) [[ADDR16]]) // CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i16(i64 42, i16* elementtype(i16) [[ADDR16]])
res |= __builtin_arm_stlex(42, (int *)addr); res |= __builtin_arm_stlex(42, (int *)addr);
// CHECK: [[ADDR32:%.*]] = bitcast i8* %addr to i32* // CHECK: [[ADDR32:%.*]] = bitcast i8* %addr to i32*
// CHECK: call i32 @llvm.arm.stlex.p0i32(i32 42, i32* [[ADDR32]]) // CHECK: call i32 @llvm.arm.stlex.p0i32(i32 42, i32* elementtype(i32) [[ADDR32]])
// CHECK-ARM64: [[ADDR32:%.*]] = bitcast i8* %addr to i32* // CHECK-ARM64: [[ADDR32:%.*]] = bitcast i8* %addr to i32*
// CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i32(i64 42, i32* elementtype(i32) [[ADDR32]]) // CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i32(i64 42, i32* elementtype(i32) [[ADDR32]])
res |= __builtin_arm_stlex(42, (long long *)addr); res |= __builtin_arm_stlex(42, (long long *)addr);
// CHECK: store i64 42, i64* [[TMP:%.*]], align 8 // CHECK: store i64 42, i64* [[TMP:%.*]], align 8
// CHECK: [[LOHI_ADDR:%.*]] = bitcast i64* [[TMP]] to { i32, i32 }* // CHECK: [[LOHI_ADDR:%.*]] = bitcast i64* [[TMP]] to { i32, i32 }*
// CHECK: [[LOHI:%.*]] = load { i32, i32 }, { i32, i32 }* [[LOHI_ADDR]] // CHECK: [[LOHI:%.*]] = load { i32, i32 }, { i32, i32 }* [[LOHI_ADDR]]
// CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 // CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0
// CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 // CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to i64* // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to i64*
// CHECK: [[TMP5:%.*]] = bitcast i64* [[TMP4]] to i8* // CHECK: [[TMP5:%.*]] = bitcast i64* [[TMP4]] to i8*
// CHECK: call i32 @llvm.arm.stlexd(i32 [[LO]], i32 [[HI]], i8* [[TMP5]]) // CHECK: call i32 @llvm.arm.stlexd(i32 [[LO]], i32 [[HI]], i8* [[TMP5]])
// CHECK-ARM64: [[ADDR64:%.*]] = bitcast i8* %addr to i64* // CHECK-ARM64: [[ADDR64:%.*]] = bitcast i8* %addr to i64*
// CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i64(i64 42, i64* elementtype(i64) [[ADDR64]]) // CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i64(i64 42, i64* elementtype(i64) [[ADDR64]])
res |= __builtin_arm_stlex(2.71828f, (float *)addr); res |= __builtin_arm_stlex(2.71828f, (float *)addr);
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to float* // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to float*
// CHECK: [[TMP5:%.*]] = bitcast float* [[TMP4]] to i32* // CHECK: [[TMP5:%.*]] = bitcast float* [[TMP4]] to i32*
// CHECK: call i32 @llvm.arm.stlex.p0i32(i32 1076754509, i32* [[TMP5]]) // CHECK: call i32 @llvm.arm.stlex.p0i32(i32 1076754509, i32* elementtype(i32) [[TMP5]])
// CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to float* // CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to float*
// CHECK-ARM64: [[TMP5:%.*]] = bitcast float* [[TMP4]] to i32* // CHECK-ARM64: [[TMP5:%.*]] = bitcast float* [[TMP4]] to i32*
// CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i32(i64 1076754509, i32* elementtype(i32) [[TMP5]]) // CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i32(i64 1076754509, i32* elementtype(i32) [[TMP5]])
res |= __builtin_arm_stlex(3.14159, (double *)addr); res |= __builtin_arm_stlex(3.14159, (double *)addr);
// CHECK: store double 3.141590e+00, double* [[TMP:%.*]], align 8 // CHECK: store double 3.141590e+00, double* [[TMP:%.*]], align 8
// CHECK: [[LOHI_ADDR:%.*]] = bitcast double* [[TMP]] to { i32, i32 }* // CHECK: [[LOHI_ADDR:%.*]] = bitcast double* [[TMP]] to { i32, i32 }*
// CHECK: [[LOHI:%.*]] = load { i32, i32 }, { i32, i32 }* [[LOHI_ADDR]] // CHECK: [[LOHI:%.*]] = load { i32, i32 }, { i32, i32 }* [[LOHI_ADDR]]
// CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 // CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0
// CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 // CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to double* // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to double*
// CHECK: [[TMP5:%.*]] = bitcast double* [[TMP4]] to i8* // CHECK: [[TMP5:%.*]] = bitcast double* [[TMP4]] to i8*
// CHECK: call i32 @llvm.arm.stlexd(i32 [[LO]], i32 [[HI]], i8* [[TMP5]]) // CHECK: call i32 @llvm.arm.stlexd(i32 [[LO]], i32 [[HI]], i8* [[TMP5]])
// CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to double* // CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to double*
// CHECK-ARM64: [[TMP5:%.*]] = bitcast double* [[TMP4]] to i64* // CHECK-ARM64: [[TMP5:%.*]] = bitcast double* [[TMP4]] to i64*
// CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i64(i64 4614256650576692846, i64* elementtype(i64) [[TMP5]]) // CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i64(i64 4614256650576692846, i64* elementtype(i64) [[TMP5]])
res |= __builtin_arm_stlex(&var, (struct Simple **)addr); res |= __builtin_arm_stlex(&var, (struct Simple **)addr);
// CHECK: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple** // CHECK: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple**
// CHECK: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i32* // CHECK: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i32*
// CHECK: [[INTVAL:%.*]] = ptrtoint %struct.Simple* %var to i32 // CHECK: [[INTVAL:%.*]] = ptrtoint %struct.Simple* %var to i32
// CHECK: call i32 @llvm.arm.stlex.p0i32(i32 [[INTVAL]], i32* [[TMP5]]) // CHECK: call i32 @llvm.arm.stlex.p0i32(i32 [[INTVAL]], i32* elementtype(i32) [[TMP5]])
// CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple** // CHECK-ARM64: [[TMP4:%.*]] = bitcast i8* %addr to %struct.Simple**
// CHECK-ARM64: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i64* // CHECK-ARM64: [[TMP5:%.*]] = bitcast %struct.Simple** [[TMP4]] to i64*
// CHECK-ARM64: [[INTVAL:%.*]] = ptrtoint %struct.Simple* %var to i64 // CHECK-ARM64: [[INTVAL:%.*]] = ptrtoint %struct.Simple* %var to i64
// CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i64(i64 [[INTVAL]], i64* elementtype(i64) [[TMP5]]) // CHECK-ARM64: call i32 @llvm.aarch64.stlxr.p0i64(i64 [[INTVAL]], i64* elementtype(i64) [[TMP5]])
return res; return res;
} }
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

clang/test/CodeGenCXX/builtins-arm-exclusive.cpp

// RUN: %clang_cc1 -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -Wall -Werror -triple arm64-apple-ios7.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARM64 // RUN: %clang_cc1 -Wall -Werror -triple arm64-apple-ios7.0 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARM64
bool b; bool b;
// CHECK-LABEL: @_Z10test_ldrexv() // CHECK-LABEL: @_Z10test_ldrexv()
// CHECK: call i32 @llvm.arm.ldrex.p0i8(i8* @b) // CHECK: call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) @b)
// CHECK-ARM64-LABEL: @_Z10test_ldrexv() // CHECK-ARM64-LABEL: @_Z10test_ldrexv()
// CHECK-ARM64: call i64 @llvm.aarch64.ldxr.p0i8(i8* elementtype(i8) @b) // CHECK-ARM64: call i64 @llvm.aarch64.ldxr.p0i8(i8* elementtype(i8) @b)
void test_ldrex() { void test_ldrex() {
b = __builtin_arm_ldrex(&b); b = __builtin_arm_ldrex(&b);
} }
// CHECK-LABEL: @_Z10tset_strexv() // CHECK-LABEL: @_Z10tset_strexv()
// CHECK: %{{.*}} = call i32 @llvm.arm.strex.p0i8(i32 1, i8* @b) // CHECK: %{{.*}} = call i32 @llvm.arm.strex.p0i8(i32 1, i8* elementtype(i8) @b)
// CHECK-ARM64-LABEL: @_Z10tset_strexv() // CHECK-ARM64-LABEL: @_Z10tset_strexv()
// CHECK-ARM64: %{{.*}} = call i32 @llvm.aarch64.stxr.p0i8(i64 1, i8* elementtype(i8) @b) // CHECK-ARM64: %{{.*}} = call i32 @llvm.aarch64.stxr.p0i8(i64 1, i8* elementtype(i8) @b)
void tset_strex() { void tset_strex() {
__builtin_arm_strex(true, &b); __builtin_arm_strex(true, &b);
} }

llvm/lib/Bitcode/Reader/BitcodeReader.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
#include "llvm/IR/GlobalVariable.h" #include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/InlineAsm.h" #include "llvm/IR/InlineAsm.h"
#include "llvm/IR/InstIterator.h" #include "llvm/IR/InstIterator.h"
#include "llvm/IR/InstrTypes.h" #include "llvm/IR/InstrTypes.h"
#include "llvm/IR/Instruction.h" #include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h" #include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h" #include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsAArch64.h" #include "llvm/IR/IntrinsicsAArch64.h"
#include "llvm/IR/IntrinsicsARM.h"
#include "llvm/IR/LLVMContext.h" #include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Metadata.h" #include "llvm/IR/Metadata.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/IR/ModuleSummaryIndex.h" #include "llvm/IR/ModuleSummaryIndex.h"
#include "llvm/IR/Operator.h" #include "llvm/IR/Operator.h"
#include "llvm/IR/Type.h" #include "llvm/IR/Type.h"
#include "llvm/IR/Value.h" #include "llvm/IR/Value.h"
#include "llvm/IR/Verifier.h" #include "llvm/IR/Verifier.h"
▲ Show 20 Lines • Show All 4,076 Lines • ▼ Show 20 LinesError BitcodeReader::propagateAttributeTypes(CallBase *CB,
} }
switch (CB->getIntrinsicID()) { switch (CB->getIntrinsicID()) {
case Intrinsic::preserve_array_access_index: case Intrinsic::preserve_array_access_index:
case Intrinsic::preserve_struct_access_index: case Intrinsic::preserve_struct_access_index:
case Intrinsic::aarch64_ldaxr: case Intrinsic::aarch64_ldaxr:
case Intrinsic::aarch64_ldxr: case Intrinsic::aarch64_ldxr:
case Intrinsic::aarch64_stlxr: case Intrinsic::aarch64_stlxr:
case Intrinsic::aarch64_stxr: { case Intrinsic::aarch64_stxr:
unsigned ArgNo = CB->getIntrinsicID() == Intrinsic::aarch64_stlxr || case Intrinsic::arm_ldaex:
CB->getIntrinsicID() == Intrinsic::aarch64_stxr case Intrinsic::arm_ldrex:
? 1 case Intrinsic::arm_stlex:
: 0; case Intrinsic::arm_strex: {
unsigned ArgNo;
switch (CB->getIntrinsicID()) {
case Intrinsic::aarch64_stlxr:
case Intrinsic::aarch64_stxr:
case Intrinsic::arm_stlex:
case Intrinsic::arm_strex:
ArgNo = 1;
break;
default:
ArgNo = 0;
break;
}
if (!Attrs.getParamElementType(ArgNo)) { if (!Attrs.getParamElementType(ArgNo)) {
Type *ElTy = getPtrElementTypeByID(ArgTyIDs[ArgNo]); Type *ElTy = getPtrElementTypeByID(ArgTyIDs[ArgNo]);
if (!ElTy) if (!ElTy)
return error("Missing element type for elementtype upgrade"); return error("Missing element type for elementtype upgrade");
Attribute NewAttr = Attribute::get(Context, Attribute::ElementType, ElTy); Attribute NewAttr = Attribute::get(Context, Attribute::ElementType, ElTy);
Attrs = Attrs.addParamAttribute(Context, ArgNo, NewAttr); Attrs = Attrs.addParamAttribute(Context, ArgNo, NewAttr);
} }
break; break;
▲ Show 20 Lines • Show All 3,365 Lines • Show Last 20 Lines

llvm/lib/IR/Verifier.cpp

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
#include "llvm/IR/InlineAsm.h" #include "llvm/IR/InlineAsm.h"
#include "llvm/IR/InstVisitor.h" #include "llvm/IR/InstVisitor.h"
#include "llvm/IR/InstrTypes.h" #include "llvm/IR/InstrTypes.h"
#include "llvm/IR/Instruction.h" #include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h" #include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h" #include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsAArch64.h" #include "llvm/IR/IntrinsicsAArch64.h"
#include "llvm/IR/IntrinsicsARM.h"
#include "llvm/IR/IntrinsicsWebAssembly.h" #include "llvm/IR/IntrinsicsWebAssembly.h"
#include "llvm/IR/LLVMContext.h" #include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Metadata.h" #include "llvm/IR/Metadata.h"
#include "llvm/IR/Module.h" #include "llvm/IR/Module.h"
#include "llvm/IR/ModuleSlotTracker.h" #include "llvm/IR/ModuleSlotTracker.h"
#include "llvm/IR/PassManager.h" #include "llvm/IR/PassManager.h"
#include "llvm/IR/Statepoint.h" #include "llvm/IR/Statepoint.h"
#include "llvm/IR/Type.h" #include "llvm/IR/Type.h"
▲ Show 20 Lines • Show All 5,422 Lines • ▼ Show 20 Lines#include "llvm/IR/ConstrainedOps.def"
} }
case Intrinsic::experimental_noalias_scope_decl: { case Intrinsic::experimental_noalias_scope_decl: {
NoAliasScopeDecls.push_back(cast<IntrinsicInst>(&Call)); NoAliasScopeDecls.push_back(cast<IntrinsicInst>(&Call));
break; break;
} }
case Intrinsic::preserve_array_access_index: case Intrinsic::preserve_array_access_index:
case Intrinsic::preserve_struct_access_index: case Intrinsic::preserve_struct_access_index:
case Intrinsic::aarch64_ldaxr: case Intrinsic::aarch64_ldaxr:
case Intrinsic::aarch64_ldxr: { case Intrinsic::aarch64_ldxr:
case Intrinsic::arm_ldaex:
case Intrinsic::arm_ldrex: {
Type *ElemTy = Call.getParamElementType(0); Type *ElemTy = Call.getParamElementType(0);
Assert(ElemTy, Assert(ElemTy,
"Intrinsic requires elementtype attribute on first argument.", "Intrinsic requires elementtype attribute on first argument.",
&Call); &Call);
break; break;
} }
case Intrinsic::aarch64_stlxr: case Intrinsic::aarch64_stlxr:
case Intrinsic::aarch64_stxr: { case Intrinsic::aarch64_stxr:
case Intrinsic::arm_stlex:
case Intrinsic::arm_strex: {
Type *ElemTy = Call.getAttributes().getParamElementType(1); Type *ElemTy = Call.getAttributes().getParamElementType(1);
Assert(ElemTy, Assert(ElemTy,
"Intrinsic requires elementtype attribute on second argument.", "Intrinsic requires elementtype attribute on second argument.",
&Call); &Call);
break; break;
} }
}; };
} }
▲ Show 20 Lines • Show All 919 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 20,801 Lines • ▼ Show 20 Lines Info.memVT = MVT::getVectorVT(MVT::getIntegerVT(MemSize),
DataVT.getVectorNumElements()); DataVT.getVectorNumElements());
Info.align = Align(1); Info.align = Align(1);
Info.flags |= MachineMemOperand::MOStore; Info.flags |= MachineMemOperand::MOStore;
return true; return true;
} }
case Intrinsic::arm_ldaex: case Intrinsic::arm_ldaex:
case Intrinsic::arm_ldrex: { case Intrinsic::arm_ldrex: {
auto &DL = I.getCalledFunction()->getParent()->getDataLayout(); auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType()); Type *ValTy = I.getParamElementType(0);
Info.opc = ISD::INTRINSIC_W_CHAIN; Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::getVT(PtrTy->getPointerElementType()); Info.memVT = MVT::getVT(ValTy);
Info.ptrVal = I.getArgOperand(0); Info.ptrVal = I.getArgOperand(0);
Info.offset = 0; Info.offset = 0;
Info.align = DL.getABITypeAlign(PtrTy->getPointerElementType()); Info.align = DL.getABITypeAlign(ValTy);
Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
return true; return true;
} }
case Intrinsic::arm_stlex: case Intrinsic::arm_stlex:
case Intrinsic::arm_strex: { case Intrinsic::arm_strex: {
auto &DL = I.getCalledFunction()->getParent()->getDataLayout(); auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType()); Type *ValTy = I.getParamElementType(1);
Info.opc = ISD::INTRINSIC_W_CHAIN; Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::getVT(PtrTy->getPointerElementType()); Info.memVT = MVT::getVT(ValTy);
Info.ptrVal = I.getArgOperand(1); Info.ptrVal = I.getArgOperand(1);
Info.offset = 0; Info.offset = 0;
Info.align = DL.getABITypeAlign(PtrTy->getPointerElementType()); Info.align = DL.getABITypeAlign(ValTy);
Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
return true; return true;
} }
case Intrinsic::arm_stlexd: case Intrinsic::arm_stlexd:
case Intrinsic::arm_strexd: case Intrinsic::arm_strexd:
Info.opc = ISD::INTRINSIC_W_CHAIN; Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::i64; Info.memVT = MVT::i64;
Info.ptrVal = I.getArgOperand(2); Info.ptrVal = I.getArgOperand(2);
▲ Show 20 Lines • Show All 278 Lines • ▼ Show 20 Lines if (ValueTy->getPrimitiveSizeInBits() == 64) {
Hi = Builder.CreateZExt(Hi, ValueTy, "hi64"); Hi = Builder.CreateZExt(Hi, ValueTy, "hi64");
return Builder.CreateOr( return Builder.CreateOr(
Lo, Builder.CreateShl(Hi, ConstantInt::get(ValueTy, 32)), "val64"); Lo, Builder.CreateShl(Hi, ConstantInt::get(ValueTy, 32)), "val64");
} }
Type *Tys[] = { Addr->getType() }; Type *Tys[] = { Addr->getType() };
Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex; Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
Function *Ldrex = Intrinsic::getDeclaration(M, Int, Tys); Function *Ldrex = Intrinsic::getDeclaration(M, Int, Tys);
CallInst *CI = Builder.CreateCall(Ldrex, Addr);
return Builder.CreateTruncOrBitCast(Builder.CreateCall(Ldrex, Addr), ValueTy); CI->addParamAttr(
0, Attribute::get(M->getContext(), Attribute::ElementType, ValueTy));
return Builder.CreateTruncOrBitCast(CI, ValueTy);
} }
void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance( void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
IRBuilderBase &Builder) const { IRBuilderBase &Builder) const {
if (!Subtarget->hasV7Ops()) if (!Subtarget->hasV7Ops())
return; return;
Module *M = Builder.GetInsertBlock()->getParent()->getParent(); Module *M = Builder.GetInsertBlock()->getParent()->getParent();
Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::arm_clrex)); Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::arm_clrex));
Show All 21 Lines if (Val->getType()->getPrimitiveSizeInBits() == 64) {
Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext())); Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
return Builder.CreateCall(Strex, {Lo, Hi, Addr}); return Builder.CreateCall(Strex, {Lo, Hi, Addr});
} }
Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex; Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
Type *Tys[] = { Addr->getType() }; Type *Tys[] = { Addr->getType() };
Function *Strex = Intrinsic::getDeclaration(M, Int, Tys); Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
return Builder.CreateCall( CallInst *CI = Builder.CreateCall(
Strex, {Builder.CreateZExtOrBitCast( Strex, {Builder.CreateZExtOrBitCast(
Val, Strex->getFunctionType()->getParamType(0)), Val, Strex->getFunctionType()->getParamType(0)),
Addr}); Addr});
CI->addParamAttr(1, Attribute::get(M->getContext(), Attribute::ElementType,
Val->getType()));
return CI;
} }
bool ARMTargetLowering::alignLoopsWithOptSize() const { bool ARMTargetLowering::alignLoopsWithOptSize() const {
return Subtarget->isMClass(); return Subtarget->isMClass();
} }
/// A helper function for determining the number of interleaved accesses we /// A helper function for determining the number of interleaved accesses we
▲ Show 20 Lines • Show All 512 Lines • Show Last 20 Lines

llvm/test/Bitcode/arm-intrinsics.bc

  • This binary file was added.

llvm/test/Bitcode/arm-intrinsics.ll

  • This file was added.
; RUN: llvm-dis < %S/arm-intrinsics.bc | FileCheck %s
define void @f(i32* %p) {
; CHECK: call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32)
%a = call i32 @llvm.arm.ldrex.p0i32(i32* %p)
; CHECK: call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32)
%c = call i32 @llvm.arm.strex.p0i32(i32 0, i32* %p)
; CHECK: call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32)
%a2 = call i32 @llvm.arm.ldaex.p0i32(i32* %p)
; CHECK: call i32 @llvm.arm.stlex.p0i32(i32 0, i32* elementtype(i32)
%c2 = call i32 @llvm.arm.stlex.p0i32(i32 0, i32* %p)
ret void
}
declare i32 @llvm.arm.ldrex.p0i32(i32*)
declare i32 @llvm.arm.ldaex.p0i32(i32*)
declare i32 @llvm.arm.stlex.p0i32(i32, i32*)
declare i32 @llvm.arm.strex.p0i32(i32, i32*)
No newline at end of file

llvm/test/CodeGen/ARM/ldaex-stlex.ll

Show All 30 Lines
declare %0 @llvm.arm.ldaexd(i8*) nounwind readonly declare %0 @llvm.arm.ldaexd(i8*) nounwind readonly
declare i32 @llvm.arm.stlexd(i32, i32, i8*) nounwind declare i32 @llvm.arm.stlexd(i32, i32, i8*) nounwind
; CHECK-LABEL: test_load_i8: ; CHECK-LABEL: test_load_i8:
; CHECK: ldaexb r0, [r0] ; CHECK: ldaexb r0, [r0]
; CHECK-NOT: uxtb ; CHECK-NOT: uxtb
; CHECK-NOT: and ; CHECK-NOT: and
define zeroext i8 @test_load_i8(i8* %addr) { define zeroext i8 @test_load_i8(i8* %addr) {
%val = call i32 @llvm.arm.ldaex.p0i8(i8* %addr) %val = call i32 @llvm.arm.ldaex.p0i8(i8* elementtype(i8) %addr)
%val8 = trunc i32 %val to i8 %val8 = trunc i32 %val to i8
ret i8 %val8 ret i8 %val8
} }
; CHECK-LABEL: test_load_i16: ; CHECK-LABEL: test_load_i16:
; CHECK: ldaexh r0, [r0] ; CHECK: ldaexh r0, [r0]
; CHECK-NOT: uxth ; CHECK-NOT: uxth
; CHECK-NOT: and ; CHECK-NOT: and
define zeroext i16 @test_load_i16(i16* %addr) { define zeroext i16 @test_load_i16(i16* %addr) {
%val = call i32 @llvm.arm.ldaex.p0i16(i16* %addr) %val = call i32 @llvm.arm.ldaex.p0i16(i16* elementtype(i16) %addr)
%val16 = trunc i32 %val to i16 %val16 = trunc i32 %val to i16
ret i16 %val16 ret i16 %val16
} }
; CHECK-LABEL: test_load_i32: ; CHECK-LABEL: test_load_i32:
; CHECK: ldaex r0, [r0] ; CHECK: ldaex r0, [r0]
define i32 @test_load_i32(i32* %addr) { define i32 @test_load_i32(i32* %addr) {
%val = call i32 @llvm.arm.ldaex.p0i32(i32* %addr) %val = call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32) %addr)
ret i32 %val ret i32 %val
} }
declare i32 @llvm.arm.ldaex.p0i8(i8*) nounwind readonly declare i32 @llvm.arm.ldaex.p0i8(i8*) nounwind readonly
declare i32 @llvm.arm.ldaex.p0i16(i16*) nounwind readonly declare i32 @llvm.arm.ldaex.p0i16(i16*) nounwind readonly
declare i32 @llvm.arm.ldaex.p0i32(i32*) nounwind readonly declare i32 @llvm.arm.ldaex.p0i32(i32*) nounwind readonly
; CHECK-LABEL: test_store_i8: ; CHECK-LABEL: test_store_i8:
; CHECK-NOT: uxtb ; CHECK-NOT: uxtb
; CHECK: stlexb r0, r1, [r2] ; CHECK: stlexb r0, r1, [r2]
define i32 @test_store_i8(i32, i8 %val, i8* %addr) { define i32 @test_store_i8(i32, i8 %val, i8* %addr) {
%extval = zext i8 %val to i32 %extval = zext i8 %val to i32
%res = call i32 @llvm.arm.stlex.p0i8(i32 %extval, i8* %addr) %res = call i32 @llvm.arm.stlex.p0i8(i32 %extval, i8* elementtype(i8) %addr)
ret i32 %res ret i32 %res
} }
; CHECK-LABEL: test_store_i16: ; CHECK-LABEL: test_store_i16:
; CHECK-NOT: uxth ; CHECK-NOT: uxth
; CHECK: stlexh r0, r1, [r2] ; CHECK: stlexh r0, r1, [r2]
define i32 @test_store_i16(i32, i16 %val, i16* %addr) { define i32 @test_store_i16(i32, i16 %val, i16* %addr) {
%extval = zext i16 %val to i32 %extval = zext i16 %val to i32
%res = call i32 @llvm.arm.stlex.p0i16(i32 %extval, i16* %addr) %res = call i32 @llvm.arm.stlex.p0i16(i32 %extval, i16* elementtype(i16) %addr)
ret i32 %res ret i32 %res
} }
; CHECK-LABEL: test_store_i32: ; CHECK-LABEL: test_store_i32:
; CHECK: stlex r0, r1, [r2] ; CHECK: stlex r0, r1, [r2]
define i32 @test_store_i32(i32, i32 %val, i32* %addr) { define i32 @test_store_i32(i32, i32 %val, i32* %addr) {
%res = call i32 @llvm.arm.stlex.p0i32(i32 %val, i32* %addr) %res = call i32 @llvm.arm.stlex.p0i32(i32 %val, i32* elementtype(i32) %addr)
ret i32 %res ret i32 %res
} }
declare i32 @llvm.arm.stlex.p0i8(i32, i8*) nounwind declare i32 @llvm.arm.stlex.p0i8(i32, i8*) nounwind
declare i32 @llvm.arm.stlex.p0i16(i32, i16*) nounwind declare i32 @llvm.arm.stlex.p0i16(i32, i16*) nounwind
declare i32 @llvm.arm.stlex.p0i32(i32, i32*) nounwind declare i32 @llvm.arm.stlex.p0i32(i32, i32*) nounwind

llvm/test/CodeGen/ARM/ldrex-frame-size.ll

Show All 10 Lines
define void @test_large_frame() { define void @test_large_frame() {
; CHECK-LABEL: test_large_frame: ; CHECK-LABEL: test_large_frame:
; CHECK: push ; CHECK: push
; CHECK: sub.w sp, sp, #1008 ; CHECK: sub.w sp, sp, #1008
%ptr = alloca i32, i32 252 %ptr = alloca i32, i32 252
%addr = getelementptr i32, i32* %ptr, i32 1 %addr = getelementptr i32, i32* %ptr, i32 1
call i32 @llvm.arm.ldrex.p0i32(i32* %addr) call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
ret void ret void
} }
; This alloca is just is just the other side of the limit, so no frame ; This alloca is just is just the other side of the limit, so no frame
define void @test_small_frame() { define void @test_small_frame() {
; CHECK-LABEL: test_small_frame: ; CHECK-LABEL: test_small_frame:
; CHECK-NOT: push ; CHECK-NOT: push
; CHECK: sub.w sp, sp, #1004 ; CHECK: sub.w sp, sp, #1004
%ptr = alloca i32, i32 251 %ptr = alloca i32, i32 251
%addr = getelementptr i32, i32* %ptr, i32 1 %addr = getelementptr i32, i32* %ptr, i32 1
call i32 @llvm.arm.ldrex.p0i32(i32* %addr) call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
ret void ret void
} }
declare i32 @llvm.arm.ldrex.p0i32(i32*) declare i32 @llvm.arm.ldrex.p0i32(i32*)

llvm/test/CodeGen/ARM/ldstrex.ll

Show All 32 Lines
declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly
declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
; CHECK-LABEL: test_load_i8: ; CHECK-LABEL: test_load_i8:
; CHECK: ldrexb r0, [r0] ; CHECK: ldrexb r0, [r0]
; CHECK-NOT: uxtb ; CHECK-NOT: uxtb
; CHECK-NOT: and ; CHECK-NOT: and
define zeroext i8 @test_load_i8(i8* %addr) { define zeroext i8 @test_load_i8(i8* %addr) {
%val = call i32 @llvm.arm.ldrex.p0i8(i8* %addr) %val = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %addr)
%val8 = trunc i32 %val to i8 %val8 = trunc i32 %val to i8
ret i8 %val8 ret i8 %val8
} }
; CHECK-LABEL: test_load_i16: ; CHECK-LABEL: test_load_i16:
; CHECK: ldrexh r0, [r0] ; CHECK: ldrexh r0, [r0]
; CHECK-NOT: uxth ; CHECK-NOT: uxth
; CHECK-NOT: and ; CHECK-NOT: and
define zeroext i16 @test_load_i16(i16* %addr) { define zeroext i16 @test_load_i16(i16* %addr) {
%val = call i32 @llvm.arm.ldrex.p0i16(i16* %addr) %val = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %addr)
%val16 = trunc i32 %val to i16 %val16 = trunc i32 %val to i16
ret i16 %val16 ret i16 %val16
} }
; CHECK-LABEL: test_load_i32: ; CHECK-LABEL: test_load_i32:
; CHECK: ldrex r0, [r0] ; CHECK: ldrex r0, [r0]
define i32 @test_load_i32(i32* %addr) { define i32 @test_load_i32(i32* %addr) {
%val = call i32 @llvm.arm.ldrex.p0i32(i32* %addr) %val = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
ret i32 %val ret i32 %val
} }
declare i32 @llvm.arm.ldrex.p0i8(i8*) nounwind readonly declare i32 @llvm.arm.ldrex.p0i8(i8*) nounwind readonly
declare i32 @llvm.arm.ldrex.p0i16(i16*) nounwind readonly declare i32 @llvm.arm.ldrex.p0i16(i16*) nounwind readonly
declare i32 @llvm.arm.ldrex.p0i32(i32*) nounwind readonly declare i32 @llvm.arm.ldrex.p0i32(i32*) nounwind readonly
; CHECK-LABEL: test_store_i8: ; CHECK-LABEL: test_store_i8:
; CHECK-NOT: uxtb ; CHECK-NOT: uxtb
; CHECK: strexb r0, r1, [r2] ; CHECK: strexb r0, r1, [r2]
define i32 @test_store_i8(i32, i8 %val, i8* %addr) { define i32 @test_store_i8(i32, i8 %val, i8* %addr) {
%extval = zext i8 %val to i32 %extval = zext i8 %val to i32
%res = call i32 @llvm.arm.strex.p0i8(i32 %extval, i8* %addr) %res = call i32 @llvm.arm.strex.p0i8(i32 %extval, i8* elementtype(i8) %addr)
ret i32 %res ret i32 %res
} }
; CHECK-LABEL: test_store_i16: ; CHECK-LABEL: test_store_i16:
; CHECK-NOT: uxth ; CHECK-NOT: uxth
; CHECK: strexh r0, r1, [r2] ; CHECK: strexh r0, r1, [r2]
define i32 @test_store_i16(i32, i16 %val, i16* %addr) { define i32 @test_store_i16(i32, i16 %val, i16* %addr) {
%extval = zext i16 %val to i32 %extval = zext i16 %val to i32
%res = call i32 @llvm.arm.strex.p0i16(i32 %extval, i16* %addr) %res = call i32 @llvm.arm.strex.p0i16(i32 %extval, i16* elementtype(i16) %addr)
ret i32 %res ret i32 %res
} }
; CHECK-LABEL: test_store_i32: ; CHECK-LABEL: test_store_i32:
; CHECK: strex r0, r1, [r2] ; CHECK: strex r0, r1, [r2]
define i32 @test_store_i32(i32, i32 %val, i32* %addr) { define i32 @test_store_i32(i32, i32 %val, i32* %addr) {
%res = call i32 @llvm.arm.strex.p0i32(i32 %val, i32* %addr) %res = call i32 @llvm.arm.strex.p0i32(i32 %val, i32* elementtype(i32) %addr)
ret i32 %res ret i32 %res
} }
declare i32 @llvm.arm.strex.p0i8(i32, i8*) nounwind declare i32 @llvm.arm.strex.p0i8(i32, i8*) nounwind
declare i32 @llvm.arm.strex.p0i16(i32, i16*) nounwind declare i32 @llvm.arm.strex.p0i16(i32, i16*) nounwind
declare i32 @llvm.arm.strex.p0i32(i32, i32*) nounwind declare i32 @llvm.arm.strex.p0i32(i32, i32*) nounwind
; CHECK-LABEL: test_clear: ; CHECK-LABEL: test_clear:
; CHECK: clrex ; CHECK: clrex
define void @test_clear() { define void @test_clear() {
call void @llvm.arm.clrex() call void @llvm.arm.clrex()
ret void ret void
} }
declare void @llvm.arm.clrex() nounwind declare void @llvm.arm.clrex() nounwind
@base = global i32* null @base = global i32* null
define void @excl_addrmode() { define void @excl_addrmode() {
; CHECK-T2ADDRMODE-LABEL: excl_addrmode: ; CHECK-T2ADDRMODE-LABEL: excl_addrmode:
%base1020 = load i32*, i32** @base %base1020 = load i32*, i32** @base
%offset1020 = getelementptr i32, i32* %base1020, i32 255 %offset1020 = getelementptr i32, i32* %base1020, i32 255
call i32 @llvm.arm.ldrex.p0i32(i32* %offset1020) call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %offset1020)
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1020) call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %offset1020)
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [{{r[0-9]+}}, #1020] ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [{{r[0-9]+}}, #1020]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}, #1020] ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}, #1020]
%base1024 = load i32*, i32** @base %base1024 = load i32*, i32** @base
%offset1024 = getelementptr i32, i32* %base1024, i32 256 %offset1024 = getelementptr i32, i32* %base1024, i32 256
call i32 @llvm.arm.ldrex.p0i32(i32* %offset1024) call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %offset1024)
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1024) call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %offset1024)
; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], {{r[0-9]+}}, #1024 ; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], {{r[0-9]+}}, #1024
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
%base1 = load i32*, i32** @base %base1 = load i32*, i32** @base
%addr8 = bitcast i32* %base1 to i8* %addr8 = bitcast i32* %base1 to i8*
%offset1_8 = getelementptr i8, i8* %addr8, i32 1 %offset1_8 = getelementptr i8, i8* %addr8, i32 1
%offset1 = bitcast i8* %offset1_8 to i32* %offset1 = bitcast i8* %offset1_8 to i32*
call i32 @llvm.arm.ldrex.p0i32(i32* %offset1) call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %offset1)
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1) call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %offset1)
; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #1 ; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #1
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
%local = alloca i8, i32 1024 %local = alloca i8, i32 1024
%local32 = bitcast i8* %local to i32* %local32 = bitcast i8* %local to i32*
call i32 @llvm.arm.ldrex.p0i32(i32* %local32) call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32)
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32) call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32)
; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp ; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
ret void ret void
} }
define void @test_excl_addrmode_folded() { define void @test_excl_addrmode_folded() {
; CHECK-LABEL: test_excl_addrmode_folded: ; CHECK-LABEL: test_excl_addrmode_folded:
%local = alloca i8, i32 4096 %local = alloca i8, i32 4096
%local.0 = getelementptr i8, i8* %local, i32 4 %local.0 = getelementptr i8, i8* %local, i32 4
%local32.0 = bitcast i8* %local.0 to i32* %local32.0 = bitcast i8* %local.0 to i32*
call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0) call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32.0)
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0) call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32.0)
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #4] ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #4]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #4] ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #4]
%local.1 = getelementptr i8, i8* %local, i32 1020 %local.1 = getelementptr i8, i8* %local, i32 1020
%local32.1 = bitcast i8* %local.1 to i32* %local32.1 = bitcast i8* %local.1 to i32*
call i32 @llvm.arm.ldrex.p0i32(i32* %local32.1) call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32.1)
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.1) call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32.1)
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #1020] ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #1020]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #1020] ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #1020]
ret void ret void
} }
define void @test_excl_addrmode_range() { define void @test_excl_addrmode_range() {
; CHECK-LABEL: test_excl_addrmode_range: ; CHECK-LABEL: test_excl_addrmode_range:
%local = alloca i8, i32 4096 %local = alloca i8, i32 4096
%local.0 = getelementptr i8, i8* %local, i32 1024 %local.0 = getelementptr i8, i8* %local, i32 1024
%local32.0 = bitcast i8* %local.0 to i32* %local32.0 = bitcast i8* %local.0 to i32*
call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0) call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32.0)
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0) call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32.0)
; CHECK-T2ADDRMODE: mov r[[TMP:[0-9]+]], sp ; CHECK-T2ADDRMODE: mov r[[TMP:[0-9]+]], sp
; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], r[[TMP]], #1024 ; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], r[[TMP]], #1024
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
ret void ret void
} }
define void @test_excl_addrmode_align() { define void @test_excl_addrmode_align() {
; CHECK-LABEL: test_excl_addrmode_align: ; CHECK-LABEL: test_excl_addrmode_align:
%local = alloca i8, i32 4096 %local = alloca i8, i32 4096
%local.0 = getelementptr i8, i8* %local, i32 2 %local.0 = getelementptr i8, i8* %local, i32 2
%local32.0 = bitcast i8* %local.0 to i32* %local32.0 = bitcast i8* %local.0 to i32*
call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0) call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32.0)
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0) call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32.0)
; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp ; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp
; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #2 ; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #2
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
ret void ret void
} }
define void @test_excl_addrmode_sign() { define void @test_excl_addrmode_sign() {
; CHECK-LABEL: test_excl_addrmode_sign: ; CHECK-LABEL: test_excl_addrmode_sign:
%local = alloca i8, i32 4096 %local = alloca i8, i32 4096
%local.0 = getelementptr i8, i8* %local, i32 -4 %local.0 = getelementptr i8, i8* %local, i32 -4
%local32.0 = bitcast i8* %local.0 to i32* %local32.0 = bitcast i8* %local.0 to i32*
call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0) call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32.0)
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0) call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32.0)
; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp ; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp
; CHECK-T2ADDRMODE: subs r[[ADDR:[0-9]+]], #4 ; CHECK-T2ADDRMODE: subs r[[ADDR:[0-9]+]], #4
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
ret void ret void
} }
define void @test_excl_addrmode_combination() { define void @test_excl_addrmode_combination() {
; CHECK-LABEL: test_excl_addrmode_combination: ; CHECK-LABEL: test_excl_addrmode_combination:
%local = alloca i8, i32 4096 %local = alloca i8, i32 4096
%unused = alloca i8, i32 64 %unused = alloca i8, i32 64
%local.0 = getelementptr i8, i8* %local, i32 4 %local.0 = getelementptr i8, i8* %local, i32 4
%local32.0 = bitcast i8* %local.0 to i32* %local32.0 = bitcast i8* %local.0 to i32*
call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0) call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %local32.0)
call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0) call i32 @llvm.arm.strex.p0i32(i32 0, i32* elementtype(i32) %local32.0)
; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #68] ; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #68]
; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #68] ; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #68]
ret void ret void
} }
; LLVM should know, even across basic blocks, that ldrex is setting the high ; LLVM should know, even across basic blocks, that ldrex is setting the high
; bits of its i32 to 0. There should be no zero-extend operation. ; bits of its i32 to 0. There should be no zero-extend operation.
define zeroext i8 @test_cross_block_zext_i8(i1 %tst, i8* %addr) { define zeroext i8 @test_cross_block_zext_i8(i1 %tst, i8* %addr) {
; CHECK: test_cross_block_zext_i8: ; CHECK: test_cross_block_zext_i8:
; CHECK-NOT: uxtb ; CHECK-NOT: uxtb
; CHECK-NOT: and ; CHECK-NOT: and
; CHECK: bx lr ; CHECK: bx lr
%val = call i32 @llvm.arm.ldrex.p0i8(i8* %addr) %val = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %addr)
br i1 %tst, label %end, label %mid br i1 %tst, label %end, label %mid
mid: mid:
ret i8 42 ret i8 42
end: end:
%val8 = trunc i32 %val to i8 %val8 = trunc i32 %val to i8
ret i8 %val8 ret i8 %val8
} }

llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll

; RUN: opt -S -o - -mtriple=armv7-apple-ios7.0 -atomic-expand -codegen-opt-level=1 %s | FileCheck %s ; RUN: opt -S -o - -mtriple=armv7-apple-ios7.0 -atomic-expand -codegen-opt-level=1 %s | FileCheck %s
define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) { define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) {
; CHECK-LABEL: @test_atomic_xchg_i8 ; CHECK-LABEL: @test_atomic_xchg_i8
; CHECK-NOT: dmb ; CHECK-NOT: dmb
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK-NOT: dmb ; CHECK-NOT: dmb
; CHECK: ret i8 [[OLDVAL]] ; CHECK: ret i8 [[OLDVAL]]
%res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic %res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic
ret i8 %res ret i8 %res
} }
define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) { define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) {
; CHECK-LABEL: @test_atomic_add_i16 ; CHECK-LABEL: @test_atomic_add_i16
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16
; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend ; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend
; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i16 [[OLDVAL]] ; CHECK: ret i16 [[OLDVAL]]
%res = atomicrmw add i16* %ptr, i16 %addend seq_cst %res = atomicrmw add i16* %ptr, i16 %addend seq_cst
ret i16 %res ret i16 %res
} }
define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) { define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) {
; CHECK-LABEL: @test_atomic_sub_i32 ; CHECK-LABEL: @test_atomic_sub_i32
; CHECK-NOT: dmb ; CHECK-NOT: dmb
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %ptr) ; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %ptr)
; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend ; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* elementtype(i32) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i32 [[OLDVAL]] ; CHECK: ret i32 [[OLDVAL]]
%res = atomicrmw sub i32* %ptr, i32 %subend acquire %res = atomicrmw sub i32* %ptr, i32 %subend acquire
ret i32 %res ret i32 %res
} }
define i8 @test_atomic_and_i8(i8* %ptr, i8 %andend) { define i8 @test_atomic_and_i8(i8* %ptr, i8 %andend) {
; CHECK-LABEL: @test_atomic_and_i8 ; CHECK-LABEL: @test_atomic_and_i8
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[NEWVAL:%.*]] = and i8 [[OLDVAL]], %andend ; CHECK: [[NEWVAL:%.*]] = and i8 [[OLDVAL]], %andend
; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK-NOT: dmb ; CHECK-NOT: dmb
; CHECK: ret i8 [[OLDVAL]] ; CHECK: ret i8 [[OLDVAL]]
%res = atomicrmw and i8* %ptr, i8 %andend release %res = atomicrmw and i8* %ptr, i8 %andend release
ret i8 %res ret i8 %res
} }
define i16 @test_atomic_nand_i16(i16* %ptr, i16 %nandend) { define i16 @test_atomic_nand_i16(i16* %ptr, i16 %nandend) {
; CHECK-LABEL: @test_atomic_nand_i16 ; CHECK-LABEL: @test_atomic_nand_i16
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16
; CHECK: [[NEWVAL_TMP:%.*]] = and i16 [[OLDVAL]], %nandend ; CHECK: [[NEWVAL_TMP:%.*]] = and i16 [[OLDVAL]], %nandend
; CHECK: [[NEWVAL:%.*]] = xor i16 [[NEWVAL_TMP]], -1 ; CHECK: [[NEWVAL:%.*]] = xor i16 [[NEWVAL_TMP]], -1
; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i16 [[OLDVAL]] ; CHECK: ret i16 [[OLDVAL]]
%res = atomicrmw nand i16* %ptr, i16 %nandend seq_cst %res = atomicrmw nand i16* %ptr, i16 %nandend seq_cst
ret i16 %res ret i16 %res
} }
Show All 26 Lines; CHECK: ret i64 [[OLDVAL]]
ret i64 %res ret i64 %res
} }
define i8 @test_atomic_xor_i8(i8* %ptr, i8 %xorend) { define i8 @test_atomic_xor_i8(i8* %ptr, i8 %xorend) {
; CHECK-LABEL: @test_atomic_xor_i8 ; CHECK-LABEL: @test_atomic_xor_i8
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[NEWVAL:%.*]] = xor i8 [[OLDVAL]], %xorend ; CHECK: [[NEWVAL:%.*]] = xor i8 [[OLDVAL]], %xorend
; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i8 [[OLDVAL]] ; CHECK: ret i8 [[OLDVAL]]
%res = atomicrmw xor i8* %ptr, i8 %xorend seq_cst %res = atomicrmw xor i8* %ptr, i8 %xorend seq_cst
ret i8 %res ret i8 %res
} }
define i8 @test_atomic_max_i8(i8* %ptr, i8 %maxend) { define i8 @test_atomic_max_i8(i8* %ptr, i8 %maxend) {
; CHECK-LABEL: @test_atomic_max_i8 ; CHECK-LABEL: @test_atomic_max_i8
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[WANT_OLD:%.*]] = icmp sgt i8 [[OLDVAL]], %maxend ; CHECK: [[WANT_OLD:%.*]] = icmp sgt i8 [[OLDVAL]], %maxend
; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %maxend ; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %maxend
; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i8 [[OLDVAL]] ; CHECK: ret i8 [[OLDVAL]]
%res = atomicrmw max i8* %ptr, i8 %maxend seq_cst %res = atomicrmw max i8* %ptr, i8 %maxend seq_cst
ret i8 %res ret i8 %res
} }
define i8 @test_atomic_min_i8(i8* %ptr, i8 %minend) { define i8 @test_atomic_min_i8(i8* %ptr, i8 %minend) {
; CHECK-LABEL: @test_atomic_min_i8 ; CHECK-LABEL: @test_atomic_min_i8
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[WANT_OLD:%.*]] = icmp sle i8 [[OLDVAL]], %minend ; CHECK: [[WANT_OLD:%.*]] = icmp sle i8 [[OLDVAL]], %minend
; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %minend ; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %minend
; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i8 [[OLDVAL]] ; CHECK: ret i8 [[OLDVAL]]
%res = atomicrmw min i8* %ptr, i8 %minend seq_cst %res = atomicrmw min i8* %ptr, i8 %minend seq_cst
ret i8 %res ret i8 %res
} }
define i8 @test_atomic_umax_i8(i8* %ptr, i8 %umaxend) { define i8 @test_atomic_umax_i8(i8* %ptr, i8 %umaxend) {
; CHECK-LABEL: @test_atomic_umax_i8 ; CHECK-LABEL: @test_atomic_umax_i8
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[WANT_OLD:%.*]] = icmp ugt i8 [[OLDVAL]], %umaxend ; CHECK: [[WANT_OLD:%.*]] = icmp ugt i8 [[OLDVAL]], %umaxend
; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %umaxend ; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %umaxend
; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i8 [[OLDVAL]] ; CHECK: ret i8 [[OLDVAL]]
%res = atomicrmw umax i8* %ptr, i8 %umaxend seq_cst %res = atomicrmw umax i8* %ptr, i8 %umaxend seq_cst
ret i8 %res ret i8 %res
} }
define i8 @test_atomic_umin_i8(i8* %ptr, i8 %uminend) { define i8 @test_atomic_umin_i8(i8* %ptr, i8 %uminend) {
; CHECK-LABEL: @test_atomic_umin_i8 ; CHECK-LABEL: @test_atomic_umin_i8
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[WANT_OLD:%.*]] = icmp ule i8 [[OLDVAL]], %uminend ; CHECK: [[WANT_OLD:%.*]] = icmp ule i8 [[OLDVAL]], %uminend
; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %uminend ; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %uminend
; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i8 [[OLDVAL]] ; CHECK: ret i8 [[OLDVAL]]
%res = atomicrmw umin i8* %ptr, i8 %uminend seq_cst %res = atomicrmw umin i8* %ptr, i8 %uminend seq_cst
ret i8 %res ret i8 %res
} }
define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) { define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst ; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst
; CHECK: br label %[[START:.*]] ; CHECK: br label %[[START:.*]]
; CHECK: [[START]]: ; CHECK: [[START]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
; CHECK: [[FENCED_STORE]]: ; CHECK: [[FENCED_STORE]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[LOADED_LOOP:%.*]] = phi i8 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ] ; CHECK: [[LOADED_LOOP:%.*]] = phi i8 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ]
; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD]] ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD]]
; CHECK: [[RELEASED_LOAD]]: ; CHECK: [[RELEASED_LOAD]]:
; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) ; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i8 ; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i8
; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i8 [[OLDVAL_LOOP]], %desired ; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i8 [[OLDVAL_LOOP]], %desired
; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]] ; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]]
; CHECK: [[SUCCESS_BB]]: ; CHECK: [[SUCCESS_BB]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[DONE:.*]] ; CHECK: br label %[[DONE:.*]]
Show All 17 Lines; CHECK: ret i8 [[LOADED]]
ret i8 %old ret i8 %old
} }
define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) { define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) {
; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic ; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16 ; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
; CHECK: [[FENCED_STORE]]: ; CHECK: [[FENCED_STORE]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[LOADED_LOOP:%.*]] = phi i16 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ] ; CHECK: [[LOADED_LOOP:%.*]] = phi i16 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ]
; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD:.*]] ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD:.*]]
; CHECK: [[RELEASED_LOAD]]: ; CHECK: [[RELEASED_LOAD]]:
; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr) ; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %ptr)
; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i16 ; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i16
; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i16 [[OLDVAL_LOOP]], %desired ; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i16 [[OLDVAL_LOOP]], %desired
; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]] ; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]]
; CHECK: [[SUCCESS_BB]]: ; CHECK: [[SUCCESS_BB]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[DONE:.*]] ; CHECK: br label %[[DONE:.*]]
Show All 18 Lines
} }
define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) { define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) {
; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire ; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire
; CHECK-NOT: dmb ; CHECK-NOT: dmb
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %ptr) ; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %ptr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
; CHECK: [[FENCED_STORE]]: ; CHECK: [[FENCED_STORE]]:
; CHECK-NEXT: br label %[[TRY_STORE:.*]] ; CHECK-NEXT: br label %[[TRY_STORE:.*]]
; CHECK: [[TRY_STORE]]: ; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[OLDVAL]], %[[FENCED_STORE]] ] ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[OLDVAL]], %[[FENCED_STORE]] ]
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* elementtype(i32) %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
; CHECK: [[SUCCESS_BB]]: ; CHECK: [[SUCCESS_BB]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[DONE:.*]] ; CHECK: br label %[[DONE:.*]]
; CHECK: [[NO_STORE_BB]]: ; CHECK: [[NO_STORE_BB]]:
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
} }
define i32 @test_cmpxchg_minsize(i32* %addr, i32 %desired, i32 %new) minsize { define i32 @test_cmpxchg_minsize(i32* %addr, i32 %desired, i32 %new) minsize {
; CHECK-LABEL: @test_cmpxchg_minsize ; CHECK-LABEL: @test_cmpxchg_minsize
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[START:.*]] ; CHECK: br label %[[START:.*]]
; CHECK: [[START]]: ; CHECK: [[START]]:
; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr) ; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
; CHECK: [[FENCED_STORE]]: ; CHECK: [[FENCED_STORE]]:
; CHECK-NEXT: br label %[[TRY_STORE:.*]] ; CHECK-NEXT: br label %[[TRY_STORE:.*]]
; CHECK: [[TRY_STORE]]: ; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ] ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ]
; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr) ; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr)
; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 ; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[START]] ; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[START]]
; CHECK: [[SUCCESS_BB]]: ; CHECK: [[SUCCESS_BB]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[END:.*]] ; CHECK: br label %[[END:.*]]
; CHECK: [[NO_STORE_BB]]: ; CHECK: [[NO_STORE_BB]]:
Show All 18 Lines

llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll

; RUN: opt -S -o - -mtriple=armv8-linux-gnueabihf -atomic-expand %s -codegen-opt-level=1 | FileCheck %s ; RUN: opt -S -o - -mtriple=armv8-linux-gnueabihf -atomic-expand %s -codegen-opt-level=1 | FileCheck %s
define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) { define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) {
; CHECK-LABEL: @test_atomic_xchg_i8 ; CHECK-LABEL: @test_atomic_xchg_i8
; CHECK-NOT: fence ; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK-NOT: fence ; CHECK-NOT: fence
; CHECK: ret i8 [[OLDVAL]] ; CHECK: ret i8 [[OLDVAL]]
%res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic %res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic
ret i8 %res ret i8 %res
} }
define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) { define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) {
; CHECK-LABEL: @test_atomic_add_i16 ; CHECK-LABEL: @test_atomic_add_i16
; CHECK-NOT: fence ; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* elementtype(i16) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16
; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend ; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend
; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK-NOT: fence ; CHECK-NOT: fence
; CHECK: ret i16 [[OLDVAL]] ; CHECK: ret i16 [[OLDVAL]]
%res = atomicrmw add i16* %ptr, i16 %addend seq_cst %res = atomicrmw add i16* %ptr, i16 %addend seq_cst
ret i16 %res ret i16 %res
} }
define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) { define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) {
; CHECK-LABEL: @test_atomic_sub_i32 ; CHECK-LABEL: @test_atomic_sub_i32
; CHECK-NOT: fence ; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* %ptr) ; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32) %ptr)
; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend ; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* elementtype(i32) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]: ; CHECK: [[END]]:
; CHECK-NOT: fence ; CHECK-NOT: fence
; CHECK: ret i32 [[OLDVAL]] ; CHECK: ret i32 [[OLDVAL]]
%res = atomicrmw sub i32* %ptr, i32 %subend acquire %res = atomicrmw sub i32* %ptr, i32 %subend acquire
ret i32 %res ret i32 %res
} }
Show All 27 Lines
} }
define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) { define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst ; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst
; CHECK-NOT: fence ; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i8(i8* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i8(i8* elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i8 ; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i8
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
; CHECK: [[FENCED_STORE]]: ; CHECK: [[FENCED_STORE]]:
; CHECK-NEXT: br label %[[TRY_STORE:.*]] ; CHECK-NEXT: br label %[[TRY_STORE:.*]]
; CHECK: [[TRY_STORE]]: ; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i8 [ [[OLDVAL]], %[[FENCED_STORE]] ] ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i8 [ [[OLDVAL]], %[[FENCED_STORE]] ]
; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i8(i32 [[NEWVAL32]], i8* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
; CHECK: [[SUCCESS_BB]]: ; CHECK: [[SUCCESS_BB]]:
; CHECK-NOT: fence_cst ; CHECK-NOT: fence_cst
; CHECK: br label %[[DONE:.*]] ; CHECK: br label %[[DONE:.*]]
; CHECK: [[NO_STORE_BB]]: ; CHECK: [[NO_STORE_BB]]:
Show All 17 Lines
} }
define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) { define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) {
; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic ; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic
; CHECK-NOT: fence ; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* %ptr) ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* elementtype(i16) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16 ; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
; CHECK: [[FENCED_STORE]]: ; CHECK: [[FENCED_STORE]]:
; CHECK-NEXT: br label %[[TRY_STORE:.*]] ; CHECK-NEXT: br label %[[TRY_STORE:.*]]
; CHECK: [[TRY_STORE]]: ; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i16 [ [[OLDVAL]], %[[FENCED_STORE]] ] ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i16 [ [[OLDVAL]], %[[FENCED_STORE]] ]
; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32 ; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
; CHECK: [[SUCCESS_BB]]: ; CHECK: [[SUCCESS_BB]]:
; CHECK-NOT: fence ; CHECK-NOT: fence
; CHECK: br label %[[DONE:.*]] ; CHECK: br label %[[DONE:.*]]
; CHECK: [[NO_STORE_BB]]: ; CHECK: [[NO_STORE_BB]]:
Show All 18 Lines
} }
define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) { define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) {
; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire ; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire
; CHECK-NOT: fence ; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]] ; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]: ; CHECK: [[LOOP]]:
; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* %ptr) ; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32) %ptr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
; CHECK: [[FENCED_STORE]]: ; CHECK: [[FENCED_STORE]]:
; CHECK-NEXT: br label %[[TRY_STORE:.*]] ; CHECK-NEXT: br label %[[TRY_STORE:.*]]
; CHECK: [[TRY_STORE]]: ; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[OLDVAL]], %[[FENCED_STORE]] ] ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[OLDVAL]], %[[FENCED_STORE]] ]
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* %ptr) ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* elementtype(i32) %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
; CHECK: [[SUCCESS_BB]]: ; CHECK: [[SUCCESS_BB]]:
; CHECK-NOT: fence_cst ; CHECK-NOT: fence_cst
; CHECK: br label %[[DONE:.*]] ; CHECK: br label %[[DONE:.*]]
; CHECK: [[NO_STORE_BB]]: ; CHECK: [[NO_STORE_BB]]:
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll

; RUN: opt -atomic-expand -codegen-opt-level=1 -S -mtriple=thumbv7s-apple-ios7.0 %s | FileCheck %s ; RUN: opt -atomic-expand -codegen-opt-level=1 -S -mtriple=thumbv7s-apple-ios7.0 %s | FileCheck %s
define i32 @test_cmpxchg_seq_cst(i32* %addr, i32 %desired, i32 %new) { define i32 @test_cmpxchg_seq_cst(i32* %addr, i32 %desired, i32 %new) {
; CHECK-LABEL: @test_cmpxchg_seq_cst ; CHECK-LABEL: @test_cmpxchg_seq_cst
; Intrinsic for "dmb ishst" is then expected ; Intrinsic for "dmb ishst" is then expected
; CHECK: br label %[[START:.*]] ; CHECK: br label %[[START:.*]]
; CHECK: [[START]]: ; CHECK: [[START]]:
; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr) ; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
; CHECK: [[FENCED_STORE]]: ; CHECK: [[FENCED_STORE]]:
; CHECK: call void @llvm.arm.dmb(i32 10) ; CHECK: call void @llvm.arm.dmb(i32 10)
; CHECK: br label %[[TRY_STORE:.*]] ; CHECK: br label %[[TRY_STORE:.*]]
; CHECK: [[TRY_STORE]]: ; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ] ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ]
; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr) ; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr)
; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 ; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]] ; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]]
; CHECK: [[SUCCESS_BB]]: ; CHECK: [[SUCCESS_BB]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[END:.*]] ; CHECK: br label %[[END:.*]]
; CHECK: [[NO_STORE_BB]]: ; CHECK: [[NO_STORE_BB]]:
Show All 16 Lines; CHECK: ret i32 [[LOADED_EXIT]]
ret i32 %oldval ret i32 %oldval
} }
define i1 @test_cmpxchg_weak_fail(i32* %addr, i32 %desired, i32 %new) { define i1 @test_cmpxchg_weak_fail(i32* %addr, i32 %desired, i32 %new) {
; CHECK-LABEL: @test_cmpxchg_weak_fail ; CHECK-LABEL: @test_cmpxchg_weak_fail
; CHECK: br label %[[START:.*]] ; CHECK: br label %[[START:.*]]
; CHECK: [[START]]: ; CHECK: [[START]]:
; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr) ; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
; CHECK: [[FENCED_STORE]]: ; CHECK: [[FENCED_STORE]]:
; CHECK: call void @llvm.arm.dmb(i32 10) ; CHECK: call void @llvm.arm.dmb(i32 10)
; CHECK: br label %[[TRY_STORE:.*]] ; CHECK: br label %[[TRY_STORE:.*]]
; CHECK: [[TRY_STORE]]: ; CHECK: [[TRY_STORE]]:
; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr) ; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr)
; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 ; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]] ; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]]
; CHECK: [[SUCCESS_BB]]: ; CHECK: [[SUCCESS_BB]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[END:.*]] ; CHECK: br label %[[END:.*]]
; CHECK: [[NO_STORE_BB]]: ; CHECK: [[NO_STORE_BB]]:
Show All 14 Lines
} }
define i32 @test_cmpxchg_monotonic(i32* %addr, i32 %desired, i32 %new) { define i32 @test_cmpxchg_monotonic(i32* %addr, i32 %desired, i32 %new) {
; CHECK-LABEL: @test_cmpxchg_monotonic ; CHECK-LABEL: @test_cmpxchg_monotonic
; CHECK-NOT: dmb ; CHECK-NOT: dmb
; CHECK: br label %[[START:.*]] ; CHECK: br label %[[START:.*]]
; CHECK: [[START]]: ; CHECK: [[START]]:
; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr) ; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
; CHECK: [[FENCED_STORE]]: ; CHECK: [[FENCED_STORE]]:
; CHECK-NEXT: br label %[[TRY_STORE]] ; CHECK-NEXT: br label %[[TRY_STORE]]
; CHECK: [[TRY_STORE]]: ; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ] ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ]
; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr) ; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr)
; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 ; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]] ; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]]
; CHECK: [[SUCCESS_BB]]: ; CHECK: [[SUCCESS_BB]]:
; CHECK-NOT: dmb ; CHECK-NOT: dmb
; CHECK: br label %[[END:.*]] ; CHECK: br label %[[END:.*]]
; CHECK: [[NO_STORE_BB]]: ; CHECK: [[NO_STORE_BB]]:
Show All 16 Lines; CHECK: ret i32 [[LOADED_EXIT]]
ret i32 %oldval ret i32 %oldval
} }
define i32 @test_cmpxchg_seq_cst_minsize(i32* %addr, i32 %desired, i32 %new) minsize { define i32 @test_cmpxchg_seq_cst_minsize(i32* %addr, i32 %desired, i32 %new) minsize {
; CHECK-LABEL: @test_cmpxchg_seq_cst_minsize ; CHECK-LABEL: @test_cmpxchg_seq_cst_minsize
; CHECK: br label %[[START:.*]] ; CHECK: br label %[[START:.*]]
; CHECK: [[START]]: ; CHECK: [[START]]:
; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr) ; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
; CHECK: [[FENCED_STORE]]: ; CHECK: [[FENCED_STORE]]:
; CHECK: call void @llvm.arm.dmb(i32 10) ; CHECK: call void @llvm.arm.dmb(i32 10)
; CHECK: br label %[[TRY_STORE:.*]] ; CHECK: br label %[[TRY_STORE:.*]]
; CHECK: [[TRY_STORE]]: ; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ] ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ]
; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr) ; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr)
; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 ; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]] ; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]]
; CHECK: [[SUCCESS_BB]]: ; CHECK: [[SUCCESS_BB]]:
; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[END:.*]] ; CHECK: br label %[[END:.*]]
; CHECK: [[NO_STORE_BB]]: ; CHECK: [[NO_STORE_BB]]:
Show All 18 Lines

llvm/test/Verifier/arm-intrinsics.ll

  • This file was added.
; RUN: not opt -passes=verify -S < %s 2>&1 | FileCheck %s
define void @f(i32* %p) {
; CHECK: Intrinsic requires elementtype attribute on first argument
%a = call i32 @llvm.arm.ldrex.p0i32(i32* %p)
; CHECK: Intrinsic requires elementtype attribute on second argument
%c = call i32 @llvm.arm.strex.p0i32(i32 0, i32* %p)
; CHECK: Intrinsic requires elementtype attribute on first argument
%a2 = call i32 @llvm.arm.ldaex.p0i32(i32* %p)
; CHECK: Intrinsic requires elementtype attribute on second argument
%c2 = call i32 @llvm.arm.stlex.p0i32(i32 0, i32* %p)
ret void
}
declare i32 @llvm.arm.ldrex.p0i32(i32*)
declare i32 @llvm.arm.ldaex.p0i32(i32*)
declare i32 @llvm.arm.stlex.p0i32(i32, i32*)
declare i32 @llvm.arm.strex.p0i32(i32, i32*)
No newline at end of file