Implement __aeabi_c{d,f}{cmpeq,cmple,rcmple}.

[jmgao]

Summary

Implement more missing ARM EABI runtime functions.

[compnerd]

lib/builtins/arm/aeabi_cdcmp.S

13

Is this actually portable? Can you rewrite this as:

__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__

or even:

__ARMEB__

14

Please replace FIXME with a slightly better message. How about something like:

#error big endian support not implemented

22

Did you mean the _helper here?

29

Please add a comment that as per the RTABI, this function *must* save/restore the core registers except ip, lr, and CPSR. And a note about lr since its not immediately obvious that it is for compactness.

32

Not a big fan of this helper name. It simply checks for NaNs.

34

Cant you hoist the pop {r0-r3} here?

40

Indicate that this is safe now since we have ruled out NaNs, so cmple can't trap.

84

Why not just swap and tail call?

lib/builtins/arm/aeabi_cdcmpeq_helper.c

13 ↗

(On Diff #32342)

Don't you need to check the mantissa to determine if it is a NaN?

lib/builtins/arm/aeabi_cfcmpeq_helper.c

13 ↗

(On Diff #32342)

Why the mask? Don't you need to check if the mantissa to determine if it is a NaN?

[srhines]

lib/builtins/arm/aeabi_cdcmp.S

21

Double comment on this line, and the rest of the lines are formatted strangely.

47

These comments don't match the implementation below, so something seems wrong.

lib/builtins/arm/aeabi_cdcmpeq_helper.c

19 ↗

(On Diff #32342)

Couldn't this be using __builtin_isnan instead of redefining it?

lib/builtins/arm/aeabi_cfcmpeq_helper.c

19 ↗

(On Diff #32342)

I have the same comment about using __builtin_isnan() here too.

[rengolin]

I agree with Stephen and Saleem on their comments, and I have some additional ones.

Also, avoid using push lr / pop pc, since this behaviour doesn't work across all ARM cores. There's a macro for returning that should be used.

cheers,
--renato

lib/builtins/arm/aeabi_cdcmp.S

21

you can move the comment up one line. Though, you may want to encode the logic in the example and avoid a comment.

32

me neither. If it's small enough, you can either write in asm or move to a separate static function in this file with a more descriptive name.

lib/builtins/arm/aeabi_cdcmpeq_helper.c

19 ↗

(On Diff #32342)

or even calling it directly from the asm function?

[jmgao]

Thanks for the comments, I'll fix them up and have an updated patch shortly

lib/builtins/arm/aeabi_cdcmp.S

13

Fixed

14

Fixed

34

Yep, done

40

Fixed

47

Oops, the comments are incorrect. Fixed

84

I misinterpreted the RTABI doc, I was applying the "3 way status returning functions preserve all registers except ip, lr, cpsr" to the reversed 3 way functions as well.

Fixed

test/builtins/Unit/arm/call_apsr.S

13

indentation broken here

[jmgao]

Oops, I somehow managed to overlook the Done checkbox in Phabricator.

[jmgao]

lib/builtins/arm/aeabi_cfcmp.S

14

This comment is wrong

[jmgao]

In D12089#226545, @rengolin wrote:

Also, avoid using push lr / pop pc, since this behaviour doesn't work across all ARM cores. There's a macro for returning that should be used.

Ugh, I didn't know that ARMv4's pop {pc} doesn't work with switching Thumb mode. Are there any other problems with that?

There are several other functions that use push {lr}, pop {pc}. What do you think about something along the lines of the following?

#if __ARM_ARCH > 4 || !defined(__ARM_ARCH_ISA_THUMB)
#define POP_FRAME(registers) \
    pop {registers, pc}
#else
#define POP_FRAME(registers) \
    pop {registers}          \
    pop {lr}                 \
    JMP(lr)
#endif

[jmgao]

Address most of the comments

lib/builtins/arm/aeabi_cdcmp.S

29

If I'm reading it correctly, this function is not actually required to preserve the argument registers, only the c?cmple ones are. We just happen to need them after checking for NaNs.

I added the comment to c?cmple.

32

Renamed it to __aeabi_cdcmpeq_check_nan

lib/builtins/arm/aeabi_cdcmpeq_helper.c

19 ↗

(On Diff #32342)

Doesn't __builtin_isnan do overloading via magic and/or generic macros? Is there an actual symbol I can jump to?

lib/builtins/arm/aeabi_cfcmpeq_helper.c

13 ↗

(On Diff #32342)

Yeah, this is wrong, I replaced it with a __builtin_nan instead

[srhines]

lib/builtins/arm/aeabi_cdcmpeq_helper.c

19 ↗

(On Diff #32342)

It looks like you resolved the issue here (by calling through with the appropriate C type). Was this just a stale reply?

[jmgao]

lib/builtins/arm/aeabi_cdcmpeq_helper.c

19 ↗

(On Diff #32342)

It was a response to the "calling it directly from the asm function" post from @rengolin in case that there actually is a way to call __builtin_isnan directly from asm, so I could do that instead.

[compnerd]

lib/builtins/arm/aeabi_cdcmp.S

30

Yeah, after a second (or third) reading, I agree. This function is exempt from that restriction. Im not sure what the benefit of saving lr here is, as you can just as well as bx lr in one case, and just tail call as you do in the other case.

34

I think that this plus the highlighting in my copy of the RTABI document caused the confusion. Saving behaviour of cdcmple is irrelevant.

35

You hoisted it one instruction too early. You just clobbered the result (r0).

45

Wouldn't this be shorter as:

__aeabi_cdcmpeq:
    push {r0-r3}
    blx __aeabi_cdcmpeq_check_nan
    cmp r0, #1
    pop {r0-r3}
    beq __aeabi_cdcmple
    msr CPSR_f, #APSR_C
    bx lr

75

It seems you can factor out the setting of the CPSR, and do a single return. Something along the lines of:

__aeabi_cdcmple:
  push {r0-r3}
  blx __aeabi_dcmplt
  cmp r0, #1
  moveq ip, #0
  beq 1f
  ldm sp, {r0-r3}
  blx __aeabi_dcmpeq
  cmp r0, #1
  moveq ip, #(APSR_Z | APSR_C)
  beq 1f
  mov ip, #APSR_C
1:msr CPSR_f, ip
  pop {r0-r3}
  bx lr

[jmgao]

lib/builtins/arm/aeabi_cdcmp.S

30

The call to the check_nan helper trashes lr

35

Whoops. I'm not sure how I missed that. I guess the tests passed because it's not changing the behavior if the implementation doesn't trap on NaN and you don't pass in a float with a value of 1 in the first word.

45

Yes it would, except {r0-r3, lr} for the push/pop since the call to __aeabi_cdcmpeq_check_nan will trash lr.

76

How about this?

__aeabi_cdcmple:
    push {r0-r4, lr}

    bl __aeabi_dcmplt
    cmp r0, #1
    moveq r4, #0
    beq 1f

    ldm sp, {r0-r3}
    bl __aeabi_dcmpeq
    cmp r0, #1
    moveq r4, #(APSR_C | APSR_Z)
    movne r4, #(APSR_C)
1:
    msr CPSR_f, r4
    pop {r0-r4, pc}

[compnerd]

lib/builtins/arm/aeabi_cdcmp.S

45

Ah, right.

76

I like the idea of the moveq/movne ... though, Im not sure I understand the purpose of using r4 rather than ip which is already a scratch register. The pop {pc} has the issue that Renato pointed out wrt older chips, (the stack savings are probably not important).

[jmgao]

lib/builtins/arm/aeabi_cdcmp.S

76

Oh yeah, using ip is fine here. I originally had orr r4, r4, #APSR_C; orreq r4, r4, #APSR_Z instead of the direct mov.

I added a macro for doing either pop {pc} or pop {ip}; bx ip

[compnerd]

Missing file headers on call_apsr.S and call_apr.h. Please use the DEFINE_COMPILERRT_PRIVATE_FUNCTION macros for call_apr_{d,f}. LGTM otherwise.

[jmgao]

In D12089#228583, @compnerd wrote:

Please use the DEFINE_COMPILERRT_PRIVATE_FUNCTION macros for call_apr_{d,f}.

Is #include "../../../../lib/builtins/assembly.h okay?

[jmgao]

Use DEFINE_COMPILERRT_PRIVATE_FUNCTION in call_apsr.S, file headers.

lib/builtins/CMakeLists.txt

 set(arm_SOURCES
   arm/adddf3vfp.S
   arm/addsf3vfp.S
+  arm/aeabi_cdcmp.S
+  arm/aeabi_cdcmpeq_check_nan.c
+  arm/aeabi_cfcmp.S
+  arm/aeabi_cfcmpeq_check_nan.c
   arm/aeabi_dcmp.S
   arm/aeabi_div0.c
   arm/aeabi_drsub.c

lib/builtins/arm/aeabi_cdcmp.S

+//===-- aeabi_cdcmp.S - EABI cdcmp* implementation ------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is dual licensed under the MIT and the University of Illinois Open
+// Source Licenses. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
+#error big endian support not implemented
+#endif
+
+#define APSR_Z (1 << 30)
+#define APSR_C (1 << 29)
+
+// void __aeabi_cdcmpeq(double a, double b) {
+//   if (isnan(a) || isnan(b)) {
+//     Z = 0; C = 1;
+//   } else {
+//     __aeabi_cdcmple(a, b);
+//   }
+// }
+
+        .syntax unified
+        .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmpeq)
+        push {r0-r3, lr}
+        bl __aeabi_cdcmpeq_check_nan
+        cmp r0, #1
+        pop {r0-r3, lr}
+
+        // NaN has been ruled out, so __aeabi_cdcmple can't trap
+        bne __aeabi_cdcmple
+
+        msr CPSR_f, #APSR_C
+        JMP(lr)
+END_COMPILERRT_FUNCTION(__aeabi_cdcmpeq)
+
+
+// void __aeabi_cdcmple(double a, double b) {
+//   if (__aeabi_dcmplt(a, b)) {
+//     Z = 0; C = 0;
+//   } else if (__aeabi_dcmpeq(a, b)) {
+//     Z = 1; C = 1;
+//   } else {
+//     Z = 0; C = 1;
+//   }
+// }
+
+        .syntax unified
+        .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmple)
+        // Per the RTABI, this function must preserve r0-r11.
+        // Save lr in the same instruction for compactness
+        push {r0-r3, lr}
+
+        bl __aeabi_dcmplt
+        cmp r0, #1
+        moveq ip, #0
+        beq 1f
+
+        ldm sp, {r0-r3}
+        bl __aeabi_dcmpeq
+        cmp r0, #1
+        moveq ip, #(APSR_C | APSR_Z)
+        movne ip, #(APSR_C)
+
+1:
+        msr CPSR_f, ip
+        pop {r0-r3}
+        POP_PC()
+END_COMPILERRT_FUNCTION(__aeabi_cdcmple)
+
+// int __aeabi_cdrcmple(double a, double b) {
+//   return __aeabi_cdcmple(b, a);
+// }
+
+        .syntax unified
+        .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__aeabi_cdrcmple)
+        // Swap r0 and r2
+        mov ip, r0
+        mov r0, r2
+        mov r2, ip
+
+        // Swap r1 and r3
+        mov ip, r1
+        mov r1, r3
+        mov r3, ip
+
+        b __aeabi_cdcmple
+END_COMPILERRT_FUNCTION(__aeabi_cdrcmple)
+

lib/builtins/arm/aeabi_cdcmpeq_check_nan.c

+//===-- lib/arm/aeabi_cdcmpeq_helper.c - Helper for cdcmpeq ---------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is dual licensed under the MIT and the University of Illinois Open
+// Source Licenses. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdint.h>
+
+__attribute__((pcs("aapcs")))
+__attribute__((visibility("hidden")))
+int __aeabi_cdcmpeq_check_nan(double a, double b) {
+    return __builtin_isnan(a) || __builtin_isnan(b);
+}

lib/builtins/arm/aeabi_cfcmp.S

+//===-- aeabi_cfcmp.S - EABI cfcmp* implementation ------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is dual licensed under the MIT and the University of Illinois Open
+// Source Licenses. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+
+#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
+#error big endian support not implemented
+#endif
+
+#define APSR_Z (1 << 30)
+#define APSR_C (1 << 29)
+
+// void __aeabi_cfcmpeq(float a, float b) {
+//   if (isnan(a) || isnan(b)) {
+//     Z = 0; C = 1;
+//   } else {
+//     __aeabi_cfcmple(a, b);
+//   }
+// }
+
+        .syntax unified
+        .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
+        push {r0-r3, lr}
+        bl __aeabi_cfcmpeq_check_nan
+        cmp r0, #1
+        pop {r0-r3, lr}
+
+        // NaN has been ruled out, so __aeabi_cfcmple can't trap
+        bne __aeabi_cfcmple
+
+        msr CPSR_f, #APSR_C
+        JMP(lr)
+END_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
+
+
+// void __aeabi_cfcmple(float a, float b) {
+//   if (__aeabi_fcmplt(a, b)) {
+//     Z = 0; C = 0;
+//   } else if (__aeabi_fcmpeq(a, b)) {
+//     Z = 1; C = 1;
+//   } else {
+//     Z = 0; C = 1;
+//   }
+// }
+
+        .syntax unified
+        .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmple)
+        // Per the RTABI, this function must preserve r0-r11.
+        // Save lr in the same instruction for compactness
+        push {r0-r3, lr}
+
+        bl __aeabi_fcmplt
+        cmp r0, #1
+        moveq ip, #0
+        beq 1f
+
+        ldm sp, {r0-r3}
+        bl __aeabi_fcmpeq
+        cmp r0, #1
+        moveq ip, #(APSR_C | APSR_Z)
+        movne ip, #(APSR_C)
+
+1:
+        msr CPSR_f, ip
+        pop {r0-r3}
+        POP_PC()
+END_COMPILERRT_FUNCTION(__aeabi_cfcmple)
+
+// int __aeabi_cfrcmple(float a, float b) {
+//   return __aeabi_cfcmple(b, a);
+// }
+
+        .syntax unified
+        .p2align 2
+DEFINE_COMPILERRT_FUNCTION(__aeabi_cfrcmple)
+        // Swap r0 and r1
+        mov ip, r0
+        mov r0, r1
+        mov r1, ip
+
+        b __aeabi_cfcmple
+END_COMPILERRT_FUNCTION(__aeabi_cfrcmple)
+

lib/builtins/arm/aeabi_cfcmpeq_check_nan.c

+//===-- lib/arm/aeabi_cfcmpeq_helper.c - Helper for cdcmpeq ---------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is dual licensed under the MIT and the University of Illinois Open
+// Source Licenses. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdint.h>
+
+__attribute__((pcs("aapcs")))
+__attribute__((visibility("hidden")))
+int __aeabi_cfcmpeq_check_nan(float a, float b) {
+    return __builtin_isnan(a) || __builtin_isnan(b);
+}

lib/builtins/assembly.h

 #define JMPc(r, c) mov##c pc, r
 #endif
 
+// pop {pc} can't switch Thumb mode on ARMv4T
+#if __ARM_ARCH >= 5
+#define POP_PC() pop {pc}
+#else
+#define POP_PC()                                                               \
+  pop {ip};                                                                    \
+  JMP(ip)
+#endif
+
 #if __ARM_ARCH_ISA_THUMB == 2
 #define IT(cond)  it cond
 #define ITT(cond) itt cond

test/builtins/Unit/arm/aeabi_cdcmpeq_test.c

+//===-- aeabi_cdcmpeq.c - Test __aeabi_cdcmpeq ----------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is dual licensed under the MIT and the University of Illinois Open
+// Source Licenses. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file tests __aeabi_cdcmpeq for the compiler_rt library.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+
+#if __arm__
+#include "call_apsr.h"
+
+extern __attribute__((pcs("aapcs"))) void __aeabi_cdcmpeq(double a, double b);
+
+int test__aeabi_cdcmpeq(double a, double b, int expected)
+{
+    uint32_t cpsr_value = call_apsr_d(a, b, __aeabi_cdcmpeq);
+    union cpsr cpsr = { .value = cpsr_value };
+    if (expected != cpsr.flags.z) {
+        printf("error in __aeabi_cdcmpeq(%f, %f) => Z = %d, expected %d\n",
+               a, b, cpsr.flags.z, expected);
+        return 1;
+    }
+    return 0;
+}
+#endif
+
+int main()
+{
+#if __arm__
+    if (test__aeabi_cdcmpeq(1.0, 1.0, 1))
+        return 1;
+    if (test__aeabi_cdcmpeq(1234.567, 765.4321, 0))
+        return 1;
+    if (test__aeabi_cdcmpeq(-123.0, -678.0, 0))
+        return 1;
+    if (test__aeabi_cdcmpeq(0.0, -0.0, 1))
+        return 1;
+    if (test__aeabi_cdcmpeq(1.0, NAN, 0))
+        return 1;
+    if (test__aeabi_cdcmpeq(NAN, 1.0, 0))
+        return 1;
+    if (test__aeabi_cdcmpeq(NAN, NAN, 0))
+        return 1;
+    if (test__aeabi_cdcmpeq(INFINITY, 1.0, 0))
+        return 1;
+    if (test__aeabi_cdcmpeq(0.0, INFINITY, 0))
+        return 1;
+    if (test__aeabi_cdcmpeq(-INFINITY, 0.0, 0))
+        return 1;
+    if (test__aeabi_cdcmpeq(0.0, -INFINITY, 0))
+        return 1;
+    if (test__aeabi_cdcmpeq(INFINITY, INFINITY, 1))
+        return 1;
+    if (test__aeabi_cdcmpeq(-INFINITY, -INFINITY, 1))
+        return 1;
+#else
+    printf("skipped\n");
+#endif
+    return 0;
+}

test/builtins/Unit/arm/aeabi_cdcmple_test.c

+//===-- aeabi_cdcmple.c - Test __aeabi_cdcmple and __aeabi_cdrcmple -------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is dual licensed under the MIT and the University of Illinois Open
+// Source Licenses. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file tests __aeabi_cdcmple and __aeabi_cdrcmple for the compiler_rt
+// library.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+
+#include "call_apsr.h"
+
+#if __arm__
+
+extern __attribute__((pcs("aapcs"))) void __aeabi_cdcmple(double a, double b);
+extern __attribute__((pcs("aapcs"))) void __aeabi_cdrcmple(double a, double b);
+
+int test__aeabi_cdcmple(double a, double b, int expected)
+{
+    int32_t cpsr_value = call_apsr_d(a, b, __aeabi_cdcmple);
+    int32_t r_cpsr_value = call_apsr_d(b, a, __aeabi_cdrcmple);
+
+    if (cpsr_value != r_cpsr_value) {
+        printf("error: __aeabi_cdcmple(%f, %f) != __aeabi_cdrcmple(%f, %f)\n", a, b, b, a);
+        return 1;
+    }
+
+    int expected_z, expected_c;
+    if (expected == -1) {
+        expected_z = 0;
+        expected_c = 0;
+    } else if (expected == 0) {
+        expected_z = 1;
+        expected_c = 1;
+    } else {
+        // a or b is NaN, or a > b
+        expected_z = 0;
+        expected_c = 1;
+    }
+
+    union cpsr cpsr = { .value = cpsr_value };
+    if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
+        printf("error in __aeabi_cdcmple(%f, %f) => (Z = %d, C = %d), expected (Z = %d, C = %d)\n",
+               a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c);
+        return 1;
+    }
+
+    cpsr.value = r_cpsr_value;
+    if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
+        printf("error in __aeabi_cdrcmple(%f, %f) => (Z = %d, C = %d), expected (Z = %d, C = %d)\n",
+               a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c);
+        return 1;
+    }
+    return 0;
+}
+#endif
+
+int main()
+{
+#if __arm__
+    if (test__aeabi_cdcmple(1.0, 1.0, 0))
+        return 1;
+    if (test__aeabi_cdcmple(1234.567, 765.4321, 1))
+        return 1;
+    if (test__aeabi_cdcmple(765.4321, 1234.567, -1))
+        return 1;
+    if (test__aeabi_cdcmple(-123.0, -678.0, 1))
+        return 1;
+    if (test__aeabi_cdcmple(-678.0, -123.0, -1))
+        return 1;
+    if (test__aeabi_cdcmple(0.0, -0.0, 0))
+        return 1;
+    if (test__aeabi_cdcmple(1.0, NAN, 1))
+        return 1;
+    if (test__aeabi_cdcmple(NAN, 1.0, 1))
+        return 1;
+    if (test__aeabi_cdcmple(NAN, NAN, 1))
+        return 1;
+#else
+    printf("skipped\n");
+#endif
+    return 0;
+}

test/builtins/Unit/arm/aeabi_cfcmpeq_test.c

+//===-- aeabi_cfcmpeq.c - Test __aeabi_cfcmpeq ----------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is dual licensed under the MIT and the University of Illinois Open
+// Source Licenses. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file tests __aeabi_cfcmpeq for the compiler_rt library.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+
+#if __arm__
+#include "call_apsr.h"
+
+extern __attribute__((pcs("aapcs"))) void __aeabi_cfcmpeq(float a, float b);
+
+int test__aeabi_cfcmpeq(float a, float b, int expected)
+{
+    uint32_t cpsr_value = call_apsr_f(a, b, __aeabi_cfcmpeq);
+    union cpsr cpsr = { .value = cpsr_value };
+    if (expected != cpsr.flags.z) {
+        printf("error in __aeabi_cfcmpeq(%f, %f) => Z = %d, expected %d\n",
+               a, b, cpsr.flags.z, expected);
+        return 1;
+    }
+    return 0;
+}
+#endif
+
+int main()
+{
+#if __arm__
+    if (test__aeabi_cfcmpeq(1.0, 1.0, 1))
+        return 1;
+    if (test__aeabi_cfcmpeq(1234.567, 765.4321, 0))
+        return 1;
+    if (test__aeabi_cfcmpeq(-123.0, -678.0, 0))
+        return 1;
+    if (test__aeabi_cfcmpeq(0.0, -0.0, 1))
+        return 1;
+    if (test__aeabi_cfcmpeq(1.0, NAN, 0))
+        return 1;
+    if (test__aeabi_cfcmpeq(NAN, 1.0, 0))
+        return 1;
+    if (test__aeabi_cfcmpeq(NAN, NAN, 0))
+        return 1;
+    if (test__aeabi_cfcmpeq(INFINITY, 1.0, 0))
+        return 1;
+    if (test__aeabi_cfcmpeq(0.0, INFINITY, 0))
+        return 1;
+    if (test__aeabi_cfcmpeq(-INFINITY, 0.0, 0))
+        return 1;
+    if (test__aeabi_cfcmpeq(0.0, -INFINITY, 0))
+        return 1;
+    if (test__aeabi_cfcmpeq(INFINITY, INFINITY, 1))
+        return 1;
+    if (test__aeabi_cfcmpeq(-INFINITY, -INFINITY, 1))
+        return 1;
+#else
+    printf("skipped\n");
+#endif
+    return 0;
+}

test/builtins/Unit/arm/aeabi_cfcmple_test.c

+//===-- aeabi_cfcmple.c - Test __aeabi_cfcmple and __aeabi_cfrcmple -------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is dual licensed under the MIT and the University of Illinois Open
+// Source Licenses. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file tests __aeabi_cfcmple and __aeabi_cfrcmple for the compiler_rt
+// library.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+
+#include "call_apsr.h"
+
+#if __arm__
+
+extern __attribute__((pcs("aapcs"))) void __aeabi_cfcmple(float a, float b);
+extern __attribute__((pcs("aapcs"))) void __aeabi_cfrcmple(float a, float b);
+
+int test__aeabi_cfcmple(float a, float b, int expected)
+{
+    int32_t cpsr_value = call_apsr_f(a, b, __aeabi_cfcmple);
+    int32_t r_cpsr_value = call_apsr_f(b, a, __aeabi_cfrcmple);
+
+    if (cpsr_value != r_cpsr_value) {
+        printf("error: __aeabi_cfcmple(%f, %f) != __aeabi_cfrcmple(%f, %f)\n", a, b, b, a);
+        return 1;
+    }
+
+    int expected_z, expected_c;
+    if (expected == -1) {
+        expected_z = 0;
+        expected_c = 0;
+    } else if (expected == 0) {
+        expected_z = 1;
+        expected_c = 1;
+    } else {
+        // a or b is NaN, or a > b
+        expected_z = 0;
+        expected_c = 1;
+    }
+
+    union cpsr cpsr = { .value = cpsr_value };
+    if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
+        printf("error in __aeabi_cfcmple(%f, %f) => (Z = %d, C = %d), expected (Z = %d, C = %d)\n",
+               a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c);
+        return 1;
+    }
+
+    cpsr.value = r_cpsr_value;
+    if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
+        printf("error in __aeabi_cfrcmple(%f, %f) => (Z = %d, C = %d), expected (Z = %d, C = %d)\n",
+               a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c);
+        return 1;
+    }
+    return 0;
+}
+#endif
+
+int main()
+{
+#if __arm__
+    if (test__aeabi_cfcmple(1.0, 1.0, 0))
+        return 1;
+    if (test__aeabi_cfcmple(1234.567, 765.4321, 1))
+        return 1;
+    if (test__aeabi_cfcmple(765.4321, 1234.567, -1))
+        return 1;
+    if (test__aeabi_cfcmple(-123.0, -678.0, 1))
+        return 1;
+    if (test__aeabi_cfcmple(-678.0, -123.0, -1))
+        return 1;
+    if (test__aeabi_cfcmple(0.0, -0.0, 0))
+        return 1;
+    if (test__aeabi_cfcmple(1.0, NAN, 1))
+        return 1;
+    if (test__aeabi_cfcmple(NAN, 1.0, 1))
+        return 1;
+    if (test__aeabi_cfcmple(NAN, NAN, 1))
+        return 1;
+#else
+    printf("skipped\n");
+#endif
+    return 0;
+}

test/builtins/Unit/arm/call_apsr.h

+#ifndef CALL_APSR_H
+#define CALL_APSR_H
+
+#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
+#error big endian support not implemented
+#endif
+
+union cpsr {
+    struct {
+        uint32_t filler: 28;
+        uint32_t v: 1;
+        uint32_t c: 1;
+        uint32_t z: 1;
+        uint32_t n: 1;
+    } flags;
+    uint32_t value;
+};
+
+extern __attribute__((pcs("aapcs")))
+uint32_t call_apsr_f(float a, float b, __attribute__((pcs("aapcs"))) void (*fn)(float, float));
+
+extern __attribute__((pcs("aapcs")))
+uint32_t call_apsr_d(double a, double b, __attribute__((pcs("aapcs"))) void (*fn)(double, double));
+
+#endif // CALL_APSR_H

test/builtins/Unit/arm/call_apsr.S

+.syntax unified
+// __attribute__((pcs("aapcs"))) int32_t call_apsr_d(double a, double b, void(*fn)(double, double)) {
+//   fn(a, b);
+//   return apsr;
+// }
+
+.globl call_apsr_d
+.type call_apsr_d,%function
+call_apsr_d:
+    push {lr}
+    ldr ip, [sp, #4]
+    blx ip
+    mrs r0, apsr
+    pop {pc}
+
+// __attribute__((pcs("aapcs"))) int32_t call_apsr_f(float a, float b, void(*fn)(float, float)) {
+//   fn(a, b);
+//   return apsr;
+// }
+
+.globl call_apsr_f
+.type call_apsr_f,%function
+call_apsr_f:
+    push {lr}
+    blx r2
+    mrs r0, apsr
+    pop {pc}