[RISCV] Add FMV_W_X and FMV_H_X instrutions to hasAllNBitUsers

[Jimerlife]

Summary

I think fmv.w.x and fmv.h.x also applied to hasAllNBitUsers.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

for (auto UI = Node->use_begin(), UE = Node->use_end(); UI != UE; ++UI) {
     case RISCV::REMUW:
     case RISCV::ROLW:
     case RISCV::RORW:
     case RISCV::RORIW:
     case RISCV::CLZW:
     case RISCV::CTZW:
     case RISCV::CPOPW:
     case RISCV::SLLI_UW:
+    case RISCV::FMV_W_X:
     case RISCV::FCVT_H_W:
     case RISCV::FCVT_H_WU:
     case RISCV::FCVT_S_W:
     case RISCV::FCVT_S_WU:
     case RISCV::FCVT_D_W:
     case RISCV::FCVT_D_WU:
       if (Bits < 32)
         return false;
       break;
     case RISCV::SLLI:
       // SLLI only uses the lower (XLen - ShAmt) bits.
       if (Bits < Subtarget->getXLen() - User->getConstantOperandVal(1))
         return false;
       break;
     case RISCV::ANDI:
       if (Bits < (64 - countLeadingZeros(User->getConstantOperandVal(1))))
         return false;
       break;
     case RISCV::SEXT_B:
       if (Bits < 8)
         return false;
       break;
     case RISCV::SEXT_H:
+    case RISCV::FMV_H_X:
     case RISCV::ZEXT_H_RV32:
     case RISCV::ZEXT_H_RV64:
       if (Bits < 16)
         return false;
       break;
     case RISCV::ADD_UW:
     case RISCV::SH1ADD_UW:
     case RISCV::SH2ADD_UW: