[VP] IR expansion pass for VP gather and scatter

[loralb]

Summary

Add vp_gather and vp_scatter expansion to unpredicated intrinsics.

[simoll]

llvm/lib/CodeGen/ExpandVectorPredication.cpp

432

Not sure about valueOrOne() here... can we assume alignment to element size? Does the data layout tell us something here?

[loralb]

Changelog:

• Use DataLayout to determine the alignment (if there is not one already)
• Add fixed vectors tests

[simoll]

LGTM

[loralb]

Changelog

• Rebase

llvm/lib/CodeGen/ExpandVectorPredication.cpp

if (IsUnmasked) {
         NewLoad->setAlignment(AlignOpt.getValue());
       NewMemoryInst = NewLoad;
     } else
       NewMemoryInst = Builder.CreateMaskedLoad(
           VPI.getType(), PtrParam, AlignOpt.valueOrOne(), MaskParam);
 
     break;
   }
+  case Intrinsic::vp_scatter:
+    NewMemoryInst = Builder.CreateMaskedScatter(
+        DataParam, PtrParam, AlignOpt.valueOrOne(), MaskParam);
+    break;
+  case Intrinsic::vp_gather:
+    NewMemoryInst = Builder.CreateMaskedGather(VPI.getType(), PtrParam,
+                                               AlignOpt.valueOrOne(), MaskParam,
+                                               nullptr, VPI.getName());
+    break;
   }
 
   assert(NewMemoryInst);
   replaceOperation(*NewMemoryInst, VPI);
   return NewMemoryInst;
 }
 
 void CachingVPExpander::discardEVLParameter(VPIntrinsic &VPI) {
Value *CachingVPExpander::expandPredication(VPIntrinsic &VPI) {
   if (auto *VPRI = dyn_cast<VPReductionIntrinsic>(&VPI))
     return expandPredicationInReduction(Builder, *VPRI);
 
   switch (VPI.getIntrinsicID()) {
   default:
     break;
   case Intrinsic::vp_load:
   case Intrinsic::vp_store:
+  case Intrinsic::vp_gather:
+  case Intrinsic::vp_scatter:
     return expandPredicationInMemoryIntrinsic(Builder, VPI);
   }
 
   return &VPI;
 }
 
 //// } CachingVPExpander
 

llvm/test/CodeGen/Generic/expand-vp-gather-scatter.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt --expandvp -S < %s | FileCheck %s
+
+declare <vscale x 1 x i64> @llvm.vp.gather.nxv1i64.nxv1p0i64(<vscale x 1 x i64*>, <vscale x 1 x i1>, i32)
+
+define <vscale x 1 x i64> @vpgather_nxv1i64(<vscale x 1 x i64*> %ptrs, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: @vpgather_nxv1i64(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i32(i32 0, i32 [[EVL:%.*]])
+; CHECK-NEXT:    [[TMP2:%.*]] = and <vscale x 1 x i1> [[TMP1]], [[M:%.*]]
+; CHECK-NEXT:    [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
+; CHECK-NEXT:    [[SCALABLE_SIZE:%.*]] = mul nuw i32 [[VSCALE]], 1
+; CHECK-NEXT:    [[V1:%.*]] = call <vscale x 1 x i64> @llvm.masked.gather.nxv1i64.nxv1p0i64(<vscale x 1 x i64*> [[PTRS:%.*]], i32 1, <vscale x 1 x i1> [[TMP2]], <vscale x 1 x i64> undef)
+; CHECK-NEXT:    ret <vscale x 1 x i64> [[V1]]
+;
+  %v = call <vscale x 1 x i64> @llvm.vp.gather.nxv1i64.nxv1p0i64(<vscale x 1 x i64*> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
+  ret <vscale x 1 x i64> %v
+}
+
+declare void @llvm.vp.scatter.nxv1i64.nxv1p0i64(<vscale x 1 x i64>, <vscale x 1 x i64*>, <vscale x 1 x i1>, i32)
+
+define void @vpscatter_nxv1i64(<vscale x 1 x i64> %val, <vscale x 1 x i64*> %ptrs, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: @vpscatter_nxv1i64(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i32(i32 0, i32 [[EVL:%.*]])
+; CHECK-NEXT:    [[TMP2:%.*]] = and <vscale x 1 x i1> [[TMP1]], [[M:%.*]]
+; CHECK-NEXT:    [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
+; CHECK-NEXT:    [[SCALABLE_SIZE:%.*]] = mul nuw i32 [[VSCALE]], 1
+; CHECK-NEXT:    call void @llvm.masked.scatter.nxv1i64.nxv1p0i64(<vscale x 1 x i64> [[VAL:%.*]], <vscale x 1 x i64*> [[PTRS:%.*]], i32 1, <vscale x 1 x i1> [[TMP2]])
+; CHECK-NEXT:    ret void
+;
+  call void @llvm.vp.scatter.nxv1i64.nxv1p0i64(<vscale x 1 x i64> %val, <vscale x 1 x i64*> %ptrs, <vscale x 1 x i1> %m, i32 %evl)
+  ret void
+}