[RISCV] Optimize (sext.w, srli) to sraiw with Zba.

[Chenbing.Zheng]

Summary

In this patch, we add a more narrower exclusion for
zeroext (srl x) -> srli (slli x), so that it provides an opportunity for the selection of sraiw.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

776

Don't you also need to check that C3 is 32?

[Chenbing.Zheng]

Address comments

[Chenbing.Zheng]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

776

Thanks, I think so.

[Chenbing.Zheng]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

776

Thanks, I think so.

I mean I agree with you

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

if (!LeftShift && isMask_64(C1)) {
           SDNode *SRLIW = CurDAG->getMachineNode(
               RISCV::SRLIW, DL, XLenVT, SDValue(SRAIW, 0),
               CurDAG->getTargetConstant(C3 - 32, DL, XLenVT));
           ReplaceNode(Node, SRLIW);
           return;
         }
 
         // (srli (slli x, c3-c2), c3).
-        if (OneUseOrZExtW && !IsANDI) {
+        // Skip it in order to select sraiw.
+        bool Skip = Subtarget->hasStdExtZba() && C3 == 32 &&
+                    X.getOpcode() == ISD::SIGN_EXTEND_INREG;
+        if (OneUseOrZExtW && !IsANDI && !Skip) {
           SDNode *SLLI = CurDAG->getMachineNode(
               RISCV::SLLI, DL, XLenVT, X,
               CurDAG->getTargetConstant(C3 - C2, DL, XLenVT));
           SDNode *SRLI =
               CurDAG->getMachineNode(RISCV::SRLI, DL, XLenVT, SDValue(SLLI, 0),
                                      CurDAG->getTargetConstant(C3, DL, XLenVT));
           ReplaceNode(Node, SRLI);
           return;

llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll

 ; RV64-LABEL: sext_sraiw_zext:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    sraiw a0, a0, 6
 ; RV64-NEXT:    ret
   %1 = ashr i32 %a, 6
   ret i32 %1
 }
 
-; TODO: The sext.w+srli can be replaced with sraiw with Zba.
 define zeroext i32 @zext_sraiw_aext(i32 %a) nounwind {
-; RV64-LABEL: zext_sraiw_aext:
-; RV64:       # %bb.0:
-; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    slli a0, a0, 25
-; RV64-NEXT:    srli a0, a0, 32
-; RV64-NEXT:    ret
+; RV64I-LABEL: zext_sraiw_aext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    slli a0, a0, 25
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: zext_sraiw_aext:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sraiw a0, a0, 7
+; RV64ZBA-NEXT:    zext.w a0, a0
+; RV64ZBA-NEXT:    ret
   %1 = ashr i32 %a, 7
   ret i32 %1
 }
 
 define zeroext i32 @zext_sraiw_sext(i32 signext %a) nounwind {
 ; RV64-LABEL: zext_sraiw_sext:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    slli a0, a0, 24
 ; RV64-NEXT:    srli a0, a0, 32
 ; RV64-NEXT:    ret
   %1 = ashr i32 %a, 8
   ret i32 %1
 }
 
-; TODO: The sext.w+srli can be replaced with sraiw with Zba.
 define zeroext i32 @zext_sraiw_zext(i32 zeroext %a) nounwind {
-; RV64-LABEL: zext_sraiw_zext:
-; RV64:       # %bb.0:
-; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    slli a0, a0, 23
-; RV64-NEXT:    srli a0, a0, 32
-; RV64-NEXT:    ret
+; RV64I-LABEL: zext_sraiw_zext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    slli a0, a0, 23
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: zext_sraiw_zext:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sraiw a0, a0, 9
+; RV64ZBA-NEXT:    zext.w a0, a0
+; RV64ZBA-NEXT:    ret
   %1 = ashr i32 %a, 9
   ret i32 %1
 }