[Triple] Add llvm::Triple::isSPARC{,32,64}

[MaskRay]

Please sync past 3a1cb362370d223e09899d234726e15b52327b0e: the patch accidentally removes isDriverKit.

[XiaodongLoong]

rebase code

[XiaodongLoong]

In D120381#3339390, @MaskRay wrote:

Please sync past 3a1cb362370d223e09899d234726e15b52327b0e: the patch accidentally removes isDriverKit.

@MaskRay Sorry, it is OK now. Thanks!

[ro]

Looking at existing cases of comparisons with Triple::sparc and Triple::sparcv9, I guess we should have isSPARC32 and isSPARC64, too, like isMIPS32/isMIPS64 and isPPC32/isPPC64. When switching to isSPARC* from existing Triple::sparc* comparisons, one will have to be extra careful if they are meant to mean SPARC in general or 32-bit SPARC in particular. little-endian SPARC is another beast altogether: I didn't even know it existed beyond the ability of SPARCV9 CPUs to partially run in LE mode, so it will be hard to tell if LE SPARC is to be included. I guess only code review and testing by interested parties can tell.

llvm/include/llvm/ADT/Triple.h

829

I'd go for isSPARC instead: SPARC is an acronym, like MIPS, although LLVM is anything but consistent about the correct capitalization.

[XiaodongLoong]

update code for review comments.
rebase code.

[XiaodongLoong]

llvm/include/llvm/ADT/Triple.h

829

Thanks for the comment, I fixed it.

[XiaodongLoong]

@ro
Since sparcv9 is Bi-endianness (https://en.wikipedia.org/wiki/Endianness#Bi-endianness), I add "sparcv9el" like on MIPS. If it is not OK, I can delete it.
Could I do the switching to isSPARC* from existing Triple::sparc* in another patch?

[brad]

In D120381#3342008, @XiaodongLoong wrote:

Since sparcv9 is Bi-endianness (https://en.wikipedia.org/wiki/Endianness#Bi-endianness), I add "sparcv9el" like on MIPS. If it is not OK, I can delete it.

I don't think this makes sense. No one runs SPARCv9 with little endian.

[XiaodongLoong]

@brad delete little endian SPARC V9

[ro]

In D120381#3342217, @brad wrote:

I don't think this makes sense. No one runs SPARCv9 with little endian.

Not only that: this isn't a full fledged little-endian mode like mipsel. See "Oracle SPARC Architecture 2015", p.20:

3.3.1.2 Addressing Conventions
[...]
The Oracle SPARC Architecture also supports little-endian byte order for data accesses only: the
address of a quadword, doubleword, word, or halfword is the address of its least significant byte.
Increasing the address means increasing the significance of the data unit being accessed.

[ro]

In D120381#3342008, @XiaodongLoong wrote:

Could I do the switching to isSPARC* from existing Triple::sparc* in another patch?

Given the evaluation and testing requirements I'd mentioned, I guess it's better to start using isSPARC* for new or modified code right now, but handle existing comparisons to Triple::sparc* separately. I don't think that's your duty, though. You've done way enough already. Thanks.

[ro]

llvm/include/llvm/ADT/Triple.h

829

I think all those clang-format reformatting suggestions should be ignored: while they might be appropriate for new code, the new methods would be formatted differently from every other one in this file.

[XiaodongLoong]

format new code

[ro]

llvm/include/llvm/ADT/Triple.h

834

That's the opposite of what I suggested: please follow existing formatting.

837

Same here.

[XiaodongLoong]

format code

[XiaodongLoong]

llvm/include/llvm/ADT/Triple.h

834

I am so sorry. I misunderstood your words. I format back.

837

Done.

[ro]

LGTM

[MaskRay]

clang-format

update subject

llvm/include/llvm/ADT/Triple.h

 ///
 /// See autoconf/config.guess for a glimpse into what configuration names
 /// look like in practice.
 class Triple {
 public:
   enum ArchType {
     UnknownArch,
 
     arm,            // ARM (little endian): arm, armv.*, xscale
     armeb,          // ARM (big endian): armeb
     aarch64,        // AArch64 (little endian): aarch64
     aarch64_be,     // AArch64 (big endian): aarch64_be
     aarch64_32,     // AArch64 (little endian) ILP32: aarch64_32
     arc,            // ARC: Synopsys ARC
     avr,            // AVR: Atmel AVR microcontroller
     bpfel,          // eBPF or extended BPF or 64-bit BPF (little endian)
     bpfeb,          // eBPF or extended BPF or 64-bit BPF (big endian)
enum ArchType {
     ppc64le,        // PPC64LE: powerpc64le
     r600,           // R600: AMD GPUs HD2XXX - HD6XXX
     amdgcn,         // AMDGCN: AMD GCN GPUs
     riscv32,        // RISC-V (32-bit): riscv32
     riscv64,        // RISC-V (64-bit): riscv64
     sparc,          // Sparc: sparc
     sparcv9,        // Sparcv9: Sparcv9
     sparcel,        // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
+    sparcv9el,      // Sparcv9: (endianness = little)
     systemz,        // SystemZ: s390x
     tce,            // TCE (http://tce.cs.tut.fi/): tce
     tcele,          // TCE little endian (http://tce.cs.tut.fi/): tcele
     thumb,          // Thumb (little endian): thumb, thumbv.*
     thumbeb,        // Thumb (big endian): thumbeb
     x86,            // X86: i[3-9]86
     x86_64,         // X86-64: amd64, x86_64
     xcore,          // XCore: xcore
bool isPPC64() const {
     return getArch() == Triple::ppc64 || getArch() == Triple::ppc64le;
   }
 
   /// Tests whether the target is RISC-V (32- and 64-bit).
   bool isRISCV() const {
     return getArch() == Triple::riscv32 || getArch() == Triple::riscv64;
   }
 
+  /// Tests whether the target is 32-bit SPARC (little and big endian).
+  bool isSPARC32() const {
+    return getArch() == Triple::sparc || getArch() == Triple::sparcel;
+  }
+
+  /// Tests whether the target is 64-bit SPARC (little and big endian).
+  bool isSPARC64() const {
+    return getArch() == Triple::sparcv9 || getArch() == Triple::sparcv9el;
+  }
+
+  /// Tests whether the target is SPARC.
+  bool isSPARC() const {
+    return isSPARC32() || isSPARC64();
+  }
+
   /// Tests whether the target is SystemZ.
   bool isSystemZ() const {
     return getArch() == Triple::systemz;
   }
 
   /// Tests whether the target is x86 (32- or 64-bit).
   bool isX86() const {
     return getArch() == Triple::x86 || getArch() == Triple::x86_64;