[CUDA][SPIRV] Assign global address space to CUDA kernel arguments

[shangwuyao]

Summary

(resubmit https://reviews.llvm.org/D119207 after fixing the test for some build settings)
This patch converts CUDA pointer kernel arguments with default address space to
CrossWorkGroup address space (__global in OpenCL). This is because Generic or
Function (OpenCL's private) is not supported as storage class for kernel pointer types.

[shangwuyao]

Looking into the (new) test failure on Windows, since the change has already been reviewed, will try to commit after resolving the test failure.

[shangwuyao]

Disabled a hip test on Windows that's breaking on head.

[jlebar]

• What's different in this patch vs the previous one?
• *Disabled a hip test on Windows that's breaking on head.* Can you clarify: Is this test broken at HEAD, or does it break with your patch?
  
  If it's broken at HEAD, then it should be disabled in a separate patch.
  
  If it breaks with your patch, can you explain why it should be disabled rather than fixed?

[shangwuyao]

In D120366#3344221, @jlebar wrote:

• What's different in this patch vs the previous one?

Previous patch broke at two different post-commit build configurations. The generated SPIR-V are:

define hidden spir_kernel void @_Z6kernelPi(i32 addrspace(1)* noundef %output.coerce) #0 {

define spir_kernel void @_Z6kernelPi(i32 addrspace(1)* noundef %0) #0 {

And the original test:

// CHECK: define spir_kernel void @_Z6kernelPi(i32 addrspace(1)* noundef %output.coerce)

Changed that to below so that it could handle those two build configurations correctly.

// CHECK: define
// CHECK-SAME: spir_kernel void @_Z6kernelPi(i32 addrspace(1)* noundef

(The previous reverted patch could have been reopened so that the change is more clear, but didn't know such option exist until recently.)

• *Disabled a hip test on Windows that's breaking on head.* Can you clarify: Is this test broken at HEAD, or does it break with your patch?
  
  If it's broken at HEAD, then it should be disabled in a separate patch.
  
  If it breaks with your patch, can you explain why it should be disabled rather than fixed?

It is broken at HEAD, will add another patch.

[shangwuyao]

Disabling the test failing at HEAD with a separate patch.

[shangwuyao]

@yaxunl I saw that you added the test recently, could you provide some context? I think this test is broken at HEAD as I saw it is broken for other patches (see this build) as well.

[jlebar]

I'll land this for you.

[yaxunl]

In D120366#3344428, @shangwuyao wrote:

@yaxunl I saw that you added the test recently, could you provide some context? I think this test is broken at HEAD as I saw it is broken for other patches (see this build) as well.

which test?

[yaxunl]

In D120366#3345401, @yaxunl wrote:

In D120366#3344428, @shangwuyao wrote:

@yaxunl I saw that you added the test recently, could you provide some context? I think this test is broken at HEAD as I saw it is broken for other patches (see this build) as well.

which test?

OK. I saw it. Thanks for handling it. I will fix it.

clang/lib/Basic/Targets/SPIR.h

void setAddressSpaceMap(bool DefaultIsGeneric) {
     AddrSpaceMap = DefaultIsGeneric ? &SPIRDefIsGenMap : &SPIRDefIsPrivMap;
   }
 
   void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override {
     TargetInfo::adjust(Diags, Opts);
     // FIXME: SYCL specification considers unannotated pointers and references
     // to be pointing to the generic address space. See section 5.9.3 of
     // SYCL 2020 specification.
-    // Currently, there is no way of representing SYCL's and HIP's default
+    // Currently, there is no way of representing SYCL's and HIP/CUDA's default
     // address space language semantic along with the semantics of embedded C's
     // default address space in the same address space map. Hence the map needs
     // to be reset to allow mapping to the desired value of 'Default' entry for
-    // SYCL and HIP.
+    // SYCL and HIP/CUDA.
     setAddressSpaceMap(
         /*DefaultIsGeneric=*/Opts.SYCLIsDevice ||
-        // The address mapping from HIP language for device code is only defined
-        // for SPIR-V.
-        (getTriple().isSPIRV() && Opts.HIP && Opts.CUDAIsDevice));
+        // The address mapping from HIP/CUDA language for device code is only
+        // defined for SPIR-V.
+        (getTriple().isSPIRV() && Opts.CUDAIsDevice));
   }
 
   void setSupportedOpenCLOpts() override {
     // Assume all OpenCL extensions and optional core features are supported
     // for SPIR and SPIR-V since they are generic targets.
     supportAllOpenCLOpts();
   }
 

clang/lib/CodeGen/TargetInfo.cpp

 } // End anonymous namespace.
 
 void CommonSPIRABIInfo::setCCs() {
   assert(getRuntimeCC() == llvm::CallingConv::C);
   RuntimeCC = llvm::CallingConv::SPIR_FUNC;
 }
 
 ABIArgInfo SPIRVABIInfo::classifyKernelArgumentType(QualType Ty) const {
-  if (getContext().getLangOpts().HIP) {
+  if (getContext().getLangOpts().CUDAIsDevice) {
     // Coerce pointer arguments with default address space to CrossWorkGroup
-    // pointers for HIPSPV. When the language mode is HIP, the SPIRTargetInfo
-    // maps cuda_device to SPIR-V's CrossWorkGroup address space.
+    // pointers for HIPSPV/CUDASPV. When the language mode is HIP/CUDA, the
+    // SPIRTargetInfo maps cuda_device to SPIR-V's CrossWorkGroup address space.
     llvm::Type *LTy = CGT.ConvertType(Ty);
     auto DefaultAS = getContext().getTargetAddressSpace(LangAS::Default);
     auto GlobalAS = getContext().getTargetAddressSpace(LangAS::cuda_device);
     auto *PtrTy = llvm::dyn_cast<llvm::PointerType>(LTy);
     if (PtrTy && PtrTy->getAddressSpace() == DefaultAS) {
       LTy = llvm::PointerType::getWithSamePointeeType(PtrTy, GlobalAS);
       return ABIArgInfo::getDirect(LTy, 0, nullptr, false);
     }

clang/test/CodeGenCUDASPIRV/kernel-argument.cu

+// Tests CUDA kernel arguments get global address space when targetting SPIR-V.
+
+// REQUIRES: clang-driver
+
+// RUN: %clang -emit-llvm --cuda-device-only --offload=spirv32 \
+// RUN:   -nocudalib -nocudainc %s -o %t.bc -c 2>&1
+// RUN: llvm-dis %t.bc -o %t.ll
+// RUN: FileCheck %s --input-file=%t.ll
+
+// RUN: %clang -emit-llvm --cuda-device-only --offload=spirv64 \
+// RUN:   -nocudalib -nocudainc %s -o %t.bc -c 2>&1
+// RUN: llvm-dis %t.bc -o %t.ll
+// RUN: FileCheck %s --input-file=%t.ll
+
+// CHECK: define
+// CHECK-SAME: spir_kernel void @_Z6kernelPi(i32 addrspace(1)* noundef
+
+__attribute__((global)) void kernel(int* output) { *output = 1; }