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Differential D119912

Hoist getTotalNumVGPRs into AMDGPUBaseInfo for use in both codegen and MC
ClosedPublic

Authored by lamb-j on Feb 15 2022, 7:12 PM.

Details

Reviewers
kzhuravl
arsenm
rampitec
Commits
rG0bad7cb56526: Hoist getTotalNumVGPRs into AMDGPUBaseInfo for use in both codegen and MC

Diff Detail

Event Timeline

lamb-j created this revision.Feb 15 2022, 7:12 PM
Herald added subscribers: foad, kerbowa, hiraditya and 6 others. · View Herald TranscriptFeb 15 2022, 7:12 PM
lamb-j requested review of this revision.Feb 15 2022, 7:12 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 15 2022, 7:12 PM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
lamb-j added a parent revision: D116140: [AMDGPU] Add agpr_count to metadata and AsmParser.Feb 15 2022, 7:16 PM
Harbormaster completed remote builds in B149876: Diff 409121.Feb 15 2022, 7:51 PM
arsenm added inline comments.Feb 16 2022, 6:57 AM
llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
90

Don't need llvm::

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
1527

Formatting

rampitec added a comment.Feb 16 2022, 8:12 AM

Please fix clang-format notes as well.

lamb-j updated this revision to Diff 409303.Feb 16 2022, 9:47 AM

Removing llvm namespace from function call and addressing clang-format issues

Harbormaster completed remote builds in B149999: Diff 409303.Feb 16 2022, 9:48 AM
lamb-j updated this revision to Diff 409306.Feb 16 2022, 9:51 AM

Fix small formatting error

lamb-j marked 2 inline comments as done.Feb 16 2022, 9:52 AM
Harbormaster completed remote builds in B150001: Diff 409306.Feb 16 2022, 9:52 AM
arsenm accepted this revision.Feb 16 2022, 9:55 AM
This revision is now accepted and ready to land.Feb 16 2022, 9:55 AM
lamb-j updated this revision to Diff 409321.Feb 16 2022, 10:38 AM

Updating commit message

Harbormaster completed remote builds in B150012: Diff 409321.Feb 16 2022, 10:39 AM
This revision was landed with ongoing or failed builds.Feb 16 2022, 11:08 AM
Closed by commit rG0bad7cb56526: Hoist getTotalNumVGPRs into AMDGPUBaseInfo for use in both codegen and MC (authored by lamb-j). · Explain Why
This revision was automatically updated to reflect the committed changes.
lamb-j added a commit: rG0bad7cb56526: Hoist getTotalNumVGPRs into AMDGPUBaseInfo for use in both codegen and MC.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
4 lines
Utils/
1 line
7 lines

Diff 409339

llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Linesint32_t AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumSGPRs(
const GCNSubtarget &ST) const { const GCNSubtarget &ST) const {
return NumExplicitSGPR + return NumExplicitSGPR +
IsaInfo::getNumExtraSGPRs(&ST, UsesVCC, UsesFlatScratch, IsaInfo::getNumExtraSGPRs(&ST, UsesVCC, UsesFlatScratch,
ST.getTargetID().isXnackOnOrAny()); ST.getTargetID().isXnackOnOrAny());
} }
int32_t AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs( int32_t AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs(
const GCNSubtarget &ST, int32_t ArgNumAGPR, int32_t ArgNumVGPR) const { const GCNSubtarget &ST, int32_t ArgNumAGPR, int32_t ArgNumVGPR) const {
if (ST.hasGFX90AInsts() && ArgNumAGPR) return AMDGPU::getTotalNumVGPRs(ST.hasGFX90AInsts(), ArgNumAGPR, ArgNumVGPR);
arsenmUnsubmitted
Done
ReplyInline Actions

Don't need llvm::

arsenm: Don't need llvm::
return alignTo(ArgNumVGPR, 4) + ArgNumAGPR;
return std::max(ArgNumVGPR, ArgNumAGPR);
} }
int32_t AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs( int32_t AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs(
const GCNSubtarget &ST) const { const GCNSubtarget &ST) const {
return getTotalNumVGPRs(ST, NumAGPR, NumVGPR); return getTotalNumVGPRs(ST, NumAGPR, NumVGPR);
} }
bool AMDGPUResourceUsageAnalysis::runOnModule(Module &M) { bool AMDGPUResourceUsageAnalysis::runOnModule(Module &M) {
▲ Show 20 Lines • Show All 436 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Show First 20 Lines • Show All 769 Lines • ▼ Show 20 Lines
bool isGFX10(const MCSubtargetInfo &STI); bool isGFX10(const MCSubtargetInfo &STI);
bool isGFX10Plus(const MCSubtargetInfo &STI); bool isGFX10Plus(const MCSubtargetInfo &STI);
bool isGCN3Encoding(const MCSubtargetInfo &STI); bool isGCN3Encoding(const MCSubtargetInfo &STI);
bool isGFX10_AEncoding(const MCSubtargetInfo &STI); bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
bool isGFX10_BEncoding(const MCSubtargetInfo &STI); bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
bool hasGFX10_3Insts(const MCSubtargetInfo &STI); bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
bool isGFX90A(const MCSubtargetInfo &STI); bool isGFX90A(const MCSubtargetInfo &STI);
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI); bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
/// Is Reg - scalar register /// Is Reg - scalar register
bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI); bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
/// If \p Reg is a pseudo reg, return the correct hardware register given /// If \p Reg is a pseudo reg, return the correct hardware register given
/// \p STI otherwise return \p Reg. /// \p STI otherwise return \p Reg.
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI); unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
▲ Show 20 Lines • Show All 258 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Show First 20 Lines • Show All 1,517 Lines • ▼ Show 20 Lines
bool isGFX90A(const MCSubtargetInfo &STI) { bool isGFX90A(const MCSubtargetInfo &STI) {
return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts];
} }
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI) { bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI) {
return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];
} }
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR,
int32_t ArgNumVGPR) {
arsenmUnsubmitted
Done
ReplyInline Actions

Formatting

arsenm: Formatting
if (has90AInsts && ArgNumAGPR)
return alignTo(ArgNumVGPR, 4) + ArgNumAGPR;
return std::max(ArgNumVGPR, ArgNumAGPR);
}
bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) { bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID); const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0); const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) || return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
Reg == AMDGPU::SCC; Reg == AMDGPU::SCC;
} }
#define MAP_REG2REG \ #define MAP_REG2REG \
▲ Show 20 Lines • Show All 560 Lines • Show Last 20 Lines