[ARM] Recognize SSAT and USAT from SMIN/SMAX

[dmgreen]

Summary

We have some recognition of SSAT and USAT from SELECT_CC at the moment. This extends the matching to SMIN/SMAX which can help catch more cases, either from min/max being the canonical form in instcombine or from some expanded nodes like fp_to_si_sat.

[RKSimon]

Any reason why this couldn't be performed generically in DAGCombiner::visitIMINMAX?

[dmgreen]

In D119819#3324269, @RKSimon wrote:

Any reason why this couldn't be performed generically in DAGCombiner::visitIMINMAX?

I think ssat/usat are Arm specific things. There is not even an AArch64 equivalent.

[RKSimon]

Sorry - turns out I was half remembering D52286, which never even landed!

[SjoerdMeijer]

llvm/lib/Target/ARM/ARMISelLowering.cpp

1571

I was just curious if we need to set a target combine for SMAX given that SMIN is the root of the node that we are matching; don't know how that works exactly...

17566

Typo: we they

17615

Should we try PerformVQDMULHCombine if this returns SDValue()?

[dmgreen]

Thanks for taking a look.

llvm/lib/Target/ARM/ARMISelLowering.cpp

1571

The code tries to match min(max(..)) or max(min(..)), providing the bounds are correct. Both seem to come up in practice, from the tests we have. There is some code in PerformMinMaxToSatCombine that swaps the min and max nodes if it needs to.

17566

Oh yeah, will fix.

17615

The rest of this function looks at vectors under MVE. VQDMULH is only an MVE vector operation, so won't do anything for i32.

[SjoerdMeijer]

Ok, thanks, looks like a nice patch to me.

[dmgreen]

Thanks! Here's an update for that comment, to make sure I don't forget.

llvm/lib/Target/ARM/ARMISelLowering.cpp

 
   if (Subtarget->hasMVEIntegerOps())
     setTargetDAGCombine(ISD::VSELECT);
 
   if (Subtarget->hasV6Ops())
     setTargetDAGCombine(ISD::SRL);
   if (Subtarget->isThumb1Only())
     setTargetDAGCombine(ISD::SHL);
+  // Attempt to lower smin/smax to ssat/usat
+  if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) ||
+      Subtarget->isThumb2()) {
+    setTargetDAGCombine(ISD::SMIN);
+    setTargetDAGCombine(ISD::SMAX);
+  }
 
   setStackPointerRegisterToSaveRestore(ARM::SP);
 
   if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
       !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
     setSchedulingPreference(Sched::RegPressure);
   else
     setSchedulingPreference(Sched::Hybrid);
static SDValue PerformFPExtendCombine(SDNode *N, SelectionDAG &DAG,
                                       const ARMSubtarget *ST) {
   if (ST->hasMVEFloatOps())
     if (SDValue NewLoad = PerformSplittingToWideningLoad(N, DAG))
       return NewLoad;
 
   return SDValue();
 }
 
+// Lower smin(smax(x, C1), C2) to ssat or usat, if they have saturating
+// constant bounds.
+static SDValue PerformMinMaxToSatCombine(SDValue Op, SelectionDAG &DAG,
+                                         const ARMSubtarget *Subtarget) {
+  if ((Subtarget->isThumb() || !Subtarget->hasV6Ops()) &&
+      !Subtarget->isThumb2())
+    return SDValue();
+
+  EVT VT = Op.getValueType();
+  SDValue Op0 = Op.getOperand(0);
+
+  if (VT != MVT::i32 ||
+      (Op0.getOpcode() != ISD::SMIN && Op0.getOpcode() != ISD::SMAX) ||
+      !isa<ConstantSDNode>(Op.getOperand(1)) ||
+      !isa<ConstantSDNode>(Op0.getOperand(1)))
+    return SDValue();
+
+  SDValue Min = Op;
+  SDValue Max = Op0;
+  SDValue Input = Op0.getOperand(0);
+  if (Min.getOpcode() == ISD::SMAX)
+    std::swap(Min, Max);
+
+  APInt MinC = Min.getConstantOperandAPInt(1);
+  APInt MaxC = Max.getConstantOperandAPInt(1);
+
+  if (Min.getOpcode() != ISD::SMIN || Max.getOpcode() != ISD::SMAX ||
+      !(MinC + 1).isPowerOf2())
+    return SDValue();
+
+  SDLoc DL(Op);
+  if (MinC == ~MaxC)
+    return DAG.getNode(ARMISD::SSAT, DL, VT, Input,
+                       DAG.getConstant(MinC.countTrailingOnes(), DL, VT));
+  if (MaxC == 0)
+    return DAG.getNode(ARMISD::USAT, DL, VT, Input,
+                       DAG.getConstant(MinC.countTrailingOnes(), DL, VT));
+
+  return SDValue();
+}
+
 /// PerformMinMaxCombine - Target-specific DAG combining for creating truncating
 /// saturates.
 static SDValue PerformMinMaxCombine(SDNode *N, SelectionDAG &DAG,
                                     const ARMSubtarget *ST) {
   EVT VT = N->getValueType(0);
   SDValue N0 = N->getOperand(0);
+
+  if (VT == MVT::i32)
+    return PerformMinMaxToSatCombine(SDValue(N, 0), DAG, ST);
+
   if (!ST->hasMVEIntegerOps())
     return SDValue();
 
   if (SDValue V = PerformVQDMULHCombine(N, DAG))
     return V;
 
   if (VT != MVT::v4i32 && VT != MVT::v8i16)
     return SDValue();

llvm/test/CodeGen/ARM/fpclamptosat.ll

 ; SOFT-NEXT:    .long 4294934528 @ 0xffff8000
 ;
 ; VFP2-LABEL: stest_f64i16_mm:
 ; VFP2:       @ %bb.0: @ %entry
 ; VFP2-NEXT:    .save {r7, lr}
 ; VFP2-NEXT:    push {r7, lr}
 ; VFP2-NEXT:    vmov r0, r1, d0
 ; VFP2-NEXT:    bl __aeabi_d2iz
-; VFP2-NEXT:    movw r1, #32767
-; VFP2-NEXT:    cmp r0, r1
-; VFP2-NEXT:    it ge
-; VFP2-NEXT:    movge r0, r1
-; VFP2-NEXT:    movw r1, #32768
-; VFP2-NEXT:    movt r1, #65535
-; VFP2-NEXT:    cmn.w r0, #32768
-; VFP2-NEXT:    it le
-; VFP2-NEXT:    movle r0, r1
+; VFP2-NEXT:    ssat r0, #16, r0
 ; VFP2-NEXT:    pop {r7, pc}
 ;
 ; FULL-LABEL: stest_f64i16_mm:
 ; FULL:       @ %bb.0: @ %entry
 ; FULL-NEXT:    vcvt.s32.f64 s0, d0
-; FULL-NEXT:    movw r1, #32767
 ; FULL-NEXT:    vmov r0, s0
-; FULL-NEXT:    cmp r0, r1
-; FULL-NEXT:    csel r0, r0, r1, lt
-; FULL-NEXT:    movw r1, #32768
-; FULL-NEXT:    movt r1, #65535
-; FULL-NEXT:    cmn.w r0, #32768
-; FULL-NEXT:    csel r0, r0, r1, gt
+; FULL-NEXT:    ssat r0, #16, r0
 ; FULL-NEXT:    bx lr
 entry:
   %conv = fptosi double %x to i32
   %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 32767)
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 -32768)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }

 ; SOFT-NEXT:    .long 65535 @ 0xffff
 ;
 ; VFP2-LABEL: ustest_f64i16_mm:
 ; VFP2:       @ %bb.0: @ %entry
 ; VFP2-NEXT:    .save {r7, lr}
 ; VFP2-NEXT:    push {r7, lr}
 ; VFP2-NEXT:    vmov r0, r1, d0
 ; VFP2-NEXT:    bl __aeabi_d2iz
-; VFP2-NEXT:    movw r1, #65535
-; VFP2-NEXT:    cmp r0, r1
-; VFP2-NEXT:    it lt
-; VFP2-NEXT:    movlt r1, r0
-; VFP2-NEXT:    bic.w r0, r1, r1, asr #31
+; VFP2-NEXT:    usat r0, #16, r0
 ; VFP2-NEXT:    pop {r7, pc}
 ;
 ; FULL-LABEL: ustest_f64i16_mm:
 ; FULL:       @ %bb.0: @ %entry
 ; FULL-NEXT:    vcvt.s32.f64 s0, d0
-; FULL-NEXT:    movw r1, #65535
 ; FULL-NEXT:    vmov r0, s0
-; FULL-NEXT:    cmp r0, r1
-; FULL-NEXT:    csel r0, r0, r1, lt
-; FULL-NEXT:    bic.w r0, r0, r0, asr #31
+; FULL-NEXT:    usat r0, #16, r0
 ; FULL-NEXT:    bx lr
 entry:
   %conv = fptosi double %x to i32
   %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 65535)
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 0)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }

 ; SOFT-NEXT:    pop {r7, pc}
 ; SOFT-NEXT:    .p2align 2
 ; SOFT-NEXT:  @ %bb.5:
 ; SOFT-NEXT:  .LCPI39_0:
 ; SOFT-NEXT:    .long 32767 @ 0x7fff
 ; SOFT-NEXT:  .LCPI39_1:
 ; SOFT-NEXT:    .long 4294934528 @ 0xffff8000
 ;
-; VFP2-LABEL: stest_f32i16_mm:
-; VFP2:       @ %bb.0: @ %entry
-; VFP2-NEXT:    vcvt.s32.f32 s0, s0
-; VFP2-NEXT:    movw r1, #32767
-; VFP2-NEXT:    vmov r0, s0
-; VFP2-NEXT:    cmp r0, r1
-; VFP2-NEXT:    it lt
-; VFP2-NEXT:    movlt r1, r0
-; VFP2-NEXT:    movw r0, #32768
-; VFP2-NEXT:    cmn.w r1, #32768
-; VFP2-NEXT:    movt r0, #65535
-; VFP2-NEXT:    it gt
-; VFP2-NEXT:    movgt r0, r1
-; VFP2-NEXT:    bx lr
-;
-; FULL-LABEL: stest_f32i16_mm:
-; FULL:       @ %bb.0: @ %entry
-; FULL-NEXT:    vcvt.s32.f32 s0, s0
-; FULL-NEXT:    movw r1, #32767
-; FULL-NEXT:    vmov r0, s0
-; FULL-NEXT:    cmp r0, r1
-; FULL-NEXT:    csel r0, r0, r1, lt
-; FULL-NEXT:    movw r1, #32768
-; FULL-NEXT:    movt r1, #65535
-; FULL-NEXT:    cmn.w r0, #32768
-; FULL-NEXT:    csel r0, r0, r1, gt
-; FULL-NEXT:    bx lr
+; VFP-LABEL: stest_f32i16_mm:
+; VFP:       @ %bb.0: @ %entry
+; VFP-NEXT:    vcvt.s32.f32 s0, s0
+; VFP-NEXT:    vmov r0, s0
+; VFP-NEXT:    ssat r0, #16, r0
+; VFP-NEXT:    bx lr
 entry:
   %conv = fptosi float %x to i32
   %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 32767)
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 -32768)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 

 ; SOFT-NEXT:    asrs r1, r0, #31
 ; SOFT-NEXT:    bics r0, r1
 ; SOFT-NEXT:    pop {r7, pc}
 ; SOFT-NEXT:    .p2align 2
 ; SOFT-NEXT:  @ %bb.3:
 ; SOFT-NEXT:  .LCPI41_0:
 ; SOFT-NEXT:    .long 65535 @ 0xffff
 ;
-; VFP2-LABEL: ustest_f32i16_mm:
-; VFP2:       @ %bb.0: @ %entry
-; VFP2-NEXT:    vcvt.s32.f32 s0, s0
-; VFP2-NEXT:    movw r1, #65535
-; VFP2-NEXT:    vmov r0, s0
-; VFP2-NEXT:    cmp r0, r1
-; VFP2-NEXT:    it lt
-; VFP2-NEXT:    movlt r1, r0
-; VFP2-NEXT:    bic.w r0, r1, r1, asr #31
-; VFP2-NEXT:    bx lr
-;
-; FULL-LABEL: ustest_f32i16_mm:
-; FULL:       @ %bb.0: @ %entry
-; FULL-NEXT:    vcvt.s32.f32 s0, s0
-; FULL-NEXT:    movw r1, #65535
-; FULL-NEXT:    vmov r0, s0
-; FULL-NEXT:    cmp r0, r1
-; FULL-NEXT:    csel r0, r0, r1, lt
-; FULL-NEXT:    bic.w r0, r0, r0, asr #31
-; FULL-NEXT:    bx lr
+; VFP-LABEL: ustest_f32i16_mm:
+; VFP:       @ %bb.0: @ %entry
+; VFP-NEXT:    vcvt.s32.f32 s0, s0
+; VFP-NEXT:    vmov r0, s0
+; VFP-NEXT:    usat r0, #16, r0
+; VFP-NEXT:    bx lr
 entry:
   %conv = fptosi float %x to i32
   %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 65535)
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 0)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }
 

 ;
 ; VFP2-LABEL: stest_f16i16_mm:
 ; VFP2:       @ %bb.0: @ %entry
 ; VFP2-NEXT:    .save {r7, lr}
 ; VFP2-NEXT:    push {r7, lr}
 ; VFP2-NEXT:    vmov r0, s0
 ; VFP2-NEXT:    bl __aeabi_h2f
 ; VFP2-NEXT:    vmov s0, r0
-; VFP2-NEXT:    movw r1, #32767
 ; VFP2-NEXT:    vcvt.s32.f32 s0, s0
 ; VFP2-NEXT:    vmov r0, s0
-; VFP2-NEXT:    cmp r0, r1
-; VFP2-NEXT:    it lt
-; VFP2-NEXT:    movlt r1, r0
-; VFP2-NEXT:    movw r0, #32768
-; VFP2-NEXT:    cmn.w r1, #32768
-; VFP2-NEXT:    movt r0, #65535
-; VFP2-NEXT:    it gt
-; VFP2-NEXT:    movgt r0, r1
+; VFP2-NEXT:    ssat r0, #16, r0
 ; VFP2-NEXT:    pop {r7, pc}
 ;
 ; FULL-LABEL: stest_f16i16_mm:
 ; FULL:       @ %bb.0: @ %entry
 ; FULL-NEXT:    vcvt.s32.f16 s0, s0
-; FULL-NEXT:    movw r1, #32767
 ; FULL-NEXT:    vmov r0, s0
-; FULL-NEXT:    cmp r0, r1
-; FULL-NEXT:    csel r0, r0, r1, lt
-; FULL-NEXT:    movw r1, #32768
-; FULL-NEXT:    movt r1, #65535
-; FULL-NEXT:    cmn.w r0, #32768
-; FULL-NEXT:    csel r0, r0, r1, gt
+; FULL-NEXT:    ssat r0, #16, r0
 ; FULL-NEXT:    bx lr
 entry:
   %conv = fptosi half %x to i32
   %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 32767)
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 -32768)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }

 ;
 ; VFP2-LABEL: ustest_f16i16_mm:
 ; VFP2:       @ %bb.0: @ %entry
 ; VFP2-NEXT:    .save {r7, lr}
 ; VFP2-NEXT:    push {r7, lr}
 ; VFP2-NEXT:    vmov r0, s0
 ; VFP2-NEXT:    bl __aeabi_h2f
 ; VFP2-NEXT:    vmov s0, r0
-; VFP2-NEXT:    movw r1, #65535
 ; VFP2-NEXT:    vcvt.s32.f32 s0, s0
 ; VFP2-NEXT:    vmov r0, s0
-; VFP2-NEXT:    cmp r0, r1
-; VFP2-NEXT:    it lt
-; VFP2-NEXT:    movlt r1, r0
-; VFP2-NEXT:    bic.w r0, r1, r1, asr #31
+; VFP2-NEXT:    usat r0, #16, r0
 ; VFP2-NEXT:    pop {r7, pc}
 ;
 ; FULL-LABEL: ustest_f16i16_mm:
 ; FULL:       @ %bb.0: @ %entry
 ; FULL-NEXT:    vcvt.s32.f16 s0, s0
-; FULL-NEXT:    movw r1, #65535
 ; FULL-NEXT:    vmov r0, s0
-; FULL-NEXT:    cmp r0, r1
-; FULL-NEXT:    csel r0, r0, r1, lt
-; FULL-NEXT:    bic.w r0, r0, r0, asr #31
+; FULL-NEXT:    usat r0, #16, r0
 ; FULL-NEXT:    bx lr
 entry:
   %conv = fptosi half %x to i32
   %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 65535)
   %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 0)
   %conv6 = trunc i32 %spec.store.select7 to i16
   ret i16 %conv6
 }

llvm/test/CodeGen/ARM/sadd_sat.ll

 ; CHECK-T1-NEXT:  .LCPI2_0:
 ; CHECK-T1-NEXT:    .long 32767 @ 0x7fff
 ; CHECK-T1-NEXT:  .LCPI2_1:
 ; CHECK-T1-NEXT:    .long 4294934528 @ 0xffff8000
 ;
 ; CHECK-T2NODSP-LABEL: func16:
 ; CHECK-T2NODSP:       @ %bb.0:
 ; CHECK-T2NODSP-NEXT:    add r0, r1
-; CHECK-T2NODSP-NEXT:    movw r1, #32767
-; CHECK-T2NODSP-NEXT:    cmp r0, r1
-; CHECK-T2NODSP-NEXT:    it lt
-; CHECK-T2NODSP-NEXT:    movlt r1, r0
-; CHECK-T2NODSP-NEXT:    movw r0, #32768
-; CHECK-T2NODSP-NEXT:    cmn.w r1, #32768
-; CHECK-T2NODSP-NEXT:    movt r0, #65535
-; CHECK-T2NODSP-NEXT:    it gt
-; CHECK-T2NODSP-NEXT:    movgt r0, r1
+; CHECK-T2NODSP-NEXT:    ssat r0, #16, r0
 ; CHECK-T2NODSP-NEXT:    bx lr
 ;
 ; CHECK-T2DSP-LABEL: func16:
 ; CHECK-T2DSP:       @ %bb.0:
 ; CHECK-T2DSP-NEXT:    qadd16 r0, r0, r1
 ; CHECK-T2DSP-NEXT:    sxth r0, r0
 ; CHECK-T2DSP-NEXT:    bx lr
 ;

 ; CHECK-T1-NEXT:  @ %bb.3:
 ; CHECK-T1-NEXT:    mov r0, r1
 ; CHECK-T1-NEXT:  .LBB3_4:
 ; CHECK-T1-NEXT:    bx lr
 ;
 ; CHECK-T2NODSP-LABEL: func8:
 ; CHECK-T2NODSP:       @ %bb.0:
 ; CHECK-T2NODSP-NEXT:    add r0, r1
-; CHECK-T2NODSP-NEXT:    cmp r0, #127
-; CHECK-T2NODSP-NEXT:    it ge
-; CHECK-T2NODSP-NEXT:    movge r0, #127
-; CHECK-T2NODSP-NEXT:    cmn.w r0, #128
-; CHECK-T2NODSP-NEXT:    it le
-; CHECK-T2NODSP-NEXT:    mvnle r0, #127
+; CHECK-T2NODSP-NEXT:    ssat r0, #8, r0
 ; CHECK-T2NODSP-NEXT:    bx lr
 ;
 ; CHECK-T2DSP-LABEL: func8:
 ; CHECK-T2DSP:       @ %bb.0:
 ; CHECK-T2DSP-NEXT:    qadd8 r0, r0, r1
 ; CHECK-T2DSP-NEXT:    sxtb r0, r0
 ; CHECK-T2DSP-NEXT:    bx lr
 ;

 ; CHECK-T1-NEXT:  @ %bb.3:
 ; CHECK-T1-NEXT:    mov r0, r1
 ; CHECK-T1-NEXT:  .LBB4_4:
 ; CHECK-T1-NEXT:    bx lr
 ;
 ; CHECK-T2NODSP-LABEL: func3:
 ; CHECK-T2NODSP:       @ %bb.0:
 ; CHECK-T2NODSP-NEXT:    add r0, r1
-; CHECK-T2NODSP-NEXT:    cmp r0, #7
-; CHECK-T2NODSP-NEXT:    it ge
-; CHECK-T2NODSP-NEXT:    movge r0, #7
-; CHECK-T2NODSP-NEXT:    cmn.w r0, #8
-; CHECK-T2NODSP-NEXT:    it le
-; CHECK-T2NODSP-NEXT:    mvnle r0, #7
+; CHECK-T2NODSP-NEXT:    ssat r0, #4, r0
 ; CHECK-T2NODSP-NEXT:    bx lr
 ;
 ; CHECK-T2DSP-LABEL: func3:
 ; CHECK-T2DSP:       @ %bb.0:
 ; CHECK-T2DSP-NEXT:    lsls r1, r1, #28
 ; CHECK-T2DSP-NEXT:    lsls r0, r0, #28
 ; CHECK-T2DSP-NEXT:    qadd r0, r0, r1
 ; CHECK-T2DSP-NEXT:    asrs r0, r0, #28

llvm/test/CodeGen/ARM/sadd_sat_plus.ll

 ; CHECK-T1-NEXT:  .LCPI2_1:
 ; CHECK-T1-NEXT:    .long 4294934528 @ 0xffff8000
 ;
 ; CHECK-T2NODSP-LABEL: func16:
 ; CHECK-T2NODSP:       @ %bb.0:
 ; CHECK-T2NODSP-NEXT:    muls r1, r2, r1
 ; CHECK-T2NODSP-NEXT:    sxth r1, r1
 ; CHECK-T2NODSP-NEXT:    add r0, r1
-; CHECK-T2NODSP-NEXT:    movw r1, #32767
-; CHECK-T2NODSP-NEXT:    cmp r0, r1
-; CHECK-T2NODSP-NEXT:    it lt
-; CHECK-T2NODSP-NEXT:    movlt r1, r0
-; CHECK-T2NODSP-NEXT:    movw r0, #32768
-; CHECK-T2NODSP-NEXT:    movt r0, #65535
-; CHECK-T2NODSP-NEXT:    cmn.w r1, #32768
-; CHECK-T2NODSP-NEXT:    it gt
-; CHECK-T2NODSP-NEXT:    movgt r0, r1
+; CHECK-T2NODSP-NEXT:    ssat r0, #16, r0
 ; CHECK-T2NODSP-NEXT:    bx lr
 ;
 ; CHECK-T2DSP-LABEL: func16:
 ; CHECK-T2DSP:       @ %bb.0:
 ; CHECK-T2DSP-NEXT:    muls r1, r2, r1
 ; CHECK-T2DSP-NEXT:    qadd16 r0, r0, r1
 ; CHECK-T2DSP-NEXT:    sxth r0, r0
 ; CHECK-T2DSP-NEXT:    bx lr

 ; CHECK-T1-NEXT:  .LBB3_4:
 ; CHECK-T1-NEXT:    bx lr
 ;
 ; CHECK-T2NODSP-LABEL: func8:
 ; CHECK-T2NODSP:       @ %bb.0:
 ; CHECK-T2NODSP-NEXT:    muls r1, r2, r1
 ; CHECK-T2NODSP-NEXT:    sxtb r1, r1
 ; CHECK-T2NODSP-NEXT:    add r0, r1
-; CHECK-T2NODSP-NEXT:    cmp r0, #127
-; CHECK-T2NODSP-NEXT:    it ge
-; CHECK-T2NODSP-NEXT:    movge r0, #127
-; CHECK-T2NODSP-NEXT:    cmn.w r0, #128
-; CHECK-T2NODSP-NEXT:    it le
-; CHECK-T2NODSP-NEXT:    mvnle r0, #127
+; CHECK-T2NODSP-NEXT:    ssat r0, #8, r0
 ; CHECK-T2NODSP-NEXT:    bx lr
 ;
 ; CHECK-T2DSP-LABEL: func8:
 ; CHECK-T2DSP:       @ %bb.0:
 ; CHECK-T2DSP-NEXT:    muls r1, r2, r1
 ; CHECK-T2DSP-NEXT:    qadd8 r0, r0, r1
 ; CHECK-T2DSP-NEXT:    sxtb r0, r0
 ; CHECK-T2DSP-NEXT:    bx lr

 ; CHECK-T1-NEXT:  .LBB4_4:
 ; CHECK-T1-NEXT:    bx lr
 ;
 ; CHECK-T2NODSP-LABEL: func4:
 ; CHECK-T2NODSP:       @ %bb.0:
 ; CHECK-T2NODSP-NEXT:    muls r1, r2, r1
 ; CHECK-T2NODSP-NEXT:    lsls r1, r1, #28
 ; CHECK-T2NODSP-NEXT:    add.w r0, r0, r1, asr #28
-; CHECK-T2NODSP-NEXT:    cmp r0, #7
-; CHECK-T2NODSP-NEXT:    it ge
-; CHECK-T2NODSP-NEXT:    movge r0, #7
-; CHECK-T2NODSP-NEXT:    cmn.w r0, #8
-; CHECK-T2NODSP-NEXT:    it le
-; CHECK-T2NODSP-NEXT:    mvnle r0, #7
+; CHECK-T2NODSP-NEXT:    ssat r0, #4, r0
 ; CHECK-T2NODSP-NEXT:    bx lr
 ;
 ; CHECK-T2DSP-LABEL: func4:
 ; CHECK-T2DSP:       @ %bb.0:
 ; CHECK-T2DSP-NEXT:    muls r1, r2, r1
 ; CHECK-T2DSP-NEXT:    lsls r0, r0, #28
 ; CHECK-T2DSP-NEXT:    lsls r1, r1, #28
 ; CHECK-T2DSP-NEXT:    qadd r0, r0, r1

llvm/test/CodeGen/ARM/ssat-unroll-loops.ll

 
 while.end:                                        ; preds = %while.body, %while.body.prol.loopexit, %entry
   ret void
 }
 
 define void @ssat_unroll_minmax(i16* nocapture readonly %pSrcA, i16* nocapture readonly %pSrcB, i16* nocapture writeonly %pDst, i32 %blockSize) {
 ; CHECK-LABEL: ssat_unroll_minmax:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    .save {r4, r5, r11, lr}
-; CHECK-NEXT:    push {r4, r5, r11, lr}
+; CHECK-NEXT:    .save {r11, lr}
+; CHECK-NEXT:    push {r11, lr}
 ; CHECK-NEXT:    cmp r3, #0
-; CHECK-NEXT:    beq .LBB1_6
+; CHECK-NEXT:    beq .LBB1_5
 ; CHECK-NEXT:  @ %bb.1: @ %while.body.preheader
-; CHECK-NEXT:    movw r12, #32768
-; CHECK-NEXT:    sub lr, r3, #1
+; CHECK-NEXT:    sub r12, r3, #1
 ; CHECK-NEXT:    tst r3, #1
-; CHECK-NEXT:    movt r12, #65535
 ; CHECK-NEXT:    beq .LBB1_3
 ; CHECK-NEXT:  @ %bb.2: @ %while.body.prol.preheader
-; CHECK-NEXT:    ldrsh r3, [r0], #2
-; CHECK-NEXT:    ldrsh r4, [r1], #2
-; CHECK-NEXT:    smulbb r3, r4, r3
-; CHECK-NEXT:    asr r4, r3, #14
-; CHECK-NEXT:    cmn r4, #32768
-; CHECK-NEXT:    mov r4, r12
-; CHECK-NEXT:    asrgt r4, r3, #14
-; CHECK-NEXT:    movw r3, #32767
-; CHECK-NEXT:    cmp r4, r3
-; CHECK-NEXT:    movge r4, r3
-; CHECK-NEXT:    mov r3, lr
-; CHECK-NEXT:    strh r4, [r2], #2
+; CHECK-NEXT:    ldrsh lr, [r0], #2
+; CHECK-NEXT:    ldrsh r3, [r1], #2
+; CHECK-NEXT:    smulbb r3, r3, lr
+; CHECK-NEXT:    ssat r3, #16, r3, asr #14
+; CHECK-NEXT:    strh r3, [r2], #2
+; CHECK-NEXT:    mov r3, r12
 ; CHECK-NEXT:  .LBB1_3: @ %while.body.prol.loopexit
-; CHECK-NEXT:    cmp lr, #0
-; CHECK-NEXT:    beq .LBB1_6
-; CHECK-NEXT:  @ %bb.4: @ %while.body.preheader1
-; CHECK-NEXT:    movw lr, #32767
-; CHECK-NEXT:  .LBB1_5: @ %while.body
+; CHECK-NEXT:    cmp r12, #0
+; CHECK-NEXT:    popeq {r11, pc}
+; CHECK-NEXT:  .LBB1_4: @ %while.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    ldrsh r4, [r0]
-; CHECK-NEXT:    ldrsh r5, [r1]
-; CHECK-NEXT:    smulbb r4, r5, r4
-; CHECK-NEXT:    asr r5, r4, #14
-; CHECK-NEXT:    cmn r5, #32768
-; CHECK-NEXT:    mov r5, r12
-; CHECK-NEXT:    asrgt r5, r4, #14
-; CHECK-NEXT:    cmp r5, lr
-; CHECK-NEXT:    movge r5, lr
-; CHECK-NEXT:    strh r5, [r2]
-; CHECK-NEXT:    ldrsh r4, [r0, #2]
+; CHECK-NEXT:    ldrsh r12, [r0]
+; CHECK-NEXT:    subs r3, r3, #2
+; CHECK-NEXT:    ldrsh lr, [r1]
+; CHECK-NEXT:    smulbb r12, lr, r12
+; CHECK-NEXT:    ssat r12, #16, r12, asr #14
+; CHECK-NEXT:    strh r12, [r2]
+; CHECK-NEXT:    ldrsh r12, [r0, #2]
 ; CHECK-NEXT:    add r0, r0, #4
-; CHECK-NEXT:    ldrsh r5, [r1, #2]
+; CHECK-NEXT:    ldrsh lr, [r1, #2]
 ; CHECK-NEXT:    add r1, r1, #4
-; CHECK-NEXT:    smulbb r4, r5, r4
-; CHECK-NEXT:    asr r5, r4, #14
-; CHECK-NEXT:    cmn r5, #32768
-; CHECK-NEXT:    mov r5, r12
-; CHECK-NEXT:    asrgt r5, r4, #14
-; CHECK-NEXT:    cmp r5, lr
-; CHECK-NEXT:    movge r5, lr
-; CHECK-NEXT:    subs r3, r3, #2
-; CHECK-NEXT:    strh r5, [r2, #2]
+; CHECK-NEXT:    smulbb r12, lr, r12
+; CHECK-NEXT:    ssat r12, #16, r12, asr #14
+; CHECK-NEXT:    strh r12, [r2, #2]
 ; CHECK-NEXT:    add r2, r2, #4
-; CHECK-NEXT:    bne .LBB1_5
-; CHECK-NEXT:  .LBB1_6: @ %while.end
-; CHECK-NEXT:    pop {r4, r5, r11, pc}
+; CHECK-NEXT:    bne .LBB1_4
+; CHECK-NEXT:  .LBB1_5: @ %while.end
+; CHECK-NEXT:    pop {r11, pc}
 entry:
   %cmp.not7 = icmp eq i32 %blockSize, 0
   br i1 %cmp.not7, label %while.end, label %while.body.preheader
 
 while.body.preheader:                             ; preds = %entry
   %0 = add i32 %blockSize, -1
   %xtraiter = and i32 %blockSize, 1
   %lcmp.mod.not = icmp eq i32 %xtraiter, 0

llvm/test/CodeGen/ARM/ssat.ll

 ; V4T-NEXT:    bx lr
 ; V4T-NEXT:    .p2align 2
 ; V4T-NEXT:  @ %bb.1:
 ; V4T-NEXT:  .LCPI18_0:
 ; V4T-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6T2-LABEL: mm_sat_base_32bit:
 ; V6T2:       @ %bb.0: @ %entry
-; V6T2-NEXT:    movw r1, #65535
-; V6T2-NEXT:    movt r1, #127
-; V6T2-NEXT:    cmp r0, r1
-; V6T2-NEXT:    movge r0, r1
-; V6T2-NEXT:    movw r1, #0
-; V6T2-NEXT:    movt r1, #65408
-; V6T2-NEXT:    cmn r0, #8388608
-; V6T2-NEXT:    movle r0, r1
+; V6T2-NEXT:    ssat r0, #24, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
   %1 = call i32 @llvm.smax.i32(i32 %0, i32 -8388608)
   ret i32 %1
 }
 
 define i16 @mm_sat_base_16bit(i16 %x) {

 ; V4T-NEXT:    .p2align 2
 ; V4T-NEXT:  @ %bb.1:
 ; V4T-NEXT:  .LCPI19_0:
 ; V4T-NEXT:    .long 4294965248 @ 0xfffff800
 ;
 ; V6T2-LABEL: mm_sat_base_16bit:
 ; V6T2:       @ %bb.0: @ %entry
 ; V6T2-NEXT:    sxth r0, r0
-; V6T2-NEXT:    movw r1, #2047
-; V6T2-NEXT:    cmp r0, r1
-; V6T2-NEXT:    movlt r1, r0
-; V6T2-NEXT:    movw r0, #63488
-; V6T2-NEXT:    movt r0, #65535
-; V6T2-NEXT:    cmn r1, #2048
-; V6T2-NEXT:    movgt r0, r1
+; V6T2-NEXT:    ssat r0, #12, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i16 @llvm.smin.i16(i16 %x, i16 2047)
   %1 = call i16 @llvm.smax.i16(i16 %0, i16 -2048)
   ret i16 %1
 }
 
 define i8 @mm_sat_base_8bit(i8 %x) {
 ; V4T-LABEL: mm_sat_base_8bit:
 ; V4T:       @ %bb.0: @ %entry
 ; V4T-NEXT:    lsl r1, r0, #24
 ; V4T-NEXT:    mov r0, #31
 ; V4T-NEXT:    asr r2, r1, #24
 ; V4T-NEXT:    cmp r2, #31
 ; V4T-NEXT:    asrlt r0, r1, #24
 ; V4T-NEXT:    cmn r0, #32
 ; V4T-NEXT:    mvnle r0, #31
 ; V4T-NEXT:    bx lr
 ;
 ; V6T2-LABEL: mm_sat_base_8bit:
 ; V6T2:       @ %bb.0: @ %entry
 ; V6T2-NEXT:    sxtb r0, r0
-; V6T2-NEXT:    cmp r0, #31
-; V6T2-NEXT:    movge r0, #31
-; V6T2-NEXT:    cmn r0, #32
-; V6T2-NEXT:    mvnle r0, #31
+; V6T2-NEXT:    ssat r0, #6, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i8 @llvm.smin.i8(i8 %x, i8 31)
   %1 = call i8 @llvm.smax.i8(i8 %0, i8 -32)
   ret i8 %1
 }
 
 define i32 @mm_sat_lower_upper_1(i32 %x) {

 ; V4T-NEXT:    bx lr
 ; V4T-NEXT:    .p2align 2
 ; V4T-NEXT:  @ %bb.1:
 ; V4T-NEXT:  .LCPI21_0:
 ; V4T-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6T2-LABEL: mm_sat_lower_upper_1:
 ; V6T2:       @ %bb.0: @ %entry
-; V6T2-NEXT:    movw r1, #65535
-; V6T2-NEXT:    movt r1, #127
-; V6T2-NEXT:    cmp r0, r1
-; V6T2-NEXT:    movge r0, r1
-; V6T2-NEXT:    movw r1, #0
-; V6T2-NEXT:    movt r1, #65408
-; V6T2-NEXT:    cmn r0, #8388608
-; V6T2-NEXT:    movle r0, r1
+; V6T2-NEXT:    ssat r0, #24, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
   %1 = call i32 @llvm.smax.i32(i32 %0, i32 -8388608)
   ret i32 %1
 }
 
 define i32 @mm_sat_lower_upper_2(i32 %x) {

 ; V4T-NEXT:    bx lr
 ; V4T-NEXT:    .p2align 2
 ; V4T-NEXT:  @ %bb.1:
 ; V4T-NEXT:  .LCPI22_0:
 ; V4T-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6T2-LABEL: mm_sat_lower_upper_2:
 ; V6T2:       @ %bb.0: @ %entry
-; V6T2-NEXT:    movw r1, #65535
-; V6T2-NEXT:    movt r1, #127
-; V6T2-NEXT:    cmp r0, r1
-; V6T2-NEXT:    movge r0, r1
-; V6T2-NEXT:    movw r1, #0
-; V6T2-NEXT:    movt r1, #65408
-; V6T2-NEXT:    cmn r0, #8388608
-; V6T2-NEXT:    movle r0, r1
+; V6T2-NEXT:    ssat r0, #24, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
   %1 = call i32 @llvm.smax.i32(i32 %0, i32 -8388608)
   ret i32 %1
 }
 
 define i32 @mm_sat_upper_lower_1(i32 %x) {

 ; V4T-NEXT:    bx lr
 ; V4T-NEXT:    .p2align 2
 ; V4T-NEXT:  @ %bb.1:
 ; V4T-NEXT:  .LCPI23_0:
 ; V4T-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6T2-LABEL: mm_sat_upper_lower_1:
 ; V6T2:       @ %bb.0: @ %entry
-; V6T2-NEXT:    movw r1, #0
-; V6T2-NEXT:    cmn r0, #8388608
-; V6T2-NEXT:    movt r1, #65408
-; V6T2-NEXT:    movle r0, r1
-; V6T2-NEXT:    movw r1, #65535
-; V6T2-NEXT:    movt r1, #127
-; V6T2-NEXT:    cmp r0, r1
-; V6T2-NEXT:    movge r0, r1
+; V6T2-NEXT:    ssat r0, #24, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i32 @llvm.smax.i32(i32 %x, i32 -8388608)
   %1 = call i32 @llvm.smin.i32(i32 %0, i32 8388607)
   ret i32 %1
 }
 
 define i32 @mm_sat_upper_lower_2(i32 %x) {

 ; V4T-NEXT:    bx lr
 ; V4T-NEXT:    .p2align 2
 ; V4T-NEXT:  @ %bb.1:
 ; V4T-NEXT:  .LCPI24_0:
 ; V4T-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6T2-LABEL: mm_sat_upper_lower_2:
 ; V6T2:       @ %bb.0: @ %entry
-; V6T2-NEXT:    movw r1, #0
-; V6T2-NEXT:    cmn r0, #8388608
-; V6T2-NEXT:    movt r1, #65408
-; V6T2-NEXT:    movle r0, r1
-; V6T2-NEXT:    movw r1, #65535
-; V6T2-NEXT:    movt r1, #127
-; V6T2-NEXT:    cmp r0, r1
-; V6T2-NEXT:    movge r0, r1
+; V6T2-NEXT:    ssat r0, #24, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i32 @llvm.smax.i32(i32 %x, i32 -8388608)
   %1 = call i32 @llvm.smin.i32(i32 %0, i32 8388607)
   ret i32 %1
 }
 
 define i32 @mm_sat_upper_lower_3(i32 %x) {

 ; V4T-NEXT:    bx lr
 ; V4T-NEXT:    .p2align 2
 ; V4T-NEXT:  @ %bb.1:
 ; V4T-NEXT:  .LCPI25_0:
 ; V4T-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6T2-LABEL: mm_sat_upper_lower_3:
 ; V6T2:       @ %bb.0: @ %entry
-; V6T2-NEXT:    movw r1, #0
-; V6T2-NEXT:    cmn r0, #8388608
-; V6T2-NEXT:    movt r1, #65408
-; V6T2-NEXT:    movle r0, r1
-; V6T2-NEXT:    movw r1, #65535
-; V6T2-NEXT:    movt r1, #127
-; V6T2-NEXT:    cmp r0, r1
-; V6T2-NEXT:    movge r0, r1
+; V6T2-NEXT:    ssat r0, #24, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i32 @llvm.smax.i32(i32 %x, i32 -8388608)
   %1 = call i32 @llvm.smin.i32(i32 %0, i32 8388607)
   ret i32 %1
 }
 
 define i32 @mm_sat_le_ge(i32 %x) {

 ; V4T-NEXT:    bx lr
 ; V4T-NEXT:    .p2align 2
 ; V4T-NEXT:  @ %bb.1:
 ; V4T-NEXT:  .LCPI26_0:
 ; V4T-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6T2-LABEL: mm_sat_le_ge:
 ; V6T2:       @ %bb.0: @ %entry
-; V6T2-NEXT:    movw r1, #0
-; V6T2-NEXT:    cmn r0, #8388608
-; V6T2-NEXT:    movt r1, #65408
-; V6T2-NEXT:    movle r0, r1
-; V6T2-NEXT:    movw r1, #65535
-; V6T2-NEXT:    movt r1, #127
-; V6T2-NEXT:    cmp r0, r1
-; V6T2-NEXT:    movge r0, r1
+; V6T2-NEXT:    ssat r0, #24, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i32 @llvm.smax.i32(i32 %x, i32 -8388608)
   %1 = call i32 @llvm.smin.i32(i32 %0, i32 8388607)
   ret i32 %1
 }
 
 define i32 @mm_no_sat_incorrect_interval(i32 %x) {

llvm/test/CodeGen/ARM/ssub_sat.ll

 ; CHECK-T1-NEXT:  .LCPI2_0:
 ; CHECK-T1-NEXT:    .long 32767 @ 0x7fff
 ; CHECK-T1-NEXT:  .LCPI2_1:
 ; CHECK-T1-NEXT:    .long 4294934528 @ 0xffff8000
 ;
 ; CHECK-T2NODSP-LABEL: func16:
 ; CHECK-T2NODSP:       @ %bb.0:
 ; CHECK-T2NODSP-NEXT:    subs r0, r0, r1
-; CHECK-T2NODSP-NEXT:    movw r1, #32767
-; CHECK-T2NODSP-NEXT:    cmp r0, r1
-; CHECK-T2NODSP-NEXT:    it lt
-; CHECK-T2NODSP-NEXT:    movlt r1, r0
-; CHECK-T2NODSP-NEXT:    movw r0, #32768
-; CHECK-T2NODSP-NEXT:    cmn.w r1, #32768
-; CHECK-T2NODSP-NEXT:    movt r0, #65535
-; CHECK-T2NODSP-NEXT:    it gt
-; CHECK-T2NODSP-NEXT:    movgt r0, r1
+; CHECK-T2NODSP-NEXT:    ssat r0, #16, r0
 ; CHECK-T2NODSP-NEXT:    bx lr
 ;
 ; CHECK-T2DSP-LABEL: func16:
 ; CHECK-T2DSP:       @ %bb.0:
 ; CHECK-T2DSP-NEXT:    qsub16 r0, r0, r1
 ; CHECK-T2DSP-NEXT:    sxth r0, r0
 ; CHECK-T2DSP-NEXT:    bx lr
 ;

 ; CHECK-T1-NEXT:  @ %bb.3:
 ; CHECK-T1-NEXT:    mov r0, r1
 ; CHECK-T1-NEXT:  .LBB3_4:
 ; CHECK-T1-NEXT:    bx lr
 ;
 ; CHECK-T2NODSP-LABEL: func8:
 ; CHECK-T2NODSP:       @ %bb.0:
 ; CHECK-T2NODSP-NEXT:    subs r0, r0, r1
-; CHECK-T2NODSP-NEXT:    cmp r0, #127
-; CHECK-T2NODSP-NEXT:    it ge
-; CHECK-T2NODSP-NEXT:    movge r0, #127
-; CHECK-T2NODSP-NEXT:    cmn.w r0, #128
-; CHECK-T2NODSP-NEXT:    it le
-; CHECK-T2NODSP-NEXT:    mvnle r0, #127
+; CHECK-T2NODSP-NEXT:    ssat r0, #8, r0
 ; CHECK-T2NODSP-NEXT:    bx lr
 ;
 ; CHECK-T2DSP-LABEL: func8:
 ; CHECK-T2DSP:       @ %bb.0:
 ; CHECK-T2DSP-NEXT:    qsub8 r0, r0, r1
 ; CHECK-T2DSP-NEXT:    sxtb r0, r0
 ; CHECK-T2DSP-NEXT:    bx lr
 ;

 ; CHECK-T1-NEXT:  @ %bb.3:
 ; CHECK-T1-NEXT:    mov r0, r1
 ; CHECK-T1-NEXT:  .LBB4_4:
 ; CHECK-T1-NEXT:    bx lr
 ;
 ; CHECK-T2NODSP-LABEL: func3:
 ; CHECK-T2NODSP:       @ %bb.0:
 ; CHECK-T2NODSP-NEXT:    subs r0, r0, r1
-; CHECK-T2NODSP-NEXT:    cmp r0, #7
-; CHECK-T2NODSP-NEXT:    it ge
-; CHECK-T2NODSP-NEXT:    movge r0, #7
-; CHECK-T2NODSP-NEXT:    cmn.w r0, #8
-; CHECK-T2NODSP-NEXT:    it le
-; CHECK-T2NODSP-NEXT:    mvnle r0, #7
+; CHECK-T2NODSP-NEXT:    ssat r0, #4, r0
 ; CHECK-T2NODSP-NEXT:    bx lr
 ;
 ; CHECK-T2DSP-LABEL: func3:
 ; CHECK-T2DSP:       @ %bb.0:
 ; CHECK-T2DSP-NEXT:    lsls r1, r1, #28
 ; CHECK-T2DSP-NEXT:    lsls r0, r0, #28
 ; CHECK-T2DSP-NEXT:    qsub r0, r0, r1
 ; CHECK-T2DSP-NEXT:    asrs r0, r0, #28

llvm/test/CodeGen/ARM/ssub_sat_plus.ll

 ; CHECK-T1-NEXT:  .LCPI2_1:
 ; CHECK-T1-NEXT:    .long 4294934528 @ 0xffff8000
 ;
 ; CHECK-T2NODSP-LABEL: func16:
 ; CHECK-T2NODSP:       @ %bb.0:
 ; CHECK-T2NODSP-NEXT:    muls r1, r2, r1
 ; CHECK-T2NODSP-NEXT:    sxth r1, r1
 ; CHECK-T2NODSP-NEXT:    subs r0, r0, r1
-; CHECK-T2NODSP-NEXT:    movw r1, #32767
-; CHECK-T2NODSP-NEXT:    cmp r0, r1
-; CHECK-T2NODSP-NEXT:    it lt
-; CHECK-T2NODSP-NEXT:    movlt r1, r0
-; CHECK-T2NODSP-NEXT:    movw r0, #32768
-; CHECK-T2NODSP-NEXT:    movt r0, #65535
-; CHECK-T2NODSP-NEXT:    cmn.w r1, #32768
-; CHECK-T2NODSP-NEXT:    it gt
-; CHECK-T2NODSP-NEXT:    movgt r0, r1
+; CHECK-T2NODSP-NEXT:    ssat r0, #16, r0
 ; CHECK-T2NODSP-NEXT:    bx lr
 ;
 ; CHECK-T2DSP-LABEL: func16:
 ; CHECK-T2DSP:       @ %bb.0:
 ; CHECK-T2DSP-NEXT:    muls r1, r2, r1
 ; CHECK-T2DSP-NEXT:    qsub16 r0, r0, r1
 ; CHECK-T2DSP-NEXT:    sxth r0, r0
 ; CHECK-T2DSP-NEXT:    bx lr

 ; CHECK-T1-NEXT:  .LBB3_4:
 ; CHECK-T1-NEXT:    bx lr
 ;
 ; CHECK-T2NODSP-LABEL: func8:
 ; CHECK-T2NODSP:       @ %bb.0:
 ; CHECK-T2NODSP-NEXT:    muls r1, r2, r1
 ; CHECK-T2NODSP-NEXT:    sxtb r1, r1
 ; CHECK-T2NODSP-NEXT:    subs r0, r0, r1
-; CHECK-T2NODSP-NEXT:    cmp r0, #127
-; CHECK-T2NODSP-NEXT:    it ge
-; CHECK-T2NODSP-NEXT:    movge r0, #127
-; CHECK-T2NODSP-NEXT:    cmn.w r0, #128
-; CHECK-T2NODSP-NEXT:    it le
-; CHECK-T2NODSP-NEXT:    mvnle r0, #127
+; CHECK-T2NODSP-NEXT:    ssat r0, #8, r0
 ; CHECK-T2NODSP-NEXT:    bx lr
 ;
 ; CHECK-T2DSP-LABEL: func8:
 ; CHECK-T2DSP:       @ %bb.0:
 ; CHECK-T2DSP-NEXT:    muls r1, r2, r1
 ; CHECK-T2DSP-NEXT:    qsub8 r0, r0, r1
 ; CHECK-T2DSP-NEXT:    sxtb r0, r0
 ; CHECK-T2DSP-NEXT:    bx lr

 ; CHECK-T1-NEXT:  .LBB4_4:
 ; CHECK-T1-NEXT:    bx lr
 ;
 ; CHECK-T2NODSP-LABEL: func4:
 ; CHECK-T2NODSP:       @ %bb.0:
 ; CHECK-T2NODSP-NEXT:    muls r1, r2, r1
 ; CHECK-T2NODSP-NEXT:    lsls r1, r1, #28
 ; CHECK-T2NODSP-NEXT:    sub.w r0, r0, r1, asr #28
-; CHECK-T2NODSP-NEXT:    cmp r0, #7
-; CHECK-T2NODSP-NEXT:    it ge
-; CHECK-T2NODSP-NEXT:    movge r0, #7
-; CHECK-T2NODSP-NEXT:    cmn.w r0, #8
-; CHECK-T2NODSP-NEXT:    it le
-; CHECK-T2NODSP-NEXT:    mvnle r0, #7
+; CHECK-T2NODSP-NEXT:    ssat r0, #4, r0
 ; CHECK-T2NODSP-NEXT:    bx lr
 ;
 ; CHECK-T2DSP-LABEL: func4:
 ; CHECK-T2DSP:       @ %bb.0:
 ; CHECK-T2DSP-NEXT:    muls r1, r2, r1
 ; CHECK-T2DSP-NEXT:    lsls r0, r0, #28
 ; CHECK-T2DSP-NEXT:    lsls r1, r1, #28
 ; CHECK-T2DSP-NEXT:    qsub r0, r0, r1

llvm/test/CodeGen/ARM/usat.ll

 ; V4T-NEXT:    bx lr
 ; V4T-NEXT:    .p2align 2
 ; V4T-NEXT:  @ %bb.1:
 ; V4T-NEXT:  .LCPI15_0:
 ; V4T-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6-LABEL: mm_unsigned_sat_base_32bit:
 ; V6:       @ %bb.0: @ %entry
-; V6-NEXT:    ldr r1, .LCPI15_0
-; V6-NEXT:    cmp r0, r1
-; V6-NEXT:    movlt r1, r0
-; V6-NEXT:    bic r0, r1, r1, asr #31
+; V6-NEXT:    usat r0, #23, r0
 ; V6-NEXT:    bx lr
-; V6-NEXT:    .p2align 2
-; V6-NEXT:  @ %bb.1:
-; V6-NEXT:  .LCPI15_0:
-; V6-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6T2-LABEL: mm_unsigned_sat_base_32bit:
 ; V6T2:       @ %bb.0: @ %entry
-; V6T2-NEXT:    movw r1, #65535
-; V6T2-NEXT:    movt r1, #127
-; V6T2-NEXT:    cmp r0, r1
-; V6T2-NEXT:    movlt r1, r0
-; V6T2-NEXT:    bic r0, r1, r1, asr #31
+; V6T2-NEXT:    usat r0, #23, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
   %1 = call i32 @llvm.smax.i32(i32 %0, i32 0)
   ret i32 %1
 }
 
 define i16 @mm_unsigned_sat_base_16bit(i16 %x) {
 ; V4T-LABEL: mm_unsigned_sat_base_16bit:
 ; V4T:       @ %bb.0: @ %entry
 ; V4T-NEXT:    mov r2, #255
 ; V4T-NEXT:    lsl r0, r0, #16
 ; V4T-NEXT:    orr r2, r2, #1792
 ; V4T-NEXT:    asr r1, r0, #16
 ; V4T-NEXT:    cmp r1, r2
 ; V4T-NEXT:    asrlt r2, r0, #16
 ; V4T-NEXT:    bic r0, r2, r2, asr #31
 ; V4T-NEXT:    bx lr
 ;
 ; V6-LABEL: mm_unsigned_sat_base_16bit:
 ; V6:       @ %bb.0: @ %entry
-; V6-NEXT:    mov r1, #255
 ; V6-NEXT:    sxth r0, r0
-; V6-NEXT:    orr r1, r1, #1792
-; V6-NEXT:    cmp r0, r1
-; V6-NEXT:    movlt r1, r0
-; V6-NEXT:    bic r0, r1, r1, asr #31
+; V6-NEXT:    usat r0, #11, r0
 ; V6-NEXT:    bx lr
 ;
 ; V6T2-LABEL: mm_unsigned_sat_base_16bit:
 ; V6T2:       @ %bb.0: @ %entry
 ; V6T2-NEXT:    sxth r0, r0
-; V6T2-NEXT:    movw r1, #2047
-; V6T2-NEXT:    cmp r0, r1
-; V6T2-NEXT:    movlt r1, r0
-; V6T2-NEXT:    bic r0, r1, r1, asr #31
+; V6T2-NEXT:    usat r0, #11, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i16 @llvm.smin.i16(i16 %x, i16 2047)
   %1 = call i16 @llvm.smax.i16(i16 %0, i16 0)
   ret i16 %1
 }
 
 define i8 @mm_unsigned_sat_base_8bit(i8 %x) {
 ; V4T-LABEL: mm_unsigned_sat_base_8bit:
 ; V4T:       @ %bb.0: @ %entry
 ; V4T-NEXT:    lsl r0, r0, #24
 ; V4T-NEXT:    mov r2, #31
 ; V4T-NEXT:    asr r1, r0, #24
 ; V4T-NEXT:    cmp r1, #31
 ; V4T-NEXT:    asrlt r2, r0, #24
 ; V4T-NEXT:    bic r0, r2, r2, asr #31
 ; V4T-NEXT:    bx lr
 ;
 ; V6-LABEL: mm_unsigned_sat_base_8bit:
 ; V6:       @ %bb.0: @ %entry
 ; V6-NEXT:    sxtb r0, r0
-; V6-NEXT:    cmp r0, #31
-; V6-NEXT:    movge r0, #31
-; V6-NEXT:    bic r0, r0, r0, asr #31
+; V6-NEXT:    usat r0, #5, r0
 ; V6-NEXT:    bx lr
 ;
 ; V6T2-LABEL: mm_unsigned_sat_base_8bit:
 ; V6T2:       @ %bb.0: @ %entry
 ; V6T2-NEXT:    sxtb r0, r0
-; V6T2-NEXT:    cmp r0, #31
-; V6T2-NEXT:    movge r0, #31
-; V6T2-NEXT:    bic r0, r0, r0, asr #31
+; V6T2-NEXT:    usat r0, #5, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i8 @llvm.smin.i8(i8 %x, i8 31)
   %1 = call i8 @llvm.smax.i8(i8 %0, i8 0)
   ret i8 %1
 }
 
 define i32 @mm_unsigned_sat_lower_upper_1(i32 %x) {
 ; V4T-LABEL: mm_unsigned_sat_lower_upper_1:
 ; V4T:       @ %bb.0: @ %entry
 ; V4T-NEXT:    ldr r1, .LCPI18_0
 ; V4T-NEXT:    cmp r0, r1
 ; V4T-NEXT:    movlt r1, r0
 ; V4T-NEXT:    bic r0, r1, r1, asr #31
 ; V4T-NEXT:    bx lr
 ; V4T-NEXT:    .p2align 2
 ; V4T-NEXT:  @ %bb.1:
 ; V4T-NEXT:  .LCPI18_0:
 ; V4T-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6-LABEL: mm_unsigned_sat_lower_upper_1:
 ; V6:       @ %bb.0: @ %entry
-; V6-NEXT:    ldr r1, .LCPI18_0
-; V6-NEXT:    cmp r0, r1
-; V6-NEXT:    movlt r1, r0
-; V6-NEXT:    bic r0, r1, r1, asr #31
+; V6-NEXT:    usat r0, #23, r0
 ; V6-NEXT:    bx lr
-; V6-NEXT:    .p2align 2
-; V6-NEXT:  @ %bb.1:
-; V6-NEXT:  .LCPI18_0:
-; V6-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6T2-LABEL: mm_unsigned_sat_lower_upper_1:
 ; V6T2:       @ %bb.0: @ %entry
-; V6T2-NEXT:    movw r1, #65535
-; V6T2-NEXT:    movt r1, #127
-; V6T2-NEXT:    cmp r0, r1
-; V6T2-NEXT:    movlt r1, r0
-; V6T2-NEXT:    bic r0, r1, r1, asr #31
+; V6T2-NEXT:    usat r0, #23, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
   %1 = call i32 @llvm.smax.i32(i32 %0, i32 0)
   ret i32 %1
 }
 
 define i32 @mm_unsigned_sat_lower_upper_2(i32 %x) {
 ; V4T-LABEL: mm_unsigned_sat_lower_upper_2:
 ; V4T:       @ %bb.0: @ %entry
 ; V4T-NEXT:    ldr r1, .LCPI19_0
 ; V4T-NEXT:    cmp r0, r1
 ; V4T-NEXT:    movlt r1, r0
 ; V4T-NEXT:    bic r0, r1, r1, asr #31
 ; V4T-NEXT:    bx lr
 ; V4T-NEXT:    .p2align 2
 ; V4T-NEXT:  @ %bb.1:
 ; V4T-NEXT:  .LCPI19_0:
 ; V4T-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6-LABEL: mm_unsigned_sat_lower_upper_2:
 ; V6:       @ %bb.0: @ %entry
-; V6-NEXT:    ldr r1, .LCPI19_0
-; V6-NEXT:    cmp r0, r1
-; V6-NEXT:    movlt r1, r0
-; V6-NEXT:    bic r0, r1, r1, asr #31
+; V6-NEXT:    usat r0, #23, r0
 ; V6-NEXT:    bx lr
-; V6-NEXT:    .p2align 2
-; V6-NEXT:  @ %bb.1:
-; V6-NEXT:  .LCPI19_0:
-; V6-NEXT:    .long 8388607 @ 0x7fffff
 ;
 ; V6T2-LABEL: mm_unsigned_sat_lower_upper_2:
 ; V6T2:       @ %bb.0: @ %entry
-; V6T2-NEXT:    movw r1, #65535
-; V6T2-NEXT:    movt r1, #127
-; V6T2-NEXT:    cmp r0, r1
-; V6T2-NEXT:    movlt r1, r0
-; V6T2-NEXT:    bic r0, r1, r1, asr #31
+; V6T2-NEXT:    usat r0, #23, r0
 ; V6T2-NEXT:    bx lr
 entry:
   %0 = call i32 @llvm.smin.i32(i32 %x, i32 8388607)
   %1 = call i32 @llvm.smax.i32(i32 %0, i32 0)
   ret i32 %1
 }
 
 define i32 @mm_unsigned_sat_upper_lower_1(i32 %x) {