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Differential D119639

[NVPTX] Fix bug with int_nvvm_rotate_b64 when operand immediate
ClosedPublic

Authored by slydiman on Feb 12 2022, 10:43 AM.

Details

Reviewers
JackAKirk
c-rhodes
steffenlarsen
nyalloc
asavonic
krisb
tra
Commits
rG6645bfa8f501: [NVPTX] Fix bug with int_nvvm_rotate_b64 when operand immediate
Summary

Need to subract from 64, not 32.

Diff Detail

Event Timeline

slydiman created this revision.Feb 12 2022, 10:43 AM
Herald added subscribers: hiraditya, jholewinski. · View Herald TranscriptFeb 12 2022, 10:43 AM
slydiman requested review of this revision.Feb 12 2022, 10:43 AM
Herald added subscribers: llvm-commits, jdoerfert. · View Herald TranscriptFeb 12 2022, 10:43 AM
Harbormaster completed remote builds in B149223: Diff 408195.Feb 12 2022, 11:15 AM
tra accepted this revision.Feb 14 2022, 1:46 PM
tra added a subscriber: tra.

Good catch! LGTM.

This revision is now accepted and ready to land.Feb 14 2022, 1:46 PM
This revision was landed with ongoing or failed builds.Feb 14 2022, 2:24 PM
Closed by commit rG6645bfa8f501: [NVPTX] Fix bug with int_nvvm_rotate_b64 when operand immediate (authored by slydiman). · Explain Why
This revision was automatically updated to reflect the committed changes.
slydiman added a commit: rG6645bfa8f501: [NVPTX] Fix bug with int_nvvm_rotate_b64 when operand immediate.

Revision Contents

PathSize
llvm/
lib/
Target/
NVPTX/
2 lines
test/
CodeGen/
NVPTX/
25 lines

Diff 408622

llvm/lib/Target/NVPTX/NVPTXIntrinsics.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,467 Lines • ▼ Show 20 Linesdef : Pat<(int_nvvm_rotate_right_b64 Int64Regs:$src, Int32Regs:$amt),
(SHF_R_WRAP_B32_REG (GET_LO_INT64 Int64Regs:$src), (SHF_R_WRAP_B32_REG (GET_LO_INT64 Int64Regs:$src),
(GET_HI_INT64 Int64Regs:$src), Int32Regs:$amt), (GET_HI_INT64 Int64Regs:$src), Int32Regs:$amt),
(SHF_R_WRAP_B32_REG (GET_HI_INT64 Int64Regs:$src), (SHF_R_WRAP_B32_REG (GET_HI_INT64 Int64Regs:$src),
(GET_LO_INT64 Int64Regs:$src), Int32Regs:$amt))>, (GET_LO_INT64 Int64Regs:$src), Int32Regs:$amt))>,
Requires<[hasHWROT32]>; Requires<[hasHWROT32]>;
// SW version of rotate 64 // SW version of rotate 64
def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, (i32 imm:$amt)), def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, (i32 imm:$amt)),
(ROT64imm_sw Int64Regs:$src, imm:$amt, (SUB_FRM_32 node:$amt))>, (ROT64imm_sw Int64Regs:$src, imm:$amt, (SUB_FRM_64 node:$amt))>,
Requires<[noHWROT32]>; Requires<[noHWROT32]>;
def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, Int32Regs:$amt), def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, Int32Regs:$amt),
(ROTL64reg_sw Int64Regs:$src, Int32Regs:$amt)>, (ROTL64reg_sw Int64Regs:$src, Int32Regs:$amt)>,
Requires<[noHWROT32]>; Requires<[noHWROT32]>;
def : Pat<(int_nvvm_rotate_right_b64 Int64Regs:$src, (i32 imm:$amt)), def : Pat<(int_nvvm_rotate_right_b64 Int64Regs:$src, (i32 imm:$amt)),
(ROT64imm_sw Int64Regs:$src, (SUB_FRM_64 node:$amt), imm:$amt)>, (ROT64imm_sw Int64Regs:$src, (SUB_FRM_64 node:$amt), imm:$amt)>,
Requires<[noHWROT32]>; Requires<[noHWROT32]>;
def : Pat<(int_nvvm_rotate_right_b64 Int64Regs:$src, Int32Regs:$amt), def : Pat<(int_nvvm_rotate_right_b64 Int64Regs:$src, Int32Regs:$amt),
▲ Show 20 Lines • Show All 4,024 Lines • Show Last 20 Lines

llvm/test/CodeGen/NVPTX/rotate_64.ll

  • This file was added.
; RUN: llc < %s -march=nvptx | FileCheck %s
declare i64 @llvm.nvvm.rotate.b64(i64, i32)
declare i64 @llvm.nvvm.rotate.right.b64(i64, i32)
; CHECK: rotate64
define i64 @rotate64(i64 %a, i32 %b) {
; CHECK: shl.b64 [[LHS:%.*]], [[RD1:%.*]], 3;
; CHECK: shr.b64 [[RHS:%.*]], [[RD1]], 61;
; CHECK: add.u64 [[RD2:%.*]], [[LHS]], [[RHS]];
; CHECK: ret
%val = tail call i64 @llvm.nvvm.rotate.b64(i64 %a, i32 3)
ret i64 %val
}
; CHECK: rotateright64
define i64 @rotateright64(i64 %a, i32 %b) {
; CHECK: shl.b64 [[LHS:%.*]], [[RD1:%.*]], 61;
; CHECK: shr.b64 [[RHS:%.*]], [[RD1]], 3;
; CHECK: add.u64 [[RD2:%.*]], [[LHS]], [[RHS]];
; CHECK: ret
%val = tail call i64 @llvm.nvvm.rotate.right.b64(i64 %a, i32 3)
ret i64 %val
}