RFC: RegAlloc: Avoid repeated calls to freezeReservedRegs

[foad]

Summary

With split register allocation, only call MRI->freezeReservedRegs if
they are not already frozen. This makes a measurable difference on
AMDGPU where regalloc is split in two and
SIRegisterInfo::getReservedRegs is expensive due to the large register
file and many subregs.

I measured a ~5% speed up with:

$ cat empty.ll
define void @f() {

ret void

}
$ perf stat -r 1000 -- llc -march amdgcn -mcpu gfx1030 empty.ll -filetype null

FIXME: The assertion I added fails on a few AArch64 CodeGen tests,
apparently because AArch64RegisterInfo::hasBasePointer changes after
FinalizeISel. How should this be handled? Is the target required to
call freezeReservedRegs again whenever the set of reserved regs might
have changed?

[arsenm]

freezeReservedRegs is actually called 3-5 times. It's first called in finalizeLowering, again in the allocators, and then again in SILowerSGPRSpills.

We may be able to get away without re-freezing the SGPR spills if we make them all live throughout every block

[foad]

and then again in SILowerSGPRSpills

OK but I'm less concerned about that because it only happens if there are some spills, and in any function that's large enough to have spills the fixed cost of getReservedRegs will be a lower proportion of the overall compile time.

[foad]

FIXME: The assertion I added fails on a few AArch64 CodeGen tests,
apparently because AArch64RegisterInfo::hasBasePointer changes after
FinalizeISel.

Digging a little deeper, this is because hasBasePointer depends on the local frame size, which is set up by the LocalStackSlotAllocation pass.

[arsenm]

llvm/lib/CodeGen/RegAllocBase.cpp

66–69

Can this just assert the regs are frozen? Why does anything reach here without having done this already?

[foad]

Simplify.

[foad]

Simplify.

[arsenm]

LGTM

[foad]

In D119436#3412647, @arsenm wrote:

LGTM

Thanks but I can't commit it because I don't know how to fix this:

FIXME: The assertion I added fails on a few AArch64 CodeGen tests,
apparently because AArch64RegisterInfo::hasBasePointer changes after
FinalizeISel. How should this be handled? Is the target required to
call freezeReservedRegs again whenever the set of reserved regs might
have changed?

llvm/lib/CodeGen/RegAllocBase.cpp

66–69

Good point. Simplified accordingly.

llvm/lib/CodeGen/RegAllocBase.cpp

 
 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis,
                         LiveRegMatrix &mat) {
   TRI = &vrm.getTargetRegInfo();
   MRI = &vrm.getRegInfo();
   VRM = &vrm;
   LIS = &lis;
   Matrix = &mat;
+#ifndef NDEBUG
+  BitVector OldReservedRegs(MRI->getReservedRegs());
   MRI->freezeReservedRegs(vrm.getMachineFunction());
+  assert(OldReservedRegs == MRI->getReservedRegs() &&
+         "Frozen reserved regs should not have changed!");
+#endif
   RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
 }
 
 // Visit all the live registers. If they are already assigned to a physical
 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
 // them on the priority queue for later assignment.
 void RegAllocBase::seedLiveRegs() {
   NamedRegionTimer T("seed", "Seed Live Regs", TimerGroupName,