[BOLT] Divide RegularPageSize for X86 and AArch64 cases

[Elvina]

Summary

For AArch64 in some cases/some distributions ld uses 64K alignment of LOAD segments by default.

[yota9]

Some of the aarch64 distros are using 64kb page size, so setting up the page size for 64kb seems to be more universal solution for arm. LGTM, but let's wait for other reviewers.

[maksfb]

I think the proper way to add different page sizes is to add an API to MCSubtargetInfo. There's already API for cache (getCacheSize(), getCacheLineSize(), getCacheAssociativity()), we can introduce the one for pages. What do you think?

bolt/include/bolt/Core/BinaryContext.h

497

Curious - what's the motivation for this change?

[yota9]

@maksfb As I see this is target (CPU) specific API. But we are talking about software-related choice of page size, this is not like the hardware feature, some of the linux distros might use standard 4kb page, some of them are using 64kb pages. So I'm not sure if the MCSubtargetInfo is the right place to add it to. Besides there are pros and cons for each choice of course, but using 64kb alignment will work on every distro, and 4kb won't :)

[maksfb]

There are typically several page sizes supported by a CPU, e.g. 4KiB, 2MiB, 1GiB for x86-64, and I believe this data could be added to MCSubtargetInfo. But you are right, in theory a system could be configured to use virtually any of the available HW options and even use a mixture for the same binary, such as one for "text", another for "data", etc. Ideally, such info could be part of ELF, but alas it is not.

[yota9]

@maksfb Yes, that is exactly what I've meant, thank you! Although the page size might be configured to be any (from the supported by hardware list), currently there are 2 types of them are used for aarch64 by linux in common: it is 4kb and 64kb. Increasing the size to 64kb will cover all of our cases, so I really think it makes sense for us to make it by default for arm.

bolt/include/bolt/Core/BinaryContext.h

497

This is just in order to make it the same type (except const, of course) like RegularPageSize variable, but it is not necessary of course :)

[Elvina]

bolt/include/bolt/Core/BinaryContext.h

497

yep :)

[maksfb]

Could you please add "[BOLT]" to the title?

ld uses 64K alignment of LOAD segments by default.

I wonder if in that case the alignment of the segment will be 0x10000 as well?

bolt/include/bolt/Core/BinaryContext.h

497

The type is still unsigned, but semantics has changed. Let's keep it as a static member.

[Elvina]

Reverted changes for HugePageSize

[Elvina]

In D119267#3313212, @maksfb wrote:

Could you please add "[BOLT]" to the title?

ld uses 64K alignment of LOAD segments by default.

I wonder if in that case the alignment of the segment will be 0x10000 as well?

Sorry for the long silence. Yes, I double-checked, in that case alignment is 0x10000

[maksfb]

LGTM

bolt/include/bolt/Core/BinaryContext.h

public:
   /// Return true if the array of bytes represents a valid code padding.
   bool hasValidCodePadding(const BinaryFunction &BF);
 
   /// Verify padding area between functions, and adjust max function size
   /// accordingly.
   void adjustCodePadding();
 
   /// Regular page size.
-  static constexpr unsigned RegularPageSize = 0x1000;
+  unsigned RegularPageSize{0x1000};
+  static constexpr unsigned RegularPageSizeX86 = 0x1000;
+  static constexpr unsigned RegularPageSizeAArch64 = 0x10000;
 
   /// Huge page size to use.
   static constexpr unsigned HugePageSize = 0x200000;
 
   /// Map address to a constant island owner (constant data in code section)
   std::map<uint64_t, BinaryFunction *> AddressToConstantIslandMap;
 
   /// A map from jump table address to insertion order.  Used for generating
   /// jump table names.
   std::map<uint64_t, size_t> JumpTableIds;
 

bolt/lib/Core/BinaryContext.cpp

BinaryContext::BinaryContext(std::unique_ptr<MCContext> Ctx,
                              std::unique_ptr<MCDisassembler> DisAsm)
     : Ctx(std::move(Ctx)), DwCtx(std::move(DwCtx)),
       TheTriple(std::move(TheTriple)), TheTarget(TheTarget),
       TripleName(TripleName), MCE(std::move(MCE)), MOFI(std::move(MOFI)),
       AsmInfo(std::move(AsmInfo)), MII(std::move(MII)), STI(std::move(STI)),
       InstPrinter(std::move(InstPrinter)), MIA(std::move(MIA)),
       MIB(std::move(MIB)), MRI(std::move(MRI)), DisAsm(std::move(DisAsm)) {
   Relocation::Arch = this->TheTriple->getArch();
+  RegularPageSize = isAArch64() ? RegularPageSizeAArch64 : RegularPageSizeX86;
   PageAlign = opts::NoHugePages ? RegularPageSize : HugePageSize;
 }
 
 BinaryContext::~BinaryContext() {
   for (BinarySection *Section : Sections)
     delete Section;
   for (BinaryFunction *InjectedFunction : InjectedBinaryFunctions)
     delete InjectedFunction;