[x86] enable fast sqrtss tuning for AMD Zen cores

[spatel]

Summary

As discussed in D118534, all of the recent AMD CPUs have relatively fast (<14 cycle latency) "sqrtss" instructions:
https://uops.info/table.html?search=sqrtps&cb_lat=on&cb_tp=on&cb_SNB=on&cb_SKL=on&cb_ZENp=on&cb_ZEN2=on&cb_ZEN3=on&cb_measurements=on&cb_avx=on&cb_sse=on

So we should set this tuning flag to alter codegen of plain "sqrt(X)" expansion (as opposed to reciprocal-sqrt - there is other test coverage for that pattern). The expansion is both slower and less accurate than the hardware instruction.

[lebedev.ri]

llvm/lib/Target/X86/X86.td

1172

Please also add TuningFastVectorFSQRT, i don't see any difference between scalar and vector variants at least on znver3.

[spatel]

llvm/lib/Target/X86/X86.td

1172

Good point. On Zen1, it looks like 256-bit would be split, but that's still recip throughput of 8 cycles, so it's better than the 10+ instructions/cycles in the estimate sequence.

[spatel]

Added fast vector sqrt flag in addition to fast scalar. These have throughput <8 (see uops link in description), so better than the estimate sequence.

[lebedev.ri]

LGTM, thank you.
This should be backported, please file an issue.

llvm/lib/Target/X86/X86.td

list<SubtargetFeature> ZNFeatures = [FeatureADX,
                                        FeatureXSAVE,
                                        FeatureXSAVEC,
                                        FeatureXSAVEOPT,
                                        FeatureXSAVES];
   list<SubtargetFeature> ZNTuning = [TuningFastLZCNT,
                                      TuningFastBEXTR,
                                      TuningFast15ByteNOP,
                                      TuningBranchFusion,
+                                     TuningFastScalarFSQRT,
                                      TuningFastScalarShiftMasks,
                                      TuningFastMOVBE,
                                      TuningSlowSHLD,
                                      TuningInsertVZEROUPPER];
   list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,
                                                   FeatureRDPID,
                                                   FeatureWBNOINVD];
   list<SubtargetFeature> ZN2Tuning = ZNTuning;

llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=nehalem     | FileCheck %s --check-prefixes=NHM
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=sandybridge | FileCheck %s --check-prefixes=FAST-SCALAR,SNB
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=broadwell   | FileCheck %s --check-prefixes=FAST-SCALAR,BDW
 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake     | FileCheck %s --check-prefixes=FAST-SCALAR,SKL
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1      | FileCheck %s --check-prefixes=SLOW-SCALAR,ZN1
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3      | FileCheck %s --check-prefixes=SLOW-SCALAR,ZN3
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1      | FileCheck %s --check-prefixes=FAST-SCALAR,ZN1
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3      | FileCheck %s --check-prefixes=FAST-SCALAR,ZN3
 
 define float @f32_no_daz(float %f) #0 {
 ; NHM-LABEL: f32_no_daz:
 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtss %xmm0, %xmm1
 ; NHM-NEXT:    movaps %xmm0, %xmm2
 ; NHM-NEXT:    mulss %xmm1, %xmm2
 ; NHM-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
 ; NHM-NEXT:    mulss %xmm2, %xmm3
 ; NHM-NEXT:    mulss %xmm1, %xmm2
 ; NHM-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
 ; NHM-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; NHM-NEXT:    mulss %xmm3, %xmm2
 ; NHM-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; NHM-NEXT:    andnps %xmm2, %xmm0
 ; NHM-NEXT:    retq
 ;
 ; FAST-SCALAR-LABEL: f32_no_daz:
 ; FAST-SCALAR:       # %bb.0:
 ; FAST-SCALAR-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
 ; FAST-SCALAR-NEXT:    retq
-;
-; SLOW-SCALAR-LABEL: f32_no_daz:
-; SLOW-SCALAR:       # %bb.0:
-; SLOW-SCALAR-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; SLOW-SCALAR-NEXT:    vbroadcastss {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN]
-; SLOW-SCALAR-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; SLOW-SCALAR-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; SLOW-SCALAR-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; SLOW-SCALAR-NEXT:    vandps %xmm3, %xmm0, %xmm0
-; SLOW-SCALAR-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; SLOW-SCALAR-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; SLOW-SCALAR-NEXT:    vandnps %xmm1, %xmm0, %xmm0
-; SLOW-SCALAR-NEXT:    retq
   %call = tail call fast float @llvm.sqrt.f32(float %f) #2
   ret float %call
 }
 
 define <4 x float> @v4f32_no_daz(<4 x float> %f) #0 {
 ; NHM-LABEL: v4f32_no_daz:
 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtps %xmm0, %xmm1

 ; NHM-NEXT:    cmpeqss %xmm1, %xmm0
 ; NHM-NEXT:    andnps %xmm2, %xmm0
 ; NHM-NEXT:    retq
 ;
 ; FAST-SCALAR-LABEL: f32_daz:
 ; FAST-SCALAR:       # %bb.0:
 ; FAST-SCALAR-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
 ; FAST-SCALAR-NEXT:    retq
-;
-; SLOW-SCALAR-LABEL: f32_daz:
-; SLOW-SCALAR:       # %bb.0:
-; SLOW-SCALAR-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; SLOW-SCALAR-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; SLOW-SCALAR-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; SLOW-SCALAR-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; SLOW-SCALAR-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; SLOW-SCALAR-NEXT:    vxorps %xmm2, %xmm2, %xmm2
-; SLOW-SCALAR-NEXT:    vcmpeqss %xmm2, %xmm0, %xmm0
-; SLOW-SCALAR-NEXT:    vandnps %xmm1, %xmm0, %xmm0
-; SLOW-SCALAR-NEXT:    retq
   %call = tail call fast float @llvm.sqrt.f32(float %f) #2
   ret float %call
 }
 
 define <4 x float> @v4f32_daz(<4 x float> %f) #1 {
 ; NHM-LABEL: v4f32_daz:
 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtps %xmm0, %xmm1