[AArch64] Do not use ABI alignment for mops.memset.tag

[nikic]

Summary

Pointer element types do not imply that the pointer is ABI aligned. We should be using either an explicit align attribute here, or fall by to an alignment of 1.

This fixes a new element type access introduced in D117764.

[dmgreen]

Thanks. Can you add a test case for a @llvm.aarch64.mops.memset.tag with an align attribute on the operand?

[nikic]

Add test with align attribute. I don't think this has any actual effect, at least I don't see how the lowering would depend on alignment.

[dmgreen]

Hmm. I was expecting to be able to test this by printing the MIR and inspecting the operand, but it appears that the alignment gets lost as we convert to a machine node. I'm not sure why.

Like you said the alignment won't be used for much though, so I think this LGTM as-is. So long as we have a test that the align operand isn't doing anything funny, that Ok on its own. Thanks.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

case Intrinsic::aarch64_sve_stnt1: {
     Info.offset = 0;
     Info.align = DL.getABITypeAlign(PtrTy->getPointerElementType());
     Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MONonTemporal;
     return true;
   }
   case Intrinsic::aarch64_mops_memset_tag: {
     Value *Dst = I.getArgOperand(0);
     Value *Val = I.getArgOperand(1);
-    PointerType *PtrTy = cast<PointerType>(Dst->getType());
     Info.opc = ISD::INTRINSIC_W_CHAIN;
     Info.memVT = MVT::getVT(Val->getType());
     Info.ptrVal = Dst;
     Info.offset = 0;
-    Info.align = DL.getABITypeAlign(PtrTy->getPointerElementType());
+    Info.align = I.getParamAlign(0).valueOrOne();
     Info.flags = MachineMemOperand::MOStore;
     // The size of the memory being operated on is unknown at this point
     Info.size = MemoryLocation::UnknownSize;
     return true;
   }
   default:
     break;
   }

llvm/test/CodeGen/AArch64/aarch64-mops-mte.ll

 ; SDAG-NEXT:    setgm [x0]!, x1!, x2
 ; SDAG-NEXT:    setge [x0]!, x1!, x2
 ; SDAG-NEXT:    ret
 entry:
   %value_trunc = trunc i32 %value to i8
   %r = tail call i8* @llvm.aarch64.mops.memset.tag(i8* %dst, i8 %value_trunc, i64 %size)
   ret i8* %r
 }
+
+define i8* @memset_tagged_size_aligned(i8* %dst, i64 %size, i32 %value) {
+; GISel-O0-LABEL: memset_tagged_size_aligned:
+; GISel-O0:       // %bb.0: // %entry
+; GISel-O0-NEXT:    // implicit-def: $x8
+; GISel-O0-NEXT:    mov w8, w2
+; GISel-O0-NEXT:    setgp [x0]!, x1!, x8
+; GISel-O0-NEXT:    setgm [x0]!, x1!, x8
+; GISel-O0-NEXT:    setge [x0]!, x1!, x8
+; GISel-O0-NEXT:    ret
+;
+; GISel-LABEL: memset_tagged_size_aligned:
+; GISel:       // %bb.0: // %entry
+; GISel-NEXT:    // kill: def $w2 killed $w2 def $x2
+; GISel-NEXT:    setgp [x0]!, x1!, x2
+; GISel-NEXT:    setgm [x0]!, x1!, x2
+; GISel-NEXT:    setge [x0]!, x1!, x2
+; GISel-NEXT:    ret
+;
+; SDAG-LABEL: memset_tagged_size_aligned:
+; SDAG:       // %bb.0: // %entry
+; SDAG-NEXT:    // kill: def $w2 killed $w2 def $x2
+; SDAG-NEXT:    setgp [x0]!, x1!, x2
+; SDAG-NEXT:    setgm [x0]!, x1!, x2
+; SDAG-NEXT:    setge [x0]!, x1!, x2
+; SDAG-NEXT:    ret
+entry:
+  %value_trunc = trunc i32 %value to i8
+  %r = tail call i8* @llvm.aarch64.mops.memset.tag(i8* align 16 %dst, i8 %value_trunc, i64 %size)
+  ret i8* %r
+}