[RISCV][MC] Guard vmulh, vsmul correctly

[eopXD]

Summary

According to v-spec 1.0, these 2 instructions shall be enabled in V ext.
but not in Zve ext. This patch addresses it.

Credits to Jianjian as he pointed this out in D117854.

[craig.topper]

The instructions are only not supported with SEW=64. Smaller SEWs are supported. The MC layer doesn’t know about SEW.

[eopXD]

Should not guard these instructions in MC, moving to D117913 to guard in clang.

llvm/lib/Target/RISCV/RISCV.td

def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
           "'V' (Vector Extension for Application Processors) or 'Zve64x' "
           "(Vector Extensions for Embedded Processors)">;
 def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
       AssemblerPredicate<
           (any_of FeatureStdExtZve32f),
           "'V' (Vector Extension for Application Processors), 'Zve32f', "
           "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">;
 
+def HasVInstructionMULHSMUL : Predicate<"Subtarget->hasVInstructionMULHSMUL()">,
+      AssemblerPredicate<
+          (any_of FeatureStdExtV),
+          "'V' (Vector Extension for Application Processors)">;
+
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of Feature64Bit),
                        "RV64I Base Instruction Set">;
 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of (not Feature64Bit)),
                        "RV32I Base Instruction Set">;

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 // Vector Integer Min/Max Instructions
 defm VMINU_V : VCMP_IV_V_X<"vminu", 0b000100>;
 defm VMIN_V : VCMP_IV_V_X<"vmin", 0b000101>;
 defm VMAXU_V : VCMP_IV_V_X<"vmaxu", 0b000110>;
 defm VMAX_V : VCMP_IV_V_X<"vmax", 0b000111>;
 
 // Vector Single-Width Integer Multiply Instructions
 defm VMUL_V : VMUL_MV_V_X<"vmul", 0b100101>;
-defm VMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>;
-defm VMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>;
-defm VMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>;
 
 // Vector Integer Divide Instructions
 defm VDIVU_V : VDIV_MV_V_X<"vdivu", 0b100000>;
 defm VDIV_V : VDIV_MV_V_X<"vdiv", 0b100001>;
 defm VREMU_V : VDIV_MV_V_X<"vremu", 0b100010>;
 defm VREM_V : VDIV_MV_V_X<"vrem", 0b100011>;
 
 // Vector Widening Integer Multiply Instructions

 defm VSSUB_V : VSALU_IV_V_X<"vssub", 0b100011>;
 
 // Vector Single-Width Averaging Add and Subtract
 defm VAADDU_V : VAALU_MV_V_X<"vaaddu", 0b001000>;
 defm VAADD_V : VAALU_MV_V_X<"vaadd", 0b001001>;
 defm VASUBU_V : VAALU_MV_V_X<"vasubu", 0b001010>;
 defm VASUB_V : VAALU_MV_V_X<"vasub", 0b001011>;
 
-// Vector Single-Width Fractional Multiply with Rounding and Saturation
-defm VSMUL_V : VSMUL_IV_V_X<"vsmul", 0b100111>;
-
 // Vector Single-Width Scaling Shift Instructions
 defm VSSRL_V : VSSHF_IV_V_X_I<"vssrl", 0b101010, uimm5>;
 defm VSSRA_V : VSSHF_IV_V_X_I<"vssra", 0b101011, uimm5>;
 
 // Vector Narrowing Fixed-Point Clip Instructions
 let Constraints = "@earlyclobber $vd" in {
 defm VNCLIPU_W : VNCLP_IV_V_X_I<"vnclipu", 0b101110, uimm5, "w">;
 defm VNCLIP_W : VNCLP_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">;
def VSUXSEG#nf#EI64_V :
       VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, LSWidth64,
                            "vsuxseg"#nf#"ei64.v">;
     def VSOXSEG#nf#EI64_V :
       VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth64,
                            "vsoxseg"#nf#"ei64.v">;
   }
 } // Predicates = [HasVInstructionsI64, IsRV64]
 
+let Predicates = [HasVInstructionMULHSMUL] in {
+  // NOTE: According to v-spec 1.0:
+  // All Zve* extensions support all vector fixed-point arithmetic
+  // instructions (Vector Fixed-Point Arithmetic Instructions), except that
+  // vsmul.vv and vsmul.vx are not supported for EEW=64 in Zve64*.
+
+  // Vector Single-Width Integer Multiply Instructions
+  defm VMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>;
+  defm VMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>;
+  defm VMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>;
+
+  // Vector Single-Width Fractional Multiply with Rounding and Saturation
+  defm VSMUL_V : VSMUL_IV_V_X<"vsmul", 0b100111>;
+} // Predicates = [HasVInstructionMULHSMUL]
+
 include "RISCVInstrInfoVPseudos.td"

llvm/lib/Target/RISCV/RISCVSubtarget.h

public:
   bool hasVInstructionsI64() const { return HasStdExtZve64x; }
   bool hasVInstructionsF16() const { return HasStdExtZve32f && HasStdExtZfh; }
   // FIXME: Consider Zfinx in the future
   bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; }
   // FIXME: Consider Zdinx in the future
   bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; }
   // F16 and F64 both require F32.
   bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
+  bool hasVInstructionMULHSMUL() const { return HasStdExtV; }
   unsigned getMaxInterleaveFactor() const {
     return hasVInstructions() ? MaxInterleaveFactor : 1;
   }
 
 protected:
   // GlobalISel related APIs.
   std::unique_ptr<CallLowering> CallLoweringInfo;
   std::unique_ptr<InstructionSelector> InstSelector;

llvm/test/MC/RISCV/rvv/mul.s

 # CHECK-UNKNOWN: 57 64 45 94 <unknown>
 
 vmul.vx v8, v4, a0
 # CHECK-INST: vmul.vx v8, v4, a0
 # CHECK-ENCODING: [0x57,0x64,0x45,0x96]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
 # CHECK-UNKNOWN: 57 64 45 96 <unknown>
 
-vmulh.vv v8, v4, v20, v0.t
-# CHECK-INST: vmulh.vv v8, v4, v20, v0.t
-# CHECK-ENCODING: [0x57,0x24,0x4a,0x9c]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
-# CHECK-UNKNOWN: 57 24 4a 9c <unknown>
-
-vmulh.vv v8, v4, v20
-# CHECK-INST: vmulh.vv v8, v4, v20
-# CHECK-ENCODING: [0x57,0x24,0x4a,0x9e]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
-# CHECK-UNKNOWN: 57 24 4a 9e <unknown>
-
-vmulh.vx v8, v4, a0, v0.t
-# CHECK-INST: vmulh.vx v8, v4, a0, v0.t
-# CHECK-ENCODING: [0x57,0x64,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
-# CHECK-UNKNOWN: 57 64 45 9c <unknown>
-
-vmulh.vx v8, v4, a0
-# CHECK-INST: vmulh.vx v8, v4, a0
-# CHECK-ENCODING: [0x57,0x64,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
-# CHECK-UNKNOWN: 57 64 45 9e <unknown>
-
-vmulhu.vv v8, v4, v20, v0.t
-# CHECK-INST: vmulhu.vv v8, v4, v20, v0.t
-# CHECK-ENCODING: [0x57,0x24,0x4a,0x90]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
-# CHECK-UNKNOWN: 57 24 4a 90 <unknown>
-
-vmulhu.vv v8, v4, v20
-# CHECK-INST: vmulhu.vv v8, v4, v20
-# CHECK-ENCODING: [0x57,0x24,0x4a,0x92]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
-# CHECK-UNKNOWN: 57 24 4a 92 <unknown>
-
-vmulhu.vx v8, v4, a0, v0.t
-# CHECK-INST: vmulhu.vx v8, v4, a0, v0.t
-# CHECK-ENCODING: [0x57,0x64,0x45,0x90]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
-# CHECK-UNKNOWN: 57 64 45 90 <unknown>
-
-vmulhu.vx v8, v4, a0
-# CHECK-INST: vmulhu.vx v8, v4, a0
-# CHECK-ENCODING: [0x57,0x64,0x45,0x92]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
-# CHECK-UNKNOWN: 57 64 45 92 <unknown>
-
-vmulhsu.vv v8, v4, v20, v0.t
-# CHECK-INST: vmulhsu.vv v8, v4, v20, v0.t
-# CHECK-ENCODING: [0x57,0x24,0x4a,0x98]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
-# CHECK-UNKNOWN: 57 24 4a 98 <unknown>
-
-vmulhsu.vv v8, v4, v20
-# CHECK-INST: vmulhsu.vv v8, v4, v20
-# CHECK-ENCODING: [0x57,0x24,0x4a,0x9a]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
-# CHECK-UNKNOWN: 57 24 4a 9a <unknown>
-
-vmulhsu.vx v8, v4, a0, v0.t
-# CHECK-INST: vmulhsu.vx v8, v4, a0, v0.t
-# CHECK-ENCODING: [0x57,0x64,0x45,0x98]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
-# CHECK-UNKNOWN: 57 64 45 98 <unknown>
-
-vmulhsu.vx v8, v4, a0
-# CHECK-INST: vmulhsu.vx v8, v4, a0
-# CHECK-ENCODING: [0x57,0x64,0x45,0x9a]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
-# CHECK-UNKNOWN: 57 64 45 9a <unknown>
-
 vwmul.vv v8, v4, v20, v0.t
 # CHECK-INST: vwmul.vv v8, v4, v20, v0.t
 # CHECK-ENCODING: [0x57,0x24,0x4a,0xec]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
 # CHECK-UNKNOWN: 57 24 4a ec <unknown>
 
 vwmul.vv v8, v4, v20
 # CHECK-INST: vwmul.vv v8, v4, v20

 # CHECK-INST: vwmulsu.vx v8, v4, a0
 # CHECK-ENCODING: [0x57,0x64,0x45,0xea]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
 # CHECK-UNKNOWN: 57 64 45 ea <unknown>
 
 vsmul.vv v8, v4, v20, v0.t
 # CHECK-INST: vsmul.vv v8, v4, v20, v0.t
 # CHECK-ENCODING: [0x57,0x04,0x4a,0x9c]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
 # CHECK-UNKNOWN: 57 04 4a 9c <unknown>
 
 vsmul.vv v8, v4, v20
 # CHECK-INST: vsmul.vv v8, v4, v20
 # CHECK-ENCODING: [0x57,0x04,0x4a,0x9e]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
 # CHECK-UNKNOWN: 57 04 4a 9e <unknown>
 
 vsmul.vx v8, v4, a0, v0.t
 # CHECK-INST: vsmul.vx v8, v4, a0, v0.t
 # CHECK-ENCODING: [0x57,0x44,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
 # CHECK-UNKNOWN: 57 44 45 9c <unknown>
 
 vsmul.vx v8, v4, a0
 # CHECK-INST: vsmul.vx v8, v4, a0
 # CHECK-ENCODING: [0x57,0x44,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
 # CHECK-UNKNOWN: 57 44 45 9e <unknown>
+
+vmulh.vv v8, v4, v20, v0.t
+# CHECK-INST: vmulh.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
+# CHECK-UNKNOWN: 57 24 4a 9c <unknown>
+
+vmulh.vv v8, v4, v20
+# CHECK-INST: vmulh.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
+# CHECK-UNKNOWN: 57 24 4a 9e <unknown>
+
+vmulh.vx v8, v4, a0, v0.t
+# CHECK-INST: vmulh.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
+# CHECK-UNKNOWN: 57 64 45 9c <unknown>
+
+vmulh.vx v8, v4, a0
+# CHECK-INST: vmulh.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
+# CHECK-UNKNOWN: 57 64 45 9e <unknown>
+
+vmulhu.vv v8, v4, v20, v0.t
+# CHECK-INST: vmulhu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
+# CHECK-UNKNOWN: 57 24 4a 90 <unknown>
+
+vmulhu.vv v8, v4, v20
+# CHECK-INST: vmulhu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
+# CHECK-UNKNOWN: 57 24 4a 92 <unknown>
+
+vmulhu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmulhu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
+# CHECK-UNKNOWN: 57 64 45 90 <unknown>
+
+vmulhu.vx v8, v4, a0
+# CHECK-INST: vmulhu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
+# CHECK-UNKNOWN: 57 64 45 92 <unknown>
+
+vmulhsu.vv v8, v4, v20, v0.t
+# CHECK-INST: vmulhsu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x98]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
+# CHECK-UNKNOWN: 57 24 4a 98 <unknown>
+
+vmulhsu.vv v8, v4, v20
+# CHECK-INST: vmulhsu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x9a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
+# CHECK-UNKNOWN: 57 24 4a 9a <unknown>
+
+vmulhsu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmulhsu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x98]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
+# CHECK-UNKNOWN: 57 64 45 98 <unknown>
+
+vmulhsu.vx v8, v4, a0
+# CHECK-INST: vmulhsu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x9a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors)
+# CHECK-UNKNOWN: 57 64 45 9a <unknown>