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[AArch64] Remove PRBAR0_ELn and PRLAR0_ELn sysregs.
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Authored by simon_tatham on Jan 20 2022, 1:47 AM.

Details

Summary

The Armv8-R.64 architecture defines numbered MPU region registers with
indices 1-15, not 0-15. So there's no such register as PRBAR0_EL2 or
PRLAR0_EL1 (for example). The encodings that they would occupy are
used for the unnumbered PRBAR_ELn and PRLAR_ELn registers.

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Event Timeline

simon_tatham created this revision.Jan 20 2022, 1:47 AM
simon_tatham requested review of this revision.Jan 20 2022, 1:47 AM
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labrinea accepted this revision.Jan 20 2022, 5:18 AM

Indeed the reference manual suggests that the <n> sysreg names are in the range of 1-15:

  • G1.3.18 PRBAR<n>_EL1, Protection Region Base Address Register n (EL1), n = 1 - 15
  • G1.3.19 PRBAR<n>_EL2, Protection Region Base Address Register n (EL2), n = 1 - 15
  • G1.3.24 PRLAR<n>_EL1, Protection Region Limit Address Register n (EL1), n = 1 - 15
  • G1.3.25 PRLAR<n>_EL2, Protection Region Limit Address Register n (EL2), n = 1 - 15
This revision is now accepted and ready to land.Jan 20 2022, 5:18 AM
This revision was landed with ongoing or failed builds.Jan 20 2022, 5:38 AM
This revision was automatically updated to reflect the committed changes.